CN110754042A - 信息处理的方法和通信装置 - Google Patents
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- H—ELECTRICITY
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1168—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
- H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
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- H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
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- H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
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Abstract
一种编码方法,装置、通信设备和通信系统。该方法包括:使用低密度奇偶校验LDPC矩阵对输入比特序列进行编码;其中,所述LDPC矩阵是基于基图得到的,所述基图包括子矩阵A、B、C、D和E,其中,所述子矩阵A为mA行nA列的矩阵,mA、nA为正整数,且4≤mA≤7,nA=10;所述子矩阵B为mA行mA列的矩阵,所述子矩阵B包括权重为3的列和双对角结构的子矩阵B’;所述子矩阵D包括矩阵F中mD行,所述矩阵F为mF行(mA+nA)列的矩阵,mD、mF为正整数,0≤mD≤mF,35≤mF≤38;所述子矩阵C为mA行mD列的全0矩阵;所述子矩阵E为mD行mD列的单位矩阵。该编码方法、装置、通信设备和通信系统,能够支持多种长度的信息比特序列的编码需求。
Description
PCT国内申请,说明书已公开。
Claims (26)
- PCT国内申请,权利要求书已公开。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010009164.6A CN111416625B (zh) | 2017-06-15 | 2017-07-13 | 信息处理的方法和通信装置 |
| CN202410657104.3A CN119602808A (zh) | 2017-06-15 | 2017-07-13 | 信息处理的方法、装置和通信设备 |
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| CN201710454030.3A CN109150191B (zh) | 2017-06-15 | 2017-06-15 | 信息处理的方法、装置和通信设备 |
| CN2017104540303 | 2017-06-15 | ||
| CN2017105030562 | 2017-06-27 | ||
| CN201710503056 | 2017-06-27 | ||
| PCT/CN2017/092878 WO2018227681A1 (zh) | 2017-06-15 | 2017-07-13 | 信息处理的方法和通信装置 |
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| CN202410657104.3A Division CN119602808A (zh) | 2017-06-15 | 2017-07-13 | 信息处理的方法、装置和通信设备 |
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| CN110754042A true CN110754042A (zh) | 2020-02-04 |
| CN110754042B CN110754042B (zh) | 2024-06-04 |
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| Country | Link |
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| US (5) | US10742235B2 (zh) |
| EP (2) | EP3588786B1 (zh) |
| JP (2) | JP6820438B2 (zh) |
| KR (1) | KR102194029B1 (zh) |
| CN (3) | CN111416625B (zh) |
| AU (1) | AU2017418080B9 (zh) |
| BR (1) | BR112019020158B1 (zh) |
| CA (1) | CA3055231C (zh) |
| RU (1) | RU2740154C1 (zh) |
| WO (2) | WO2018227681A1 (zh) |
| ZA (1) | ZA201906314B (zh) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112821895A (zh) * | 2021-04-16 | 2021-05-18 | 成都戎星科技有限公司 | 一种实现信号高误码率下的编码识别方法 |
| WO2025065449A1 (zh) * | 2023-09-27 | 2025-04-03 | 华为技术有限公司 | 序列传输方法及装置 |
| WO2025092569A1 (zh) * | 2023-10-30 | 2025-05-08 | 华为技术有限公司 | 一种基于ldpc码的通信方法和通信装置 |
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| US10469104B2 (en) | 2016-06-14 | 2019-11-05 | Qualcomm Incorporated | Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes |
| US10312939B2 (en) | 2017-06-10 | 2019-06-04 | Qualcomm Incorporated | Communication techniques involving pairwise orthogonality of adjacent rows in LPDC code |
| AU2017418080B9 (en) | 2017-06-15 | 2021-01-28 | Huawei Technologies Co., Ltd. | Information processing method and communication apparatus |
| US12476733B2 (en) | 2017-06-19 | 2025-11-18 | Qualcomm Incorporated | Communication techniques with self-decodable redundancy versions (RVs) using systematic codes |
| CN109150197B (zh) | 2017-06-27 | 2024-05-14 | 华为技术有限公司 | 信息处理的方法、装置和通信设备 |
| CN110832799B (zh) | 2017-07-07 | 2021-04-02 | 高通股份有限公司 | 应用低密度奇偶校验码基图选择的通信技术 |
| US11791938B2 (en) * | 2019-09-26 | 2023-10-17 | Nvidia Corporation | Parity check decoding |
| US11640255B2 (en) * | 2020-11-19 | 2023-05-02 | Macronix International Co., Ltd. | Memory device and operation method thereof |
| DE112022000278T5 (de) * | 2021-01-20 | 2024-01-18 | Nvidia Corporation | Verfahren zur durchführung einer min-sum-decodierung von qc-ldpc-codewörtern von signaldaten zur drahtlosen kommunikation |
| US12395189B2 (en) * | 2021-01-20 | 2025-08-19 | NVIDIA Technologies, Inc. | Technique to perform decoding of wireless communications signal data |
| CN115913252A (zh) * | 2021-09-30 | 2023-04-04 | 华为技术有限公司 | 编码方法、译码方法及装置 |
| CN115102555B (zh) | 2022-06-30 | 2025-01-24 | 北京奕斯伟计算技术股份有限公司 | 信道编译码方法及处理装置、通信方法及装置 |
| CN115173868A (zh) | 2022-06-30 | 2022-10-11 | 北京奕斯伟计算技术股份有限公司 | 构建方法及处理装置、存储介质、编译码方法 |
| CN115102556B (zh) * | 2022-06-30 | 2025-09-16 | 北京奕斯伟计算技术股份有限公司 | 构建基矩阵的方法及处理装置、存储介质 |
| CN120858528A (zh) * | 2023-03-03 | 2025-10-28 | 华为技术有限公司 | 一种编码和译码方法及装置 |
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