CN110534428B - Method for manufacturing metal layer structure, semiconductor device and method for manufacturing semiconductor device - Google Patents
Method for manufacturing metal layer structure, semiconductor device and method for manufacturing semiconductor device Download PDFInfo
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- CN110534428B CN110534428B CN201910838252.4A CN201910838252A CN110534428B CN 110534428 B CN110534428 B CN 110534428B CN 201910838252 A CN201910838252 A CN 201910838252A CN 110534428 B CN110534428 B CN 110534428B
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- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
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- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- Chemical & Material Sciences (AREA)
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Abstract
The invention provides a manufacturing method of a metal layer structure, a semiconductor device and a manufacturing method thereof, wherein the manufacturing method of the metal layer structure comprises the following steps: providing a wafer; forming a metal film layer on the wafer, wherein the temperature of the metal film layer is higher than the solid solution temperature of the material of the metal film layer; cooling the metal film layer; detecting whether the impurity defects in the metal film layer exceed the specification or not, and if the impurity defects in the metal film layer exceed the specification, performing impurity removal treatment on the metal film layer to enable the impurity defects in the metal film layer not to exceed the specification; and if the impurity defects in the metal film layer do not exceed the specification, etching the metal film layer to form the metal layer structure. According to the technical scheme, the impurity defects in the metal layer structure are controlled within the specification, and the influence on the performance of the metal layer structure is further avoided.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a method for manufacturing a metal layer structure, a semiconductor device, and a method for manufacturing the semiconductor device.
Background
During the wafer manufacturing process, various abnormalities may be encountered in the aluminum plating machine during production, which may cause a shutdown. For the wafers in the chamber of the aluminum plating machine, the wafers are generally fed down after the completion of the plating process as soon as possible, but inevitably, some of the wafers in aluminum plating cannot complete the plating process in a short time. Research shows that when the wafer in aluminum plating stays in the aluminum plating machine during shutdown for more than 20min and is not subjected to additional plating, serious impurity residues are generated on the aluminum film structure formed after the subsequent etching process, that is, the size and/or the number of the residual impurities exceed the specification, as shown in fig. 1a, a large number of impurity defects D1 exceeding the specification are generated on the aluminum film structure plated on the wafer, and the performance of the finally formed aluminum film structure is further affected.
Therefore, how to improve the problem of out-of-specification impurities generated on the aluminum film structure produced in the abnormal aluminum plating machine to avoid affecting the performance of the aluminum film structure is a problem that needs to be solved at present.
Disclosure of Invention
The invention aims to provide a manufacturing method of a metal layer structure, a semiconductor device and a manufacturing method thereof, which can control the impurity defects in the metal layer structure within the specification and further avoid influencing the performance of the metal layer structure.
To achieve the above object, the present invention provides a method for manufacturing a metal layer structure,
providing a wafer;
forming a metal film layer on the wafer, wherein the temperature of the metal film layer is higher than the solid solution temperature of the material of the metal film layer;
cooling the metal film layer; and the number of the first and second groups,
detecting whether the impurity defects in the metal film layer exceed the specification or not, and if the impurity defects in the metal film layer exceed the specification, performing impurity removal treatment on the metal film layer to enable the impurity defects in the metal film layer not to exceed the specification; and if the impurity defects in the metal film layer do not exceed the specification, etching the metal film layer to form a metal layer structure.
Optionally, the metal layer structure includes a metal interconnection structure, a plate of a resistor or a plate of a capacitor.
Optionally, the metal film layer is made of one or an alloy of at least two of aluminum, copper, tungsten, nickel, gold, silver and titanium.
Optionally, the metal film layer is formed on the wafer by sputtering plating, the material of the metal film layer includes an alloy composed of aluminum and copper, and the temperature of the metal film layer is not less than 300 ℃.
Optionally, if the impurity defect in the metal film layer exceeds the specification, the step of performing impurity removal processing on the metal film layer includes: directly annealing the metal film layer; or, reforming the metal film layer on the wafer, and annealing the reformed metal film layer.
Optionally, the annealing includes: the metal film layer is maintained for a certain time at the temperature not less than the solid solution temperature of the material of the metal film layer, and then the metal film layer is rapidly cooled to the room temperature.
Optionally, the rapidly cooling the metal film layer to room temperature includes cooling by a two-stage cooling method.
Optionally, before forming the metal film layer on the wafer, a diffusion barrier layer is formed on the wafer.
The present invention also provides a method for manufacturing a semiconductor device, comprising: the metal layer structure is formed on a wafer by adopting the manufacturing method of the metal layer structure provided by the invention.
The present invention also provides a semiconductor device comprising: the manufacturing method of the metal layer structure provided by the invention is adopted to manufacture the metal layer structure, and the metal layer structure is formed on a wafer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. according to the manufacturing method of the metal layer structure, the metal film layer with the temperature higher than the solid solution temperature of the material of the metal film layer is formed on the wafer, the metal film layer is cooled, whether the impurity defects in the metal film layer exceed the specification or not is detected, and the metal film layer with the impurity defects exceeding the specification is subjected to impurity removal treatment, so that the impurity defects in the metal film layer are controlled within the specification; further, the metal film layer with the impurity defects within the specification is etched to form the metal layer structure, so that the impurity defects in the metal layer structure are also controlled within the specification, and the performance of the metal layer structure is prevented from being influenced.
2. According to the manufacturing method of the semiconductor device, the metal layer structure is formed on the wafer by adopting the manufacturing method of the metal layer structure provided by the invention, so that the metal layer structure has a uniform structure or surface, and the performance of the semiconductor device is improved.
3. According to the semiconductor device, the metal layer structure is formed on a wafer by adopting the manufacturing method of the metal layer structure provided by the invention, so that the metal layer structure has a uniform structure or surface, and the performance of the semiconductor device is improved.
Drawings
FIG. 1a is a schematic diagram showing the distribution of impurities remaining on an aluminum film structure;
FIG. 1b is a scanning electron microscope image of impurities remaining on the aluminum film structure;
FIG. 2 is a flow chart of a method of fabricating a metal layer structure according to an embodiment of the present invention;
fig. 3 is a schematic view of the distribution of impurity defects on the improved metal layer structure.
Detailed Description
The research shows that the reason for generating impurity residue on the aluminum film structure is as follows: in the technical process of sputtering aluminum plating, the adopted aluminum target contains 0.5 percent of copper, the temperature of the surface of the wafer can be raised to be more than 300 ℃ under the action of plasma of the target sputtered on the surface of the wafer, the temperature is the solid solution temperature of aluminum/copper, and the aluminum film structure formed at the temperature has good uniformity; when the aluminum plating machine in production is abnormal and stops aluminum plating, the surface temperature of the wafer in the aluminum plating machine chamber is slowly reduced to below 300 ℃ within about 20min, so that copper aggregation occurs on the aluminum film structure plated on the surface of the wafer to form a large amount of out-of-specification Al2Cu impurities, which in turn cause a large amount of Al to be accumulated on the aluminum film structure formed after the compensation plating and etching processes2Cu impurities remain, as shown in FIG. 1b, residual aggregated Al2The Cu impurity defect D2 is in a convex state on the aluminum film structure, so that the surface of the aluminum film structure is not uniform, and the performance of the aluminum film structure is influenced. Therefore, the invention provides a manufacturing method of a metal layer structure and a manufacturing method of a semiconductor device, which can improve impurity defects in the metal layer structure and further avoid influencing the performance of the metal layer structure.
In order to make the objects, advantages and features of the present invention more clear, the following will explain the manufacturing method of the metal layer structure and the semiconductor device and the manufacturing method thereof in detail with reference to fig. 2 to 3. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
An embodiment of the present invention provides a method for manufacturing a metal layer structure, and referring to fig. 2, fig. 2 is a flowchart of a method for manufacturing a metal layer structure according to an embodiment of the present invention, where the method for manufacturing a metal layer structure includes:
step S1, providing a wafer;
step S2, forming a metal film layer on the wafer, wherein the temperature of the metal film layer is higher than the solid solution temperature of the material of the metal film layer;
step S3, cooling the metal film layer;
step S4, detecting whether the impurity defect in the metal film layer exceeds the specification, if the impurity defect in the metal film layer exceeds the specification, removing impurities from the metal film layer to ensure that the impurity defect in the metal film layer does not exceed the specification; and if the impurity defects in the metal film layer do not exceed the specification, etching the metal film layer to form a metal layer structure.
The method for manufacturing the metal layer structure provided in this embodiment is described in more detail as follows:
according to step S1, a wafer is provided. The wafer may include a substrate and a film structure formed on the substrate. The substrate may be any suitable substrate known to those skilled in the art, and may be, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and further includes a multilayer structure composed of these semiconductors, or may be Silicon On Insulator (SOI), silicon on insulator (SSOI), silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), or may be Double-Side Polished silicon Wafers (DSP), or may be a ceramic substrate such as alumina, quartz, or a glass substrate. The film layer structure formed on the wafer is, for example, a gate structure or a dielectric layer, and the gate structure may be a polysilicon gate or a metal gate. In the present invention, the structure of the wafer is not limited, and an appropriate wafer may be selected according to a device to be formed.
According to step S2, a metal film is formed on the wafer, wherein the temperature of the metal film is higher than the solid solution temperature of the material of the metal film. The method for forming the metal film layer on the wafer can comprise the following steps: vacuum evaporation, sputtering plating or ion plating, wherein the vacuum evaporation is to heat and evaporate a metal material to be evaporated in a vacuum cavity, so that evaporated atoms or atomic groups are condensed on a wafer with a lower temperature to form the metal film layer; the sputtering plating is to bombard the surface of a solid target (namely a metal material) by using enough energy obtained by charged ions under the action of an electromagnetic field, and plasma is sputtered from the surface of the target and is emitted to the surface of a wafer with certain kinetic energy to form a metal film layer on the wafer; the ion plating is to partially separate gas or evaporated substance by gas discharge under vacuum condition, and deposit the evaporated substance or its reactant on the wafer while the gas ion or evaporated substance particle is bombarded to form the metal film layer.
In the process of forming the metal film layer by the methods, the metal film layer and the wafer have higher temperature due to factors such as heating in a reaction cavity or plasma bombardment in the reaction process, and the higher temperature is higher than the solid solution temperature of the material of the metal film layer. The temperature of the metal film layer is higher than the solid solution temperature of the material of the metal film layer, so that the structure or the surface of the formed metal film layer is more uniform, and the temperature of the surface of the metal film layer is different according to different methods for forming the metal film layer and different materials of the formed metal film layer. The material of the metal film layer may include one or an alloy of at least two of aluminum, copper, tungsten, nickel, gold, silver, titanium and the like. For example, when the material of the metal film layer is an alloy composed of aluminum and copper, the metal film layer may be formed on the wafer by a sputtering method, wherein an aluminum target material used for sputtering contains 0.5% of copper, and when plasma of aluminum and copper is sputtered onto the surface of the wafer, the surface temperature of the metal film layer and the wafer is raised to more than 300 ℃, that is, the solid solution temperature of the alloy composed of aluminum and copper is reached, so that the structure or the surface of the formed metal film layer is kept uniform at the temperature.
In addition, before forming the metal film layer on the wafer, a diffusion barrier layer may be formed on the wafer. The diffusion barrier layer can block metal atoms in the metal film layer from diffusing, and particularly when a metal layer structure formed by etching the metal film layer is a metal interconnection structure, electrons moving in the opposite direction of an electric field can exchange momentum with the metal atoms, so that the metal atoms generate mass transport dominated by atomic diffusion, namely, an electromigration phenomenon is generated, the electromigration phenomenon can cause the metal interconnection structure to form defects such as voids (void) or bulges (hillock) due to diffusion and movement of the metal atoms, and even open circuit or short circuit can occur in a region with serious defects, so that the existence of the diffusion barrier layer is particularly important. The diffusion barrier layer may be a single layer or at least two layers, the material of the diffusion barrier layer may include one or a combination of at least two of tantalum, tantalum nitride, titanium nitride, tungsten nitride, and tantalum silicon nitride, and the diffusion barrier layer may be formed by using a thin film deposition technique such as physical vapor deposition or chemical vapor deposition.
The metal film layer is cooled according to step S3. According to the above description of step S2, the temperature of the formed metal film layer is higher than the solid solution temperature of the material of the metal film layer, so that the metal film layer needs to be cooled to room temperature (e.g. 20 ℃ to 30 ℃) after the metal film layer is formed, so as to perform the subsequent process. The metal film layer can be rapidly cooled to room temperature within a time less than 2min by introducing a cooling gas such as nitrogen into the cooling chamber, so that the structural state of the cooled metal film layer is kept as consistent as possible with the structural state of the metal film layer with the temperature higher than the solid solution temperature of the material of the metal film layer in the step S2, that is, the state of the metal film layer with a uniform structure or surface in the step S2 is fixed by rapid cooling, so that the structure or surface of the cooled metal film layer is kept as uniform as possible, and further, the impurity defects in the metal film layer are controlled within the specification as much as possible, so as to improve the problem of the impurity defects generated in the metal film layer. It should be understood that the cooling manner referred to herein is only an example of the embodiment, and in the actual operation process, the introduced cooling gas and the cooling time should be adjusted according to the actual situation, so the invention should not be limited thereto.
Detecting whether the impurity defect in the metal film layer exceeds the specification or not according to step S4, and if the impurity defect in the metal film layer exceeds the specification, performing impurity removal treatment on the metal film layer to ensure that the impurity defect in the metal film layer does not exceed the specification; and if the impurity defects in the metal film layer do not exceed the specification, etching the metal film layer to form a metal layer structure. The metal layer structure may include a metal interconnect structure, a plate of a resistor, or a plate of a capacitor.
For example, in the step S2, during the process of forming the metal film layer on the wafer, the deposition machine is stopped abnormally to stop the process of depositing the metal film layer, if the wafer on which the partial thickness of the metal film layer is deposited stays in the deposition chamber of the machine for more than a certain time (for example, more than 20min) and the deposition process is not continued to deposit the metal film layer, the surface temperature of the wafer may slowly decrease, that is, the temperature of the formed partial thickness of the metal film layer is slowly decreased from a temperature higher than the solid solution temperature of the material of the metal film layer to room temperature, which may cause the structural state of the metal film layer in the step S2 to change during the slow decrease of the temperature, so as to form a second phase of impurities, for example, when the material of the metal film layer is an alloy composed of aluminum and copper, in step S2, an alloy of aluminum and copper at a temperature of not less than 300 DEG CAnd when the temperature is slowly reduced to room temperature, copper aggregation can occur in the metal film layer to form Al2Cu impurity defects which cause structural or surface non-uniformity of the metal film layer. Or, in the step S3, during the cooling process of the metal film layer, the cooling process is abnormal due to insufficient amount of cooling gas such as nitrogen introduced, so that the structural state of the metal film layer changes, and the second-phase impurity defect occurs in the metal film layer. The uneven metal film layer with a large number of out-of-specification impurity defects may affect the performance of the metal layer structure formed after the subsequent etching process, for example, when the metal layer structure is a metal interconnection structure, in the subsequent packaging process, the connection reliability between a bonding pad and a lead in the metal interconnection structure with uneven structure or surface may be affected, thereby causing problems such as circuit failure.
When detecting the impurity defect in the metal film layer, if the impurity defect in the metal film layer exceeds the specification, the step of performing impurity removal treatment on the metal film layer may also be different according to the reason for causing the impurity defect in the metal film layer to exceed the specification, and the step may include: when the deposition process of the metal film layer in the deposition chamber is finished and the cooling process in the cooling chamber is abnormal to cause the defect of the out-of-specification impurities in the metal film layer, the metal film layer can be directly annealed; when the deposition machine is abnormally stopped and the deposition process of the metal film layer is not completed, the metal film layer can be formed on the wafer (namely the metal film layer which is deposited originally) again, and the newly formed metal film layer is annealed. The annealing treatment comprises the following steps: the metal film layer is maintained for a certain time at the temperature not less than the solid solution temperature of the material of the metal film layer, and then the metal film layer is rapidly cooled to the room temperature. Wherein, the certain time can include but is not limited to 2min to 20min (for example, 3min, 10min, 15min, etc.); rapidly cooling the metal film layer to room temperature can include, but is not limited to, cooling to 20-30 ℃ (e.g., 22 ℃, 25 ℃, 28 ℃, etc.) in less than 2 minutes; the appropriate certain time and the appropriate cooling rate can be selected according to different materials of the metal film layer. Maintaining the metal film layer at a temperature not less than the solid solution temperature of the material of the metal film layer for a certain time to make the structural state of the impurity defects generated in the metal film layer return to a uniform state again as much as possible, rapidly cooling the metal film layer to room temperature to fix the state of the metal film layer with a uniform structure or surface, and further making the structure or surface of the cooled metal film layer as uniform as possible to improve the impurity defects in the metal film layer, as shown in fig. 3, the number of the impurity defects D3 on the improved metal layer structure is greatly reduced compared with the impurity defects D1 shown in fig. 1 a. In addition, in order to rapidly cool the metal film layer to room temperature, a two-stage cooling method may be adopted for cooling, for example, a certain amount of nitrogen gas may be introduced to cool for 1min in the first stage, the nitrogen gas used in the first stage may be discharged in the second stage, the nitrogen gas may be introduced again to cool for 30s, and the cooling rate may be controlled by controlling parameters such as flow rate and pressure of the nitrogen gas, so as to reduce the impurity defects in the metal film layer as much as possible, and the cooling time in the first stage and the second stage may also be adjusted according to the cooling effect. In addition, if the impurity defects in the metal film layer do not exceed the specification, or the impurity defects exceeding the specification in the metal film layer are controlled within the specification through impurity removal treatment, etching is carried out on the metal film layer to form the metal layer structure. The method for etching the metal film layer may include dry etching or wet etching.
In addition, the steps in the method for manufacturing the metal layer structure are not limited to the above forming order, and the order of the steps can be adaptively adjusted.
In summary, the method for manufacturing a metal layer structure provided by the present invention includes: providing a wafer; forming a metal film layer on the wafer, wherein the temperature of the metal film layer is higher than the solid solution temperature of the material of the metal film layer; cooling the metal film layer; detecting whether the impurity defects in the metal film layer exceed the specification or not, and if the impurity defects in the metal film layer exceed the specification, performing impurity removal treatment on the metal film layer to enable the impurity defects in the metal film layer not to exceed the specification; and if the impurity defects in the metal film layer do not exceed the specification, etching the metal film layer to form the metal layer structure. The manufacturing method of the metal layer structure provided by the invention enables the impurity defects in the metal layer structure to be controlled within the specification, thereby avoiding influencing the performance of the metal layer structure.
An embodiment of the present invention provides a method for manufacturing a semiconductor device, including: the metal layer structure is formed on a wafer by adopting the manufacturing method of the metal layer structure provided by the invention. The wafer may include a substrate and a film structure formed on the substrate, such as a gate structure or a dielectric layer. The metal layer structure is formed by adopting the manufacturing method of the metal layer structure provided by the invention, so that the impurity defects in the metal layer structure are improved, namely the impurity defects are controlled within the specification, the metal layer structure has a uniform structure or surface, the performance of the metal layer structure is improved, and the performance of the semiconductor device is also improved.
The material of the metal layer structure may include one or an alloy of at least two of aluminum, copper, tungsten, nickel, gold, silver, titanium, and the like. The metal layer structure may include a metal interconnect structure, a plate of a resistor, or a plate of a capacitor. When the metal layer structure is a metal interconnection structure, in a subsequent packaging process, the metal interconnection structure with a uniform structure or surface improves the connection reliability between the welding pad and the lead wire, thereby avoiding the problems of circuit failure and the like and improving the reliability of the semiconductor device.
An embodiment of the present invention provides a semiconductor device including: the manufacturing method of the metal layer structure provided by the invention is adopted to manufacture the metal layer structure, and the metal layer structure is formed on a wafer. The wafer may include a substrate and a film structure formed on the substrate, such as a gate structure or a dielectric layer. Due to the adoption of the manufacturing method of the metal layer structure, the impurity defects in the formed metal layer structure are improved, namely the impurity defects are controlled within the specification, so that the metal layer structure has a uniform structure or surface, the performance of the metal layer structure is improved, and the performance of the semiconductor device is also improved.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (8)
1. A method of fabricating a metal layer structure, comprising:
providing a wafer;
forming a metal film layer on the wafer by sputtering plating, wherein the temperature of the metal film layer is higher than the solid solution temperature of the material of the metal film layer, the material of the metal film layer comprises an alloy consisting of aluminum and copper, and the temperature of the metal film layer is not less than 300 ℃;
cooling the metal film layer to enable the metal film layer to be rapidly cooled to room temperature within 2 min; and the number of the first and second groups,
detecting whether the impurity defects in the metal film layer exceed the specification or not, and if the impurity defects in the metal film layer exceed the specification, performing impurity removal treatment on the metal film layer to enable the impurity defects in the metal film layer not to exceed the specification; and if the impurity defects in the metal film layer do not exceed the specification, etching the metal film layer to form a metal layer structure.
2. The method of claim 1, wherein the metal layer structure comprises a metal interconnect structure, a plate of a resistor, or a plate of a capacitor.
3. The method according to claim 1, wherein if the impurity defect in the metal film layer is out of specification, the step of removing the impurity from the metal film layer comprises: directly annealing the metal film layer; or, reforming the metal film layer on the wafer, and annealing the reformed metal film layer.
4. The method of manufacturing a metal layer structure according to claim 3, wherein the annealing step includes: the metal film layer is maintained for a certain time at the temperature not less than the solid solution temperature of the material of the metal film layer, and then the metal film layer is rapidly cooled to the room temperature.
5. The method of claim 4, wherein rapidly cooling the metal film layer to room temperature comprises cooling using a two-stage cooling method.
6. The method according to any of claims 1 to 5, wherein a diffusion barrier layer is formed on the wafer before the metal film is formed on the wafer.
7. A method of manufacturing a semiconductor device, comprising: the method of manufacturing a metal layer structure according to any one of claims 1 to 6, wherein the metal layer structure is formed on a wafer.
8. A semiconductor device, comprising: the method of manufacturing a metal layer structure according to any one of claims 1 to 6, wherein the metal layer structure is formed on a wafer.
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Citations (3)
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| US6077782A (en) * | 1997-02-28 | 2000-06-20 | Texas Instruments Incorporated | Method to improve the texture of aluminum metallization |
| CN1258099A (en) * | 1998-12-21 | 2000-06-28 | 日本电气株式会社 | Semiconductor device interconnecting structure and mfg. method |
| CN1579003A (en) * | 2001-11-02 | 2005-02-09 | 株式会社荏原制作所 | Semiconductor manufacturing apparatus having a built-in inspection apparatus and a device manufacturing method using said manufacturing apparatus |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6077782A (en) * | 1997-02-28 | 2000-06-20 | Texas Instruments Incorporated | Method to improve the texture of aluminum metallization |
| CN1258099A (en) * | 1998-12-21 | 2000-06-28 | 日本电气株式会社 | Semiconductor device interconnecting structure and mfg. method |
| CN1579003A (en) * | 2001-11-02 | 2005-02-09 | 株式会社荏原制作所 | Semiconductor manufacturing apparatus having a built-in inspection apparatus and a device manufacturing method using said manufacturing apparatus |
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