CN110519536A - Power supply noise processing circuit and processing method, reading circuit and imaging sensor - Google Patents

Abstract

The present disclosure relates to a power supply noise processing circuit and processing method, a readout circuit and an image sensor. The power supply noise processing circuit includes: a ramp voltage signal generator and a comparator connected to the ramp voltage signal generator; the ramp voltage signal generator outputs a ramp voltage signal Vramp and a first fixed voltage signal Vrampc, the Vramp The generation mechanism is the same as the generation mechanism of the Vrampc, the voltage value of the Vrampc is a first fixed value; the Vramp is input to the first input of the comparator, the output signal of a single column of pixels in the pixel array and the Vrampc is respectively input to the second input terminals of the comparators.

Description

Power supply noise processing circuit and processing method, readout circuit and image sensor

technical field

The present disclosure relates to the field of electronic circuits, and in particular, to a power supply noise processing circuit and processing method, a readout circuit and an image sensor.

Background technique

CIS (CMOS image sensors) is becoming more and more popular due to the advantages of low power consumption and high integration. CIS is generally composed of pixel array and corresponding readout circuit. Due to the instability of the power supply, the power supply environment will be inconsistent when converting each row of pixels in practice, resulting in differences between rows, that is, power supply noise. The related art does not deal with the power supply noise.

SUMMARY OF THE INVENTION

The purpose of the present disclosure is to provide a power supply noise processing circuit and processing method, a readout circuit and an image sensor to eliminate power supply noise.

In order to achieve the above object, a first aspect of the present disclosure provides a power supply noise processing circuit, including:

a ramp voltage signal generator and a comparator connected to the ramp voltage signal generator;

The ramp voltage signal generator outputs a ramp voltage signal Vramp and a first fixed voltage signal Vrampc, the generation mechanism of the Vramp is the same as the generation mechanism of the Vrampc, and the voltage value of the Vrampc is a first fixed value;

The Vramp is input to the first input terminal of the comparator, and the output signal of a single column of pixels in the pixel array and the Vrampc are respectively input to the second input terminal of the comparator.

Optionally, the comparator includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a reset circuit, an operational amplifier and a buffer, the capacitors of the C1, C2, C3 and C4 the same value;

The output signal of the single-column pixel of the pixel array is input to the inverting input terminal of the operational amplifier through the C1;

The Vramp is input to the non-inverting input terminal of the operational amplifier through the C2;

The Vrampc is input to the inverting input terminal of the operational amplifier through the C3;

The second fixed voltage signal Vc is input to the non-inverting input terminal of the operational amplifier through the C4, the generation mechanism of the Vc is different from the generation mechanism of the Vrampc, and the voltage value of the Vc is a second fixed value;

The reset circuit is connected to the operational amplifier, and controls the operational amplifier to reset or operate normally;

The output signal of the operational amplifier is input to the buffer.

Optionally, the reset circuit includes:

a first switch, arranged between the non-inverting input terminal of the operational amplifier and the inverting output terminal of the operational amplifier;

a second switch, arranged between the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier;

When both the first switch and the second switch are turned on, the non-inverting input terminal and the inverting input terminal of the operational amplifier are respectively short-circuited with the corresponding output terminals of the operational amplifier, and the operational amplifier is reset;

When both the first switch and the second switch are turned off, the operational amplifier operates normally.

Optionally, the power supply noise processing circuit further includes:

A fixed voltage signal generator that outputs the Vc.

Optionally, each column of pixels in the pixel array shares the Vramp, the Vrampc, and the Vc.

Optionally, the ramp voltage signal generator includes: multiple current sources, multiple switches and resistors, one switch is connected to one current source;

By controlling a designated switch of the plurality of switches to be turned on, so that the current provided by the designated current source flows through the resistor, so as to generate the Vrampc;

The Vramp is generated by controlling the turn-on and turn-off of other switches other than the designated switch among the plurality of switches, so that currents provided by a varying number of current sources flow through the resistors.

A second aspect of the present disclosure provides a readout circuit, comprising:

The power supply noise processing circuit described in the first aspect of the present disclosure, the counter connected to the power supply noise processing circuit, and the digital processing circuit connected to the counter.

A third aspect of the present disclosure provides an image sensor, including:

a pixel array, including multiple columns of pixels;

The readout circuit according to the second aspect of the present disclosure is connected to each column of pixels included in the pixel array, respectively.

A fourth aspect of the present disclosure provides a power supply noise processing method based on the power supply noise processing circuit described in the first aspect of the present disclosure, including:

obtaining the ramp voltage signal Vramp and the first fixed voltage signal Vrampc output by the ramp voltage signal generator;

The Vramp is subtracted from the Vrampc by a comparator to eliminate power supply noise.

Through the above technical solution, the ramp voltage signal generator outputs the ramp voltage signal Vramp and the first fixed voltage signal Vrampc. Since the generation mechanism of the ramp voltage signal Vramp is the same as the generation mechanism of the first fixed voltage signal Vrampc, when the power supply noise When the voltage value of the ramp voltage signal Vramp starts to decrease from Vramp_max+ΔVramp, the voltage value of the first fixed voltage signal Vrampc also simultaneously becomes Vrampc+ΔVramp. That is, the power supply noise will affect the ramp voltage signal Vramp and the first fixed voltage signal Vrampc at the same time, so that the two change synchronously. Therefore, the ramp voltage signal Vramp is input to the first input terminal of the comparator, the output signal of a single column of pixels in the pixel array and the first fixed voltage signal Vrampc are respectively input to the second input terminal of the comparator, and the ramp voltage signal is input in the comparator. The voltage signal Vramp is subtracted from the first fixed voltage signal Vrampc to eliminate power supply noise.

Other features and advantages of the present disclosure will be described in detail in the detailed description that follows.

Description of drawings

The accompanying drawings are used to provide a further understanding of the present disclosure, and constitute a part of the specification, and together with the following detailed description, are used to explain the present disclosure, but not to limit the present disclosure. In the attached image:

FIG. 1 is a schematic diagram of an image sensor in the related art.

FIG. 2 is a schematic diagram of a ramp signal generator Vramp Gen in the related art.

FIG. 3 is a schematic diagram of a comparator Comp corresponding to a single column of pixels Pixel in the related art.

FIG. 4 is a schematic diagram of a power supply noise processing circuit provided by an embodiment of the present disclosure.

5 is a schematic diagram of a power supply noise processing method provided by an embodiment of the present disclosure based on a power supply noise processing circuit provided by an embodiment of the present disclosure.

FIG. 6 is a schematic diagram of a ramp signal generator Vramp Gen in an embodiment of the present disclosure.

FIG. 7 is a schematic diagram of an image sensor provided by an embodiment of the present disclosure.

Detailed ways

The specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure, but not to limit the present disclosure.

Before describing the power supply noise processing circuit provided by the embodiment of the present disclosure, the image sensor in the related art is first described. An image sensor in the related art includes a ramp signal generator Vramp Gen, a pixel array, a comparator Comp, a counter Counter, and a digital processing circuit. FIG. 1 is a schematic diagram of an image sensor in the related art. FIG. 1 is a schematic diagram of a pixel array including a plurality of single-column pixels Pixel. 1 is a schematic diagram of the output signal of the ramp signal generator Vramp Gen shared by each column of pixels included in the pixel array. Specifically, the output signal of Vramp Gen is respectively input to the comparator Comp corresponding to each single-column pixel Pixel, and each single-column pixel Pixel The output signal is input to the comparator Comp corresponding to the single-column pixel Pixel. FIG. 1 illustrates that the output signal of the comparator Comp corresponding to each single-column pixel is input to the counter Counter corresponding to the single-column pixel.

FIG. 2 is a schematic diagram of a ramp signal generator Vramp Gen in the related art. As shown in FIG. 2 , the ramp signal generator Vramp Gen includes: a plurality of current sources, a plurality of switches, a resistor, an output terminal and a ground terminal vssr. Each current source is connected to a switch, one end of the resistor is connected to ground vssr, and the other end of the resistor is connected to the output.

First, all switches are closed, so that the currents provided by all current sources flow through the resistors, so the voltage value of the voltage signal output by the output terminal is Vramp_max. Since the total number of current sources is preset and the resistance value of the resistor is preset, Vramp_max is fixed. Next, each switch is turned off one by one, so that the number of current sources supplying current to the resistor is gradually reduced, and thus the voltage value of the voltage signal output by the output terminal is gradually reduced to form a ramp signal Vramp.

Due to the instability of the power supply, the voltage value of the ramp voltage signal Vramp output by the ramp generator Vramp Gen is (Vramp_max+ΔVramp) when falling, where ΔVramp represents the voltage value change of the ramp voltage signal Vramp caused by power supply fluctuations.

FIG. 3 is a schematic diagram of a comparator Comp corresponding to a single column of pixels Pixel in the related art. As shown in FIG. 3 , the comparator Comp includes: a first capacitor C1 , a second capacitor C2 , an operational amplifier opamp, a switch S1 and a buffer. The output signal Vpix of the single-row pixel Pixel is connected to the inverting input terminal Vn of the operational amplifier opamp through the first capacitor C1, and the ramp voltage signal Vramp output by the ramp generator Vramp Gen is connected to the non-inverting input terminal Vp of the operational amplifier opamp through the second capacitor C2 , the switch S1 is set between the non-inverting input terminal Vp of the operational amplifier opamp and the inverting output terminal of the operational amplifier opamp, and the switch S1 is set between the inverting input terminal Vn of the operational amplifier opamp and the non-inverting output terminal of the operational amplifier opamp, The output end of the operational amplifier opamp is connected with the input end of the buffer buffer, and the output end of the buffer buffer is connected with the input end of the counter Counter.

The circuit shown in Figure 3 works as follows:

First, the switch S1 is turned on, so that the non-inverting input terminal Vp and the inverting input terminal Vn of the operational amplifier opamp are respectively short-circuited with the corresponding output terminals of the operational amplifier opamp, and the operational amplifier opamp is reset. At this time, the terminal voltage of the non-inverting input terminal Vp of the operational amplifier opamp is Vp0, and the terminal voltage of the inverting input terminal Vn of the operational amplifier opamp is Vn0, Vn0=Vp0=Vref (Vref is a voltage determined by the size of the operational amplifier opamp value).

When the operational amplifier opamp is reset, the output signal Vpix of the single-column pixel Pixel is the Reset signal, denoted as Vr, the voltage value of the ramp voltage signal Vramp output by the ramp voltage signal generator Vramp Gen is Vramp_max, and the counter Counter is set to zero.

When the operational amplifier opamp is reset, the charge stored on the first capacitor C1 is Qc1_0=C1*(Vn0-Vr)=C1*(Vref-Vr), and the charge stored on the second capacitor C2 is Qc2_0=C2*(Vp0- Vramp_max)=C2*(Vref-Vramp_max), wherein, C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2.

Next, the switch S1 is turned off, and the output signal Vpix of the pixels in a single row is a signal signal, denoted as Vs. After the switch S1 is turned off, the voltage value of the ramp voltage signal Vramp output by the ramp voltage signal generator Vramp Gen starts to decrease from Vramp_max, and at the same time, the counter starts to count, and the counter Counter is used to record the voltage value from the ramp voltage signal Vramp The length of time between the moment of falling and the moment when the output of the comparator Comp is toggled, converted into the number of clock cycles, and output in binary form.

The inversion of the output of the comparator Comp occurs when the terminal voltage of the non-inverting input terminal Vp of the operational amplifier opamp is equal to the terminal voltage of the inverting input terminal Vn of the operational amplifier opamp.

Specifically, when the voltage value of the ramp voltage signal Vramp output by the ramp voltage signal generator Vramp Gen drops to Vramp_max-(Vr-Vs), the output of the comparator Comp is inverted and the terminal voltage of the non-inverting input terminal Vp of the operational amplifier opamp is equal to The terminal voltage of the inverting input terminal Vn of the operational amplifier opamp is equal, and the output of the comparator Comp is inverted, so the counter Counter stops counting and completes the conversion of (Vr-Vs).

Due to the instability of the power supply, the voltage value of the ramp voltage signal Vramp output by the ramp generator Vramp Gen is (Vramp_max+ΔVramp) when falling, where ΔVramp represents the voltage value change of the ramp voltage signal Vramp caused by power supply fluctuations.

At this time, the terminal voltage of the non-inverting input terminal Vp of the operational amplifier opamp is Vp1, and the terminal voltage of the inverting input terminal Vn of the operational amplifier opamp is Vn1, then the charge stored on the first capacitor C1 is Qc1_1=C1*(Vn1-Vs ), the charge stored on the second capacitor C2 is Qc2_1=C2*[Vp1-(Vramp_max+ΔVramp)].

It can be known from the conservation of charge: Qc1_1=Qc1_0, that is, C1*(Vn1-Vs)=C1*(Vref-Vr)→Vn1-Vs=Vref-Vr, and then Vn1=Vref-(Vr-Vs); , according to the conservation of charge: Qc2_1=Qc2_0, that is, C2*[Vp1-(Vramp_max+ΔVramp)]=C2*(Vref-Vramp_max)→Vp1-(Vramp_max+ΔVramp)=Vref-Vramp_max, and then Vp1=Vref +ΔVramp. Then Vp1-Vn1=ΔVramp+(Vr-Vs). The power supply noise ΔVramp cannot be eliminated.

In view of the problem that the power supply noise is not processed in the prior art, an embodiment of the present disclosure proposes a power supply noise processing circuit to eliminate the power supply noise. FIG. 4 is a schematic diagram of a power supply noise processing circuit provided by an embodiment of the present disclosure. As shown in FIG. 4 , the power supply noise processing circuit provided by the embodiment of the present disclosure includes: a ramp voltage signal generator Vramp Gen and a comparator Comp connected to the ramp voltage signal generator Vramp Gen.

The ramp voltage signal generator Vramp Gen outputs a ramp voltage signal Vramp and a first fixed voltage signal Vrampc, the generation mechanism of Vramp is the same as that of Vrampc, and the voltage value of Vrampc is a first fixed value. Vramp is input to the first input terminal of the comparator Comp, and the output signals Vpix and Vrampc of the pixels Pixel in a single row in the pixel array are respectively input to the second input terminal of the comparator Comp.

Based on the power supply noise processing circuit shown in FIG. 4 , the present disclosure also provides a power supply noise processing method. FIG. 5 is a schematic diagram of a power supply noise processing method based on the power supply noise processing circuit provided by the embodiment of the present disclosure. As shown in Figure 5, the method includes:

Step S11: obtaining the ramp voltage signal Vramp and the first fixed voltage signal Vrampc output by the ramp voltage signal generator;

Step S12: Subtract the Vramp from the Vrampc through a comparator to eliminate power supply noise.

In the embodiment of the present disclosure, the ramp voltage signal generator Vramp Gen outputs two voltage signals, the first voltage signal is the ramp voltage signal Vramp, the second voltage signal is the first fixed voltage signal Vrampc, and the generation mechanism of the ramp voltage signal Vramp The generation mechanism of the first fixed voltage signal Vrampc is the same as that of the first fixed voltage signal Vrampc, and the voltage value of the first fixed voltage signal Vrampc is the first fixed value.

Since the generation mechanism of the ramp voltage signal Vramp is the same as the generation mechanism of the first fixed voltage signal Vrampc, when the voltage value of the ramp voltage signal Vramp starts to decrease from Vramp_max+ΔVramp due to the existence of power supply noise, the The voltage value also becomes Vrampc+ΔVramp at the same time. That is, the power supply noise will affect the ramp voltage signal Vramp and the first fixed voltage signal Vrampc at the same time, so that the two change synchronously.

In order to eliminate power supply noise, the ramp voltage signal Vramp is input to the first input terminal of the comparator, and the output signal of a single column of pixels in the pixel array and the first fixed voltage signal Vrampc are respectively input to the second input terminal of the comparator. In the process, the ramp voltage signal Vramp is subtracted from the first fixed voltage signal Vrampc, so as to eliminate power supply noise.

FIG. 6 is a schematic diagram of a ramp signal generator Vramp Gen in an embodiment of the present disclosure. As shown in FIG. 6 , the ramp signal generator Vramp Gen includes: a plurality of current sources, a plurality of switches, a resistor, an output terminal and a ground terminal vssr. Each current source is connected to a switch.

A designated current source and a designated switch among the plurality of current sources are used to generate the first fixed voltage signal Vrampc. Specifically, the designated switch is closed, so that the current provided by the designated current source connected to the designated switch flows through the resistor to generate the first fixed voltage signal Vrampc, and after the designated switch is closed, it will not be disconnected to ensure the first fixed voltage signal Vrampc The voltage value is the first fixed value.

First, other current sources except the designated current source among the plurality of current sources and other switches except the designated switch among the plurality of switches and other switches are used to generate the ramp voltage signal Vramp. First, all other switches are closed, so that the currents provided by all other current sources flow through the resistors, so that the voltage value of the ramp voltage signal Vramp output by the ramp signal generator Vramp Gen is the largest, that is, Vramp_max. Since the total number of current sources is preset and the resistance value of the resistor is preset, Vramp_max is fixed. Next, each other switch is turned off one by one, so that the number of current sources supplying current to the resistor gradually decreases, so the ramp signal generator Vramp Gen outputs a ramp voltage signal Vramp whose voltage value gradually decreases from Vramp_max.

Due to the instability of the power supply, the voltage value of the ramp voltage signal Vramp output by the ramp generator Vramp Gen when the voltage value drops is (Vramp_max+ΔVramp), where ΔVramp represents the voltage value change of the ramp voltage signal Vramp caused by power fluctuations.

As shown in FIG. 4 , in the power supply noise processing circuit provided by the embodiment of the present disclosure, the comparator Comp includes: a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a reset circuit, an operational amplifier, and a buffer device buffer, the capacitance values of C1, C2, C3 and C4 are the same, all of which are C;

The output signal of the single-column pixel of the pixel array is input to the inverting input terminal of the operational amplifier through the C1;

The Vramp is input to the non-inverting input terminal of the operational amplifier through the C2;

The Vrampc is input to the inverting input terminal of the operational amplifier through the C3;

The second fixed voltage signal Vc is input to the non-inverting input terminal of the operational amplifier through the C4, the generation mechanism of the Vc is different from the generation mechanism of the Vrampc, and the voltage value of the Vc is a second fixed value;

The reset circuit is connected to the operational amplifier, and controls the operational amplifier to reset or operate normally;

The output signal of the operational amplifier is input to the buffer.

The working principle of the power supply noise processing circuit provided by the embodiment of the present disclosure is as follows:

First, the reset circuit controls the operational amplifier opamp to reset. At this time, the terminal voltage of the non-inverting input terminal Vp of the operational amplifier opamp is Vp0, and the terminal voltage of the inverting input terminal Vn of the operational amplifier opamp is Vn0, Vn0=Vp0=Vref (Vref is a voltage determined by the size of the operational amplifier opamp value).

When the operational amplifier opamp is reset, the charge stored on the first capacitor C1 is Qc1_0=C1*(Vn0-Vr)=C*(Vref-Vr), and the charge stored on the second capacitor C2 is Qc2_0=C2*(Vp0- Vramp_max)=C*(Vref-Vramp_max), the charge stored on the third capacitor C3 is Qc3_0=C3*(Vn0-Vrampc)=C*(Vref-Vrampc), the charge stored on the fourth capacitor C4 is Qc4_0=C4 *(Vp0-Vc)=C*(Vref-Vc).

When the operational amplifier opamp is reset, the output signal Vpix of the single-row pixel Pixel is a Reset signal, denoted as Vr, and the voltage value of the ramp voltage signal Vramp output by the ramp voltage signal generator Vramp Gen is Vramp_max.

Next, the reset circuit controls the operational amplifier opamp to operate normally, and the output signal Vpix of a single column of pixels is a signal signal, denoted as Vs.

After the reset circuit controls the operational amplifier opamp to operate normally, the voltage value of the ramp voltage signal Vramp output by the ramp voltage signal generator Vramp Gen starts to decrease from Vramp_max,

Due to the instability of the power supply, the voltage value of the ramp voltage signal Vramp output by the ramp generator Vramp Gen is (Vramp_max+ΔVramp) when falling, where ΔVramp represents the voltage value change of the ramp voltage signal Vramp caused by power fluctuations.

At this time, the terminal voltage of the non-inverting input terminal Vp of the operational amplifier opamp is Vp1, and the terminal voltage of the inverting input terminal Vn of the operational amplifier opamp is Vn1, then the charge stored on the first capacitor C1 is Qc1_1=C1*(Vn1-Vs )=C*(Vn1-Vs), the charge stored on the second capacitor C2 is Qc2_1=C2*[Vp1-(Vramp_max+ΔVramp)]=C*[Vp1-(Vramp_max+ΔVramp)], the third capacitor C3 The stored charge is Qc3_1=C3*[Vn1-(Vrampc+ΔVramp)]=C*[Vn1-(Vrampc+ΔVramp)], and the stored charge on the fourth capacitor C4 is Qc4_1=C4*(Vp1-Vc)=C *(Vp1-Vc).

It can be known from the conservation of charge: Qc1_1+Qc3_1=Qc1_0+Qc3_0, that is, C*(Vn1-Vs)+C*[Vn1-(Vrampc+ΔVramp)]=C*(Vref-Vr)+C*(Vref-Vrampc) , and then Vn1=Vref-(Vr-Vs)/2+ΔVramp/2; in the same way, it can be known from the conservation of charge: Qc2_1+Qc4_1=Qc2_0+Qc4_0, that is, C*[Vp1-(Vramp_max+ΔVramp)]+ C*(Vp1-Vc)=C*(Vref-Vramp_max)+C*(Vref-Vc), and then Vref+ΔVramp/2 is obtained. Then Vp1-Vn1=(Vr-Vs)/2. Vp1-Vn1 has nothing to do with the power supply noise ΔVramp, so the power supply noise is eliminated.

In one embodiment, the reset circuit includes:

a first switch, arranged between the non-inverting input terminal of the operational amplifier and the inverting output terminal of the operational amplifier;

a second switch, arranged between the inverting input terminal of the operational amplifier and the non-inverting output terminal of the operational amplifier;

When both the first switch and the second switch are turned on, the non-inverting input terminal and the inverting input terminal of the operational amplifier are respectively short-circuited with the corresponding output terminals of the operational amplifier, and the operational amplifier is reset;

When both the first switch and the second switch are turned off, the operational amplifier operates normally.

As shown in FIG. 4 , the switch S1 is set between the non-inverting input terminal Vp of the operational amplifier opamp and the inverting output terminal of the operational amplifier opamp, and the switch S1 is set between the inverting input terminal Vn of the operational amplifier opamp and the non-inverting input terminal of the operational amplifier opamp between the outputs. The switch S1 is turned on, so that the non-inverting input terminal Vp and the inverting input terminal Vn of the operational amplifier opamp are respectively short-circuited with the corresponding output terminals of the operational amplifier opamp, and the operational amplifier opamp is reset. Switch S1 is open, allowing the operational amplifier opamp to operate normally.

In an implementation manner, the power supply noise processing circuit provided by the embodiment of the present disclosure further includes:

A fixed voltage signal generator that outputs the Vc.

The fixed voltage signal generator can use any known method to generate the fixed voltage signal, as long as the voltage value of the generated voltage signal is a fixed value, and the fixed voltage signal generated by the fixed voltage signal generator can be the same as the voltage value of Vrampc. It may be the same or different, which is not limited in the present disclosure.

In an implementation manner, each column of pixels in the pixel array shares the Vramp, the Vrampc, and the Vc. That is, the output signals Vramp and Vrampc of Vc and Vramp Gen are respectively input to the comparator Comp corresponding to each single-column pixel Pixel, and the output signal of each single-column pixel Pixel is input to the comparator Comp corresponding to the single-column pixel Pixel.

Based on the same inventive concept, an embodiment of the present disclosure also provides a readout circuit, including:

Embodiments of the present disclosure provide a power supply noise processing circuit, a counter connected to the power supply noise processing circuit, and a digital processing circuit connected to the counter.

The working principle of the readout circuit provided by the embodiment of the present disclosure is as follows:

First, the control operation amplifier opamp is reset. When the operation amplifier opamp is reset, the counter Counter is set to zero.

Then, the operational amplifier opamp is controlled to operate normally, the voltage value of the ramp voltage signal Vramp output by the ramp voltage signal generator Vramp Gen starts to decrease from Vramp_max, and at the same time, the counter Counter starts to count, and the counter Counter is used to record the voltage from the ramp voltage signal Vramp The length of time between the moment when the value begins to fall and the moment when the output of the Comparator Comp toggles, converted to a number of clock cycles, and output in binary form.

The inversion of the output of the comparator Comp occurs when the terminal voltage of the non-inverting input terminal Vp of the operational amplifier opamp is equal to the terminal voltage of the inverting input terminal Vn of the operational amplifier opamp.

Specifically, when the voltage value of the ramp voltage signal Vramp output by the ramp voltage signal generator Vramp Gen drops to Vramp_max-(Vr-Vs), the output of the comparator Comp is inverted and the terminal voltage of the non-inverting input terminal Vp of the operational amplifier opamp is equal to The terminal voltage of the inverting input terminal Vn of the operational amplifier opamp is equal, and the output of the comparator Comp is inverted, so the counter Counter stops counting and completes the conversion of (Vr-Vs).

Based on the same inventive concept, an embodiment of the present disclosure also provides an image sensor, including:

a pixel array, including multiple columns of pixels;

The readout circuit provided by the embodiment of the present disclosure is respectively connected to each column of pixels included in the pixel array.

FIG. 7 is a schematic diagram of an image sensor provided by an embodiment of the present disclosure. As shown in FIG. 7 , an image sensor provided by an embodiment of the present disclosure includes a ramp signal generator Vramp Gen, a pixel array, a comparator Comp, a counter, and a digital processing circuit. FIG. 7 illustrates that the pixel array includes a plurality of single-column pixels Pixel. FIG. 7 illustrates that each column of pixels included in the pixel array shares the output signals Vramp and Vrampc of the ramp signal generator Vramp Gen, and FIG. 7 illustrates that each row of pixels included in the pixel array shares Vc. That is, the output signals Vramp and Vrampc of Vc and Vramp Gen are respectively input to the comparator Comp corresponding to each single-column pixel Pixel, and the output signal of each single-column pixel Pixel is input to the comparator Comp corresponding to the single-column pixel Pixel. FIG. 7 illustrates that the output signal of the comparator Comp corresponding to each single-column pixel is input to the counter Counter corresponding to the single-column pixel. The comparator Comp corresponding to each single-column pixel in FIG. 7 is the comparator Comp in the power supply noise processing circuit provided by the embodiment of the present disclosure.

The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings. However, the present disclosure is not limited to the specific details of the above-mentioned embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure. These simple modifications all fall within the protection scope of the present disclosure.

In addition, it should be noted that, the specific technical features described in the above-mentioned specific embodiments can be combined in any suitable manner unless they are inconsistent. In order to avoid unnecessary repetition, the present disclosure provides The combination method will not be specified otherwise.

In addition, the various embodiments of the present disclosure can also be arbitrarily combined, as long as they do not violate the spirit of the present disclosure, they should also be regarded as the contents disclosed in the present disclosure.

Claims (9)

1. a kind of power supply noise processing circuit characterized by comprising

Ramp voltage signal generator and the comparator being connected with the ramp voltage signal generator；

Ramp voltage signal generator output ramp voltage signal Vramp and the first fixed voltage signal Vrampc, it is described The generation mechanism of Vramp is identical with the generation mechanism of the Vrampc, and the voltage value of the Vrampc is the first fixed value；

The Vramp is input to the first input end of the comparator, the output signal of single column of pixels and institute in pixel array State the second input terminal that Vrampc is separately input to the comparator.

2. power supply noise processing circuit according to claim 1, which is characterized in that the comparator includes: first capacitor C1, the second capacitor C2, third capacitor C3, the 4th capacitor C4, reset circuit, operational amplifier and buffer, the C1, C2, The capacitance of C3 and C4 is identical；

The output signal of the single column of pixels of the pixel array is input to the inverting input terminal of the operational amplifier through the C1；

The Vramp is input to the non-inverting input terminal of the operational amplifier through the C2；

The Vrampc is input to the inverting input terminal of the operational amplifier through the C3；

Second fixed voltage signal Vc is input to the non-inverting input terminal of the operational amplifier, the generation machine of the Vc through the C4 System is different from the generation mechanism of the Vrampc, and the voltage value of the Vc is the second fixed value；

The reset circuit is connected with the operational amplifier, controls the operational amplifier and resets or operate normally；

The output signal of the operational amplifier inputs the buffer.

3. power supply noise processing circuit according to claim 2, which is characterized in that the reset circuit includes:

First switch, be arranged in the operational amplifier non-inverting input terminal and the operational amplifier reversed-phase output it Between；

Second switch, be arranged in the operational amplifier inverting input terminal and the operational amplifier in-phase output end it Between；

When the first switch and the second switch are both turned on, the non-inverting input terminal of the operational amplifier and reversed input End is shorted with the corresponding output end of the operational amplifier respectively, and the operational amplifier resets；

When the first switch and the second switch disconnect, the operational amplifier is operated normally.

4. power supply noise processing circuit according to claim 2, which is characterized in that further include:

Fixed voltage signal generator exports the Vc.

5. power supply noise processing circuit according to claim 2, which is characterized in that each column pixel is total in the pixel array With the Vramp, the Vrampc and the Vc.

6. power supply noise processing circuit according to claim 1, which is characterized in that the ramp voltage signal generator packet Include: multiple current sources, multiple switch and resistance, a switch are connected with a current source；

Switch conduction is specified in the multiple switch by controlling, so that the electric current that specified current flow source provides flows through the resistance, To generate the Vrampc；

By controlling the conducting and disconnection that other are switched in addition to the assigned switch in the multiple switch, so that quantity variation The electric current that current source provides flows through the resistance, to generate the Vramp.

7. a kind of reading circuit characterized by comprising

Claim 1-6 any power supply noise processing circuit, the counter that is connected with the power supply noise processing circuit, The digital processing circuit being connected with the counter.

8. a kind of imaging sensor characterized by comprising

Pixel array, including multiple row pixel；

Reading circuit as claimed in claim 7, each column pixel for including with the pixel array are respectively connected with.

9. a kind of power supply noise processing method based on any power supply noise processing circuit of claim 1-6, feature It is, comprising:

Obtain the ramp voltage signal Vramp and the first fixed voltage signal Vrampc of the output of ramp voltage signal generator；

The Vramp and the Vrampc are subtracted each other by comparator, to eliminate power supply noise.