CN1104708C - Multi-stage transponder wake-up, method and struture thereof - Google Patents

Abstract

The present invention provides a system and method that provides transponders (14) to operate or wake up in multiple stages to conserve transponder or tag (14) operating energy. A threshold detector (62) is provided to measure the power level of the received RF energy. If the RF energy received by the detector (62) exceeds a predetermined level, the transponder (14) uses the modulation detector (64) to determine whether it has been awakened by a valid interrogation signal from the interrogator (12), or has received The RF energy present is simply bursts of spurious RF energy from some other source. If the modulation detector (64) detects a predetermined modulation, the transponder (14) is fully activated to its normal operating state.

Description

multistage transponder

The following patent applications are hereby incorporated by reference, all of which are assigned. Patent number/sequence number application date TI case number 5,053,774 91, February 13, 91 TI 1279707/981,635 92 November 25 Ti 1668808/021,123, February 23, 93 TI 17529

technical field

The present invention relates generally to identification systems of the type comprising interrogators and transponders, and more particularly to a system in which an interrogator transmits an interrogation signal to a transponder and in response the transponder returns a reply signal to the interrogator . The present invention also generally relates to improvements in methods of communication between interrogators and transponders. In a specific embodiment, the invention relates to Automatic Vehicle Verification (AVI) of an identification system.

Background technique

The present invention will be described in close connection with an Automatic Vehicle Identification (AVI) system capable of exchanging data codes between an interrogator and a transponder. However, the AVI domain is only one area where the principles of the invention described herein can be applied. Systems using batteryless or battery-operated transponders can be applied to identify or locate objects with transponders such as livestock, luggage or other items. In addition, transponders can provide status information about objects located by them, for example, a transponder mounted on a car door can indicate whether the door is open or not. Transponders employed in the above identification systems or other systems may be powered by batteries or by radio frequency (RF) signals.

Typically, for AVI systems, interrogators are placed at tollbooths on toll roads, parking garages, or other restricted access locations. Interrogators (readers) identify passing cars by sending wireless interrogation signals to transponders (tags), which are usually small, self-contained units placed on, for example, the car's fender or windshield superior. In this way, cars (or other vehicles or objects) can be identified in a fast and efficient manner. Using such a system, access charges can be charged to an account number associated with the driver, owner, or other designated person. A compatible standard for such AVI systems is set forth in Title 21, Unit 2, Chapter 16, Sections 1-4 of the California Code Rules, referred to herein as the Caltrans specification.

For specific embodiments compatible with the Caltrans specification, the interrogator plays the minimum role of: 1) triggering or activating the transponder; 2) interrogating the transponder for specific information; acknowledgment to the transponder. The immediate order of the Caltrans specification includes electronic tax collection, sometimes described as part of "Electronic Taxation and Traffic Management" (ETTM). Tax collection AVI equipment generally consists of two functional elements: a vehicle-mounted transponder and a fixed-position interrogator.

The toll booth consists of at least one interrogator working as described above. When interrogating or "registering" specific information such as a transponder identification number (ID), the interrogator (or separate computer) typically checks the transponder ID against a valid legal account database. If the transponder ID is valid and legitimate, the interrogator will send a signal to the gate mechanism, or to the toll station computer, to operate the gate mechanism and allow the vehicle to pass. Of course, other enforcement means that cause less disruption to traffic are also possible, for example, allowing all cars to pass, and other means to identify cars carrying transponders (or cars with invalid transponders or no transponders at all) rogue cars) and notify the appropriate enforcement agency.

The query signal and the response signal contain data codes. The Caltrans specification has four sets of definitions for the data codes transmitted between the interrogator and the transponder. The following data codes are derived from the Caltrans specification, they are only exemplary, not a complete or mandatory general AVI system code list.

(a) Institution code: This 16-digit code identifies the institution authorized to conduct the transaction;

(b) Error detection code: The error detection code can be CRC-CCITT-16 with generator polynomial X ¹⁶ +X ¹² +X ⁵ +1. As a result, a 16-bit error detection code is sent with each data message;

(c) Header code: The header code is generally the first field of each data message sent by the reader or transponder, consisting of an 8-bit word and a 4-bit word for a total of 12 bits. The header code provides a "self-synchronization" signal that a receiver within the transponder or interrogator can use to self-synchronize with data received from the interrogator or transponder, respectively. A typical self-synchronizing signal could be the binary and hexadecimal values: 10101010 and AA, respectively.

(d) Header ID code provides a unique 4-bit flag that the transponder or interrogator decoder recognizes as the end of the header code, followed by data information. Typical flag signals are binary and hexadecimal values: 1100 and C, respectively;

(e) Interrogator ID Number: This 32-bit group is used to uniquely identify the Interrogator conducting the transaction;

(f) Transaction Record Type Code: This 16-bit code uniquely identifies the specific type of transaction valid between the reader and the transponder. This code uniquely defines transponder information fields and functions as permissible. For example, the hexadecimal numbers 1 to 7FFF can be set for the transponder information structure, and 8000 to FFFF can be used for the reader to transponder information structure;

(g) Transaction Status Code: used to provide status information to the transponder; and

(h) Transponder ID Number: This 32-bit code uniquely identifies which transponder is responding to the registration request or is being acknowledged.

Because transponders typically derive their operating power from a small battery or from received RF signals, transponders are not normally operational. The interrogator transmits an RF trigger pulse to energize (turn on) a transponder on an approaching car or other object. The interrogator may transmit multiple RF trigger pulses at regular intervals to wake up approaching transponders. Or conversely, the interrogator can send an RF trigger pulse in response to an external stimulus giving it an indication that a transponder is approaching (e.g., a light, heat, or magnetic sensor), and after a time delay, the reader will send that as a registration message or The decoded signal of the interrogation, which, when detected and decoded by the transponder, provides the transponder with initial information as a block of data that the transponder should transmit.

In one embodiment described, an interrogator transponder transmits an unmodulated continuous wave RF signal as an interrogation signal while waiting for a reply signal from the transponder. Like sound signals, unmodulated RF signals resemble a constant or "pure" tone with no amplitude or frequency variation. However, it should be noted that even a frequency varying signal may be considered to be "unmodulated" in amplitude and vice versa. In this embodiment, a transponder reply signal is generated when the back reflector of the transponder modulates a continuous wave RF signal with information from the transponder. According to sound simulations, back reflector modulation is the same as singing to a fan and listening to the resulting sound. Generally, when a person sings, they control the variation or modulation of their voice. Similarly, typically an RF transmitter can modulate the signal. However, when a person sings to the fan, the blades of the fan will immediately reflect the speech back to the person, and the blades will immediately turn in front of his mouth. Thus, the singer hears a wave-like sound superimposed on his voice. The "wavy" sound heard by the singer does not vary more than the amplitude of the reflections of his speech. Similarly, a transponder may modulate (by amplitude or other means) the continuous wave RF signal received from the interrogator, the reflected signal having the modulation superimposed on it.

Contents of the invention

Disclosed herein is a transponder for radio communication with an interrogator, characterized in that the transponder comprises:

a) an antenna for receiving an RF interrogation signal from the interrogator;

b) a threshold detector in electrical communication with the antenna; the threshold detector is adapted to measure the power level of the RF interrogation signal, compare the power level to a threshold, and provide a signal indicative of the power Whether the level is greater than the threshold signal of the threshold;

c) a modulation detector in electrical communication with the antenna, the modulation detector detecting modulation in the RF interrogation signal and providing a modulation presence signal, and

d) control circuitry, upon receipt of said threshold signal and said modulation presence signal, said control circuitry receiving said RF interrogation signal from said antenna and responding with data modulated on said RF interrogation signal.

In the above-mentioned device, the transponder can be activated or woken up in various states, so as to save energy when the transponder or the tag is working. A threshold detector is provided for measuring the power level of the received RF energy. If the RF energy received by the detector exceeds a predetermined level, the transponder uses the modulated detector to determine whether it has been awakened by a valid interrogation signal from an interrogator, or to determine whether the received RF energy is only from other source pseudo-burst. If the modem detects the predetermined modulation, the transponder is activated to its normal operating state.

The present invention further protects transponders or tags from being activated or awakened by spurious RF energy. A modulation detector is provided to detect the modulation signal superimposed on the RF modulation of the interrogator. Preferably, the superimposed modulation is at a low frequency, below those at which electromagnetic interference (EMI) would normally be present, making it less likely that the transponder will be falsely activated by inadvertent RF signals. Upon receipt of an RF interrogation with the appropriate modulation superimposed on it, the modulation detector is activated, waking up the other circuitry of the transponder, enabling the transponder to communicate with the interrogator.

There is also provided a system for passing fixed or semi-fixed information from the interrogator to the transponder, preferably operated by a revenue collection agency or other authorized entity. This fixed or semi-fixed information is only communicated by effective specific commands when a specific access code is sent from an authorized interrogator to a transponder to enter a specific or maintenance mode. It is preferred that the transponder confirms to the authorized interrogator that it is operating in the maintenance mode so that the interrogator can reliably send the dedicated command.

The preferred embodiment of the present invention further includes transponder interface circuitry which enables communication between the transponder controller and external circuitry. The interface circuit has a buffer memory which enables the transponder controller and the external circuit to communicate directly without complex conventions by each transmitting data at the clock rate of the transponder or the external circuit. The interface controller enables the various transponder controllers and external circuits which receive control from the buffer memory, including the clock circuit, to the buffer memory. With the buffer memory and interface controller, either of the transponder controller and the external circuitry can fill or empty the buffer memory at the clock rate of the transponder or the external circuitry. The interface controller will monitor this transfer and when the buffer memory is full or empty, the interface controller will send a command to the appropriate transponder controller or external circuitry to receive data from a full buffer memory or send data to an empty buffer memory data.

In a preferred embodiment of the invention, a transponder is provided in an automobile driving on the roadway. The transponder receives the interrogation signal from the interrogator's transmitter, which can modulate a continuous input wave from the interrogator or other source through the back reflector to reply to the interrogator. The interrogator's receiver then decodes the signal modulated by the back reflector and can relay the information contained in the signal to control circuitry which can, for example, store the information in memory. The interrogator associated with each lane can register several transponders independently.

The principles described in connection with the present invention can be applied to non-AVI systems as well as AVI systems. For example, the power saving principles described herein may be used with commonly assigned US Patent No.: 5,053,774 and US Patent Application No. 08/021,123.

Description of drawings

Fig. 1 is the circuit block diagram of interrogator and transponder of the present invention;

FIG. 2 is a schematic side view of typical equipment of the vehicle identification (AVI) system according to FIG. 1;

3 is a schematic top view of three adjacent traffic lanes using the AVI system of FIG. 1 , including a timing diagram of trigger pulses and a diagram of interrogation signals from interrogators to transponders;

Figure 4 is an electrical block diagram of a transponder and interrogator usable in the system of Figures 1-3;

Figure 5 is a more detailed circuit block diagram than Figure 4, showing the modulation detector, high-pass filter and wake-up block;

Fig. 6 is a more detailed circuit block diagram of components than in Fig. 5, including a modulation detector, a high-pass filter and a wake-up block;

Figure 7 is a signal timing diagram on the transponder tag node shown in Figures 5-6;

Fig. 8 is the connection circuit block diagram of each functional block of the application-specific integrated circuit (ASIC) of Fig. 5;

Fig. 9 is a circuit block diagram of a preferred receiving buffer block in the digital ASIC receiving the signal "A" of the modulation detector in Fig. 8;

Figure 10 is a block diagram of a preferred path discrimination block within the digital ASIC of Figure 8;

Figure 11 is a block diagram of a preferred master controller block within the digital ASIC of Figure 8;

Figure 12 is a block diagram of a preferred main memory block within the digital ASIC of Figure 8;

Figure 13 is a block diagram of a preferred transmit block within the digital ASIC of Figure 8;

Figure 14 is a block diagram of a preferred external interface block within the digital ASIC of Figure 8;

Figure 15 is a block diagram of a preferred buzzer block within the digital ASIC of Figure 8;

Figure 16 is a block diagram of a preferred oscillator block within the digital ASIC of Figure 8;

Figure 17 is an electrical block diagram of an interrogator usable within the transponder and interrogator arrangement of Figures 1-3 wherein, in accordance with the present invention, the interrogator is capable of transmitting a low frequency modulated signal to activate the transponder;

Figure 18 shows waveform diagrams of two different embodiments of "squitter" modulation by which the low frequency signal from the interrogator of Figures 1-4 can be superimposed on the RF interrogation signal;

Figure 19 is a block circuit diagram of a transponder, which also includes an RF threshold detector.

Corresponding numerals in the different figures correspond to corresponding parts unless otherwise indicated.

Detailed ways

1 shows a block diagram of an AVI system 10 in which an interrogator 12 communicates with a remote control transponder 14. The interrogator 12 transmits an interrogation signal to the transponder 14. In response to the interrogation signal, the transponder 14 transmits back to interrogator 12 a reply signal containing a unique identifier (ID). In a typical AVI system, the interrogator 12 will transmit the ID to the host computer (host) 16 for crediting the driver's account. The AVI system preferably includes an interrogator electronics module 20 for controlling the interrogator 12.

Referring to FIGS. 2 and 3 , a plurality of traffic lanes 28 are located at traffic control points such as tolls (taxes) 29 , and each traffic lane 28 has an associated interrogator 12 . The interrogator 12 is in communication with the transponder 14 carried by the vehicle 26 traveling on the associated lane 28 of the interrogator 12 via an RF data link. Interrogator 12 may have unique internal electrical parameters such as interrogator channel position, interrogator control parameters, and interrogator reference frequency. The role of the interrogator 12 in this application is to: trigger or activate the transponder 14; interrogate or register transponder 14-specific information and confirm to the transponder 14 whether a valid data exchange has taken place. As shown in Figures 1-3, the interrogator has an antenna 18 which is preferably mounted about 18 feet above the ground. The antenna 18 is preferably circularly polarized, but there are advantages in choosing other types of polarization, including linearly polarized elliptical polarization. Interrogator electronics module 20 is connected to antenna 18 by a suitable cable, such as RF coaxial cable 22 .

The interrogator 12 communicates wirelessly with the transponder 14 by sending an on/off keyed modulated signal to the transponder 14 . Interrogator 12 then sends a continuous wave RF signal to transponder 14 . The back reflector of transponder 14 modulates the continuous wave RF signal (as described in US Patent No. 4,739,328 to Koelle et al.) to respond to interrogator 12 . The details of the communication between the interrogator 12 and the transponder 14 are now further described. The function of the optional host computer 16 is to control the work of the interrogator 12 and the peripheral functions of the toll office. Such peripheral functions may include the operation of traffic control gates and other access enforcement devices such as cameras and traffic lights. Still other peripheral functions may include communicating with the interrogator 12 and communicating with a central office computer (not shown) that maintains account balance information. The connection line 24 between the interrogator 12 and the host 16 shown in FIG. 1 may be Ethernet, Token Ring, RS232, RS422 or other connection methods.

Interrogator 12 of FIG. 1 houses two modules: electronics module 20 and antenna 18 . As shown in FIG. 4 , the electronic module 20 includes a transmitter 52 , a receiver 54 and a control circuit 56 . The connection 22 between the antenna 18 and the electronics module 20 is a low pass RF connection, typically a coaxial cable and a multi-conductor cable that provides power and control signal information.

FIG. 2 shows a side view of a typical AVI system 10 . In this illustration, a car 26 is driving on lanes 28a - c and approaching antenna 18 . The transponder 14 is located on or in the vehicle 26 . Preferably the transponder 14 is mounted on the front window of the vehicle. In some applications, such as in very large automobiles, suitable locations may be other locations, such as on the bumper of a truck, to reduce variations in transponder 14 height. As shown in the figure, a vehicle 26 carrying a transponder 14 approaches an interrogator 18 at a toll booth 29 . The communication between the transponder 14 and the interrogator 12 will be discussed in further detail herein.

Figure 3 is a top view of the AVI system 10 including three channels 28a-c. The three channels shown are for illustration only, and the present system 10 may be applied to one or more channels. Circuitry is preferably provided within interrogator 12 for determining in which lane transponder 14 is located. US Patent Application No. 08/021,123 to Claude A. Sharpe (assigned to Texas Instruments Incorporated) provides such a general authentication circuit and method.

FIG. 4 provides a block diagram of the major components of AVI system 10 . First, the transponder 14 will be described with reference to FIG. 4 in conjunction with FIGS. 2 and 3 . AVI system 10 preferably includes directional antennas 18, each antenna 18 being focused on an associated lane 28a, 28b, 28c. One or more vehicles 26 each carrying one or more transponders 14 can be driven on each lane 28a-. Each transponder 14 preferably comprises: an antenna 30, an analog or analog/digital ASIC 32, a digital ASIC 34 and a modulating reflector 41. The antenna 30 and the modulating reflector 41 can form an integral antenna 31 . Preferably, ASIC32 and ASIC34 are also integrated into a single ASIC.

Referring further to FIGS. 3 and 4 , transponder antenna 30 is operative to receive RF transmissions from interrogator 12 . The analog ASIC 32 converts the signal provided by the transponder 30 into a voltage which activates the transponder 14 when the voltage exceeds a threshold. According to a preferred embodiment of the invention, the analog ASIC 32 detects the high frequency modulation present on the signal from the transponder antenna 30 and activates the transponder 14 only when the specific modulation frequency is present. In this way, the transponder is relatively immune to wake-up by spurious RF transmissions not occurring within the interrogator 12, and is only activated when the interrogator 12 transmits a particular frequency. The voltage threshold is adjustable.

Preferably, the transponder 14 only responds to interrogation signals transmitted by the interrogator antennas 18a-c located in the lanes 28a-c of the vehicle 26 carrying the transponder 14. To achieve this desired result, the transponder 14 compares the first field strength pulse 44a received from the first directional antenna 18a with the second field strength pulse 44b received from the second directional antenna 18b. The transponder 14 may then reply with the information of the appropriate interrogator 12 (ie, the interrogator associated with the lane 28a- or 28c in which the transponder 14 is traveling). A similar process will be repeated between other pairs of lanes (eg 28a-8c, 28b-2c). Transponder 14 is then operable to demodulate the appropriate interrogator 12 interrogation signal, which in the preferred embodiment is an amplitude modulated signal. The transponder 14 works again, the continuous wave signal sent by the interrogator 12 is modulated by back reflection, and the response signal is generated by controlling the reflector 41 .

Still referring to FIG. 4, analog ASIC 32 and digital ASIC 34 typically process interrogation signals received from transmitter 52 and calculate the necessary response data. Digital ASIC 34 then provides the appropriately formatted reply data stream to modulation reflector 41. The ASIC 34 can be a simple digital system using a fixed format, or a more general (universal) digital processing system that can incorporate multiple options. Several options can be envisioned for the ASIC34 to perform various tasks, examples of which include, but are not limited to: data storage, data exchange procedures, and battery capacity. The modulation reflector 41 is modulated by changing its apparent wavelength (preferably between 1/4 to 1/2 of the carrier wavelength), and when the apparent wavelength of the modulation reflector 41 is 1/2P, the antenna 30 should reflect the incident Most of the carrier energy. When the apparent wavelength of the modulating reflector 41 is 1/4P, it reflects very little of the incident carrier. The antenna can be switched between 1/2P and 1/4P by connecting or disconnecting two lengths of 1/4P waveguides, as is well known in the art. For the described embodiment, the reflection cross section (Rcs) preferably varies between 45 cm ² and 100 cm ² . Rcs is varied in a specific manner to transmit data from the transponder 14 to the interrogator 12. The transponder 14 is usually self-contained in a small credit card-sized package, fully portable. Preferably, an internal battery is provided to provide operating power for the transponder 14 . Alternatively, the transponder 14 may derive its operating power directly from the RF signal. Although the modulating reflector 41 is described as a separate component from the transponder antenna 30, both components could be integrated into a single integrated antenna 31.

Having generally described the components of transponder 14, a preferred embodiment of interrogator 12 is now generally described in FIG. 5, with further reference to FIGS. 3-4. Interrogators 12 are placed at specific points, such as toll booths 29, where data exchange is desired. The AVI system may include a common reference oscillator 50 generating at its output 51 a reference carrier to which the interrogator 12 is synchronized. Each interrogator 12 has a directional antenna 18 and a transmitter 52 that transmits a trigger signal 42 of sufficient field strength and/or modulation type at a preselected distance to trigger or activate a vehicle traveling on the lane 28 associated with the interrogator. Transmit interrogator 14 on 26. The transponder of the preferred embodiment is activated when the low frequency wake-up circuit 64 detects a preselected modulation frequency in the received signal.

Still referring to FIG. 5, if the wake-up circuit 64 receives a predetermined modulation signal, the wake-up circuit 64 adds a clock to the digital ASIC 34 with higher energy consumption. In this way, the power consumed by the wake-up circuit 64 is much lower than that of the digital ASIC 34, it constantly monitors the trigger signal 42 (see FIG. 3), and only activates the digital ASIC 34 when the trigger signal 42 (see FIG. 3) is detected, So power is saved. After transmitting trigger signal 42 (see FIG. 3 ), interrogator 12 transmits an interrogation signal to remotely transmitted interrogator 14 . The interrogation signal is preferably transmitted by on/off keying. After sending an interrogation signal. Transmitter 52 transmits a continuous wave RF signal to transponder 14, which can back-reflect and modulate the continuous wave RF signal to generate a reply signal. The interrogator 12 further includes a receiver 54 that receives the reply signal and distinguishes the reply signal from the spurious unmodulated reflected signal. The interrogator's transmitter 52 and receiver 54 operate under the control of a control interface circuit 56 . The host 16 controls the transmitter 52 to transmit the trigger signal 42 through the control interface circuit 56, and then transmits the inquiry signal.

In order to identify suitable lanes for the three lane conditions, the first interrogator 12a, the second interrogator 12b and the third interrogator 12c respectively send out the first, second and third interrogation signals simultaneously. During the first lane discrimination period 45, the first interrogator 12a emits a first field strength pulse 44a and the second or third interrogator 12b, 12c emits no RF energy. During the second lane discrimination period 46, the second interrogator 12b emits a second field strength pulse 44b while the first and third interrogators 12a, 12c emit no RF energy. During a third lane discrimination period 47, the third interrogator 12c emits a third field strength pulse 44c, while the first and second interrogators 12a, 12b emit no RF energy. In this way the pulses 44a, 44b, 44c received during the first, second and third field strength periods 45, 46, 47 (when the car 26 is traveling in one of the three lanes 28a, 28b, 28c) are compared The magnitude of can determine that the transponder 14 of the car 26 is traveling within one of the lanes 28a, 28b, 28c associated with each interrogator 12a, 12b, 12c. The host computer 16 further controls the transmitter 52 to send out a continuous wave RF signal through the control interface circuit 56, and then sends out an inquiry signal, and at the same time controls the receiver 54 to receive a response signal. This ordering can be generalized to any number of lanes.

The electronics module 20 of the interrogator 12 will now be described in more detail with reference to FIG. 4 . The electronics module 20 includes a transmitter 52 that can send a signal to the antenna 18 interrogating the transponder 14 . Transmitter 52 typically receives signals from host 16 via host connection 24 . During the transponder reply period, the transmitter 52 transmits a continuous wave RF signal to the transponder 14, which is then modulated by the back reflector with the reply data. Receiver 54 detects the backreflected modulated reflected energy from transponder 14 and separates the modulated signal from the non-modulated reflected signal. Antenna 18, shown here in electrical communication with transmitter 52 and receiver 54, is a directional antenna 18 suitably shaped to transmit and receive RF signals, covering all areas during data exchange between interrogator 12 and transponder 14. part of the driveway. In the depicted embodiment, an antenna 18 is used for both interrogation and reply signals. Antenna 18 is typically mounted about 18 feet above the road surface and is preferably positioned to ensure a constant link between interrogator 12 and transponder 14 regardless of site variations. Also shown is a control circuit or host interface 56 for communicating with the host 16 which can control all of the interrogators 12 at a toll booth.

Still referring to FIG. 4, the host interface 56 between the interrogator 12 and the host 16 is used for certain read/write operations, it allows information to be sent from the host 16 over the host connection 24, and formats the data for transmission via the transmitter 52 Give the car 26. Preferably, the communication with the host 16 is not performed until the transmitter 52 completes a complete read/write process with the transponder 14 . The host interface 56 also decodes the reply data from the transponder 14 via the receiver 54 and provides the reply data to the host 16. Antenna 18 is preferably weatherproof and designed to operate at the extreme temperatures expected in its environment.

Referring now to FIG. 4 in accordance with FIG. 3, for multiple lanes, preferably one interrogator 12 is provided for each lane. All interrogators 12 within a tollbooth 29 are coordinated in frequency, power output and antenna shape to minimize coverage area overlap and adjacent lane-to-lane effects. Typically a different carrier frequency is used on each interrogator 12 . In other words, adjacent interrogators 12 can have different carrier frequencies to minimize interference between adjacent interrogators 12, while non-adjacent interrogators can use the same carrier frequency (i.e. When arranged as #1, #2, #3, #4, #5 and #6, interrogators #1, #3, #5 can use one carrier frequency, while interrogators #2, #4, #6 can use another carrier frequency).

Receiver 54 of interrogator 12 detects the back-reflected modulated return signal from transponder 14 . The amplitude and phase of the returned signal is entirely related to the numerous reflections from multiple sources. Undesirable sources of returns include the following: unmodulated return signals from cars 26 in the same lane as the interrogator 12, either cluster-fill or non-bunch-fill; cars 26 in adjacent lanes 28a, 28b, 28c generated unmodulated and back-reflected modulated return signals; unmodulated return signals generated by fixed obstructions of unknown structure; and leakage signals from transmitter 52 to receiver 54 during transmission of continuous wave RF signals to transmitting interrogator 14.

Typically, one interrogator 12 is provided for each lane 28 in which there may be one data link. Furthermore, all interrogators 12 are identical and coordinated in time by a common reference oscillator 50, except for field-programmable internal electrical parameters such as lane position or other controlled parameters.

The components of the analog ASIC 32 and digital ASIC 34 are now described in more detail. Wake up block:

Referring to Figure 5, a more detailed view of the analog ASIC 32 is shown. Analog ASIC 32 receives an interrogation signal from antenna 30 . Modulation detector 70 removes the carrier signal from the received interrogation signal and passes it to first stage circuitry 62 . The first stage circuit includes a low pass filter 72 which removes high frequency components from the modulated detector 70 signal. The output of the low pass filter 72 is further passed to a threshold detector 68 which compares the output of the low pass filter 72 with a reference voltage. The output of the threshold detector 68 is therefore a binary signal, which serves as the input signal din for the digital ASIC 34 and the wake-up circuit 64 .

Further according to FIG. 5, the principle of the present invention described here has a significant advantage over the prior art in terms of power consumption. It is especially important to design the transponder 14 to consume the least amount of power. High efficiency is important for the transponder 14 whether the transponder 14 is powered by the received RF signal or whether the transponder is battery operated. To implement the principles of the invention described herein, the transponder 14 is typically in a detection mode with a 1/24 duty cycle sleep mode, drawing little power from a battery or RF power source. The energy consumed in this duty cycle sleep mode is only that required to wake up circuit 64 .

Referring again to FIG. 5, a high pass filter 74 is provided at the output of the detector 70 to filter out spurious low frequency signals from sources such as cellular telephones or other sources. A high pass filtered signal is provided from node "D" of filter 74 . In another embodiment, filter 74 may be a low pass filter if the transponder is activated by a low frequency (LF) modulated signal. Once the modulation detector or pulse counter 78 detects RF modulation of the frequency of interest, the wake-up circuit 64 sends an enable signal to the OR gate 97, which then sends a wake-up signal to the digital ASIC as long as the digital ASIC34 has an "F" clock signal, which can make digital ASIC34 enter the active state. In the first preferred embodiment, the desired modulation frequency is high speed modulation approximately 100 KHz to 400 KHz. In another preferred embodiment, a low frequency signal below about 1000 Hz is superimposed on a 915 MHz carrier, which is the desired modulating signal for pulse counter 78 .

Referring further to FIG. 5, for the first preferred embodiment, pulse counter 78 is preferably a gated 5-bit counter circuit. The gate is set at a specific frequency to detect the effective count range. To further save power, the wake-up circuit 64 has its power duty cycle. For example, every 16ms can open a 2ms time window (1/8 duty cycle), within the 2ms time window, the detector can work for 62.5μs; close 125μs (1/3 duty cycle). An example of such a duty cycle (1/8 x 1/3 = 1/24 duty cycle) would effectively reduce power consumption to 1/24 of the original value.

Referring now to FIG. 6, the wake-up circuit 60 is shown in greater detail. If modulation is detected, the digital ASIC 34 is activated and the pulse counter 78 is kept active by an "assert" signal from the main controller block 140 . If the modulating RF signal disappears, the main controller block 140 can keep the wake-up signal of the OR gate 97 valid by means of the "maintain" signal until the digital ASIC 34 functions are completed. The main controller block 140 will not disable the wake-up signal of the OR gate 97 until all pending functions are completed.

Still referring to FIG. 6, detector 70 preferably includes diode 82 which receives the signal at node "A" of antenna 30 and rectifies the signal. The shunt capacitor 84 and shunt resistor 86 form a low pass filter with known time constant to obtain 300KHz Manchester modulation from a 9.15MHz continuous wave RF signal. The high-pass filter 74 functions to filter out unwanted low-frequency components. High pass filter 74 includes series capacitor 88 and shunt resistor 90 . It is important to understand that the component values of detector 70 and high-pass filter 74 are chosen according to the modulation frequency that must be detected by signal "F" (FIG. 4) in order for digital ASIC 34 to operate, in other words, if the wake-up circuit 64 is desired to have a lower modulation frequency, the high pass filter 74 can have a very low corner frequency, or the high pass filter 74 can be omitted.

Referring further to FIG. 6 , gated comparator 92 receives the clock signal from pulse generator 76 at node "E". The input from pulse generator 76 acts as a voltage pulse that gates node "D". Therefore, the input from node "D" (flowing out of high pass filter 74) is the correct modulation frequency, and gated latch 96 acts to provide a high input signal to OR gate 97, the "F" signal Logical OR operation is performed with the hold signal of the main controller block 140 . Once the correct count is reached, the "F" signal is asserted and until a gate pulse from pulse generator 76 resets gate latch 96 . Gated latch 96 provides a high input to OR gate 97 . The output of OR gate 97 provides a "wake-up" signal to digital ASIC 34 (see FIG. 5 ) based on a signal from gated latch 96 or an "external hold" signal from an external microcontroller.

Referring now to FIG. 7, there is shown a timing diagram of the modulation detector of the preferred embodiment. The signal at node "D" is shown superimposed with a 300Rbps Manchester II "on-off" ook 915MHz continuous wave signal. Since the high pass filter removes the 915MHz carrier signal from the signal at node "A", a 300KHz modulated pulse appears on the signal at node "D". At node "E" is the gated latch output which is present during the duty cycle when wake-up circuit 64 detects modulation. The wake-up signal is the output of the OR gate 97.

FIG. 8 shows an overview of the functional blocks 100 , 108 , 140 , 148 , 155 , 172 , 190 , 214 within an embodiment of a digital ASIC 34 . In digital ASIC 34 , clock block 214 receives the wake-up signal of analog ASIC 32 . Once a wake-up signal is received, clock signals of preferably 3.6MHz, 1.2MHz, 0.6MHz and 0.3MHz are generated. These clock signals are transmitted to the above-mentioned functional blocks including at least the main controller block 140 . Clock block 214 preferably continues to generate clock signals independently of the state of the wake-up signal received from analog ASIC 32 until a clock disable signal is received from master control block 140 . Once the RF signal level is removed, and the main controller block 140 is in the idle state (i.e., the main controller block 140 has completed all its necessary work), a clock disable signal will be sent to the clock block 214, and after 0.5 milliseconds, Clock block 214 will disable all clock oscillations. The digital ASIC 34 will remain inactive until the next RF signal to the appropriate level is detected and the analog ASIC 32 issues another wake-up signal. The property of CMOS digital logic is that it draws power only when changing states, or when it is simply clocking, and consumes less power, so the quiescent leakage current of all digital CMOS clocked is very small (in the nanoampere range Inside).

Still referring to FIG. 8 , the receive buffer block 100 receives the data transfer signal din of the analog ASIC 32 . Receive buffer block 100 autonomously decodes the signal from main control block 140 and transfers the received data to main control block 140 or main memory 148 . The master controller block 140 receives the decoded data via the input data signal, possibly unbuffered. Alternatively, the decoded signal can be stored as a buffer in the receive register 122 (not shown, see FIG. 9 ), and the main controller block 140 sends an address signal radr11 to access the signal. The main controller block 140 may directly receive the data output rdat11 of the receive register 12 (see FIG. 9 ), or the main memory block 148 may receive the data output rdat11 and store therein. Receive buffer block 100 also preferably provides an incoming information signal to notify master controller 140 that an inquiry has been received. In addition, the receive buffer block 100 may also provide a message valid signal to the main controller block 140 informing it that the query has been received without error. The receive buffer block 100 may also provide a Manchester active signal to the lane discrimination block 108 through which the receive buffer block 100 is actively decoding the data transmission signal din.

Referring further to FIG. 8, the lane discrimination block 108 receives the din and Manchester activation signals and determines which lane 28 (FIG. 3) the vehicle 26 is traveling in. The lane discrimination block 108 is described in more complete detail below, and is also described in detail in US Patent Application No. 08/021,123 to Claude A. Sharpe (assigned to Texas Instruments Incorporated). Once it has been determined which lane 28 (FIG. 3) the vehicle 26 (FIG. 2) is traveling in, the lane discrimination block 108 may communicate this information to the main controller block 140 as an On Lane # (number) signal.

The main memory block 148 shown in FIG. 8 may store data received from the reception buffer block 100 described above. Also, the main memory block 148 may receive data from an external microcontroller (not shown) through the external interface block 172 . The data exchange is accomplished through address signal radr12 and data signal rdat22. The main memory block 148 can also receive data from an external microcontroller (not shown) via address and data signals μC abr and μC dat respectively. The main controller block 140 can enable or disable the main memory block 148 through a selection signal. External interface block 172 operates as an interface between main memory block 148 and an external microcontroller (not shown). The external interface block 148 receives an enable signal from the main controller block 140 and a clock signal from the clock block 214 . Preferably, the clock signal is 1.2MHz. In this embodiment, the external interface block 172 communicates with an external microcontroller (not shown) via serial clock signals, serial I/O signals, and some "handshaking signals" (μc rdy, R/W, and external sustain). communication, these signals will be described in more detail with reference to Figure 14.

FIG. 8 also shows a transmit block 155 . Transmitting block 155 works under the control of main controller block 140, preferably carries out back reflection modulation to the data on the continuous wave RF signal of interrogator 14 with back reflection modulator 41, transmits the data in the response signal to interrogator ( Not shown, see Figure 1). Transmit block 155 receives the data of main memory block 148 by data signal rdat21, and addresses main memory block 148 with address signal radr21, and transmitter block 155 uses signals (xmit data selection, start, xmit completes and launch count) with main control The device block 140 communicates. These signals will be described in more detail with reference to FIG. 14 .

The buzzer block 190 shown in FIG. 8 emits a designated tone to the operator through the buzzer 212 . The main controller block 140 sends a control signal, sound generation type, sound generation permission, sound generation start, etc. to the buzzer block 190 . These signals will be described in more detail with reference to FIG. 15 .

With further reference to FIG. 8, upon successfully completing a transaction comprising a query and a response without data errors, the transponder 14 may enter a period of, for example, 10 seconds during which it will Further queries with the same institution code as the transaction just completed are not answered. Compare the inquiry received during the non-response period with the previous organization code, and if the organization code is the same as the previous organization code, no response will be made. If not, a valid agency code was received during the non-response period and the transponder 14 can reply to the new challenge. receive/buffer block

Referring now to FIG. 9, the receive buffer block 100 components of the digital ASIC 34 are depicted. The receiver block 100 includes a Manchester decoder 102 , a CRC CCITT calculator 106 and a state controller 110 . The receiver block 100 decodes the signal sent by the interrogator 12, determines which lane the transponder is in, and calculates the input signal CRC. The Manchester decoder 102 receives the data transmission signal din of the analog ASIC 32 . Manchester decoder 102 contains a 3.6MHz digital phase-locked loop to synchronize the Manchester decoder with din. Manchester decoder 102 provides at its output a serial data stream SRDT taken from data transfer signal din and a clock signal SRCK. Manchester decoder 102 also provides a Manchester activation signal to lane discrimination 108 (see FIG. 8). The role of the Manchester activation signal will be described below with reference to FIG. 10 .

Still refer to FIG. 9 . The serial data stream SRPT is fed into the CRC generator 106 . The CRC of the input information is calculated using the CCITT polynomial (X ¹⁶ +X ¹² +X ⁵ +1). Receive controller 110 determines which data bits in the CRC to calculate (additional bits that are part of the CRC are not counted) and activates CRC generator 106 to begin calculating the CRC after all the additional bits have been received. A byte calculator 114 is provided to receive the serial data string and calculate the number of bytes received. By incrementing the byte counter 114 every 8 serial data clock pulses, the number of bytes can be counted and the result of the count sent to the main controller block 140 (see FIG. 8 ). An 8-bit holding register 116 is provided to hold bytes sent from the serial parallel shift register 112 .

A data comparator 120 is provided, and the receiving controller 110 can compare the data of the serial-parallel shift register with the data stored in the SRAM 118 . In this mode, for example, the transponder identification number can be stored in SRAM 118 and compared with the ID code obtained from the serial data SRDT received from receiving controller 110 through serial parallel shift register 112 . Therefore, the receive buffer block 100 can work independently from the main controller 104 . Receive controller 110 detects Manchester code data received on the Manchester active line of Manchester decoder 102 . The receive controller 110 also bypasses the CRC generator 106 or resets the CRC generator 106 using the control line crc bypass and crc clear signals. The controller 110 preferably resets the CRC generator 106 and the byte count register 114 upon detection of the onset of reception of the Manchester decode signal. The controller 110 can control the receiving register 122 to store the data of the 8-bit holding register 116 . ID block

Referring now to FIG. 10, the lane discrimination block 108 includes a lane discrimination controller 124 which is sampled at three specific times after the interrogator 12 begins interrogating the transponder 14 (see FIG. 3). Lane discrimination controller 124 stores on capacitors 126a, 126b, 126c samples of the voltage on node "B" of analog ASIC 32 (see FIGS. Node "B" is sampled by track discrimination controller 124 during sampling periods 45, 46, 47 (see Fig. 3) to extract field strength pulses 44a-c (see Fig. 3). Switches 132a, 132b, 132c respectively connect the capacitors to node "B" to input voltage (see Figs. 5, 8). After a certain time (after stabilization) the output of the comparator 130 is sampled to determine which signal is stronger and thus which lane 28a, 28b, 28c the transponder 14 is located in.

Still referring to FIG. 10, the lane discrimination block 108 is preferably capable of sampling field strength pulses autonomously without manipulation from the main controller block 104 (see FIG. 8) or other controllers. Lane discrimination controller 124 receives the Manchester activation signal from receive buffer block 100 (see FIG. 8 ). Upon detection of the Manchester decode signal (Manchester active = high), the lane discrimination controller 124 starts a long timer 138 and waits for the completion of the incoming query (see FIG. 3). After long timer 138 has completed its period, lane discrimination controller 124 begins monitoring node "B" for field strength pulses 44a-c (see FIG. 3). A short time timer 137 provides sampling timing between pulses of 3.3 μs. Using this 3.3 μs timing, the lane discrimination controller 124 can be properly synchronized with the sampling periods 45, 46, 47 (see FIG. 3). It should be understood that the timing periods described above are examples only and that other periods may be used depending on system design parameters such as the number of lanes to be identified and the lengths of interrogation signals and timing pulses. Master Controller and Comparator Block

Referring to Fig. 11, the main controller block 140 controls all the actions of the digital ASIC 34. The main controller block 104 is woken up by a "wake up" signal from the analog ASIC 32 (see FIG. 8). The master controller 104 then makes a decision based on the content of the input information and the current transaction sequence. The comparator 142 fetches the input information from the receive buffer 122, checks the validity of the received information with the calculated CRC, and compares the input information. Master controller 104 executes the appropriate command sequence.

Still referring to Figure 11, the record type code (16 bits) of the input query is used to determine the order and type of comparisons to be made. This code uniquely specifies the information fields and functions of the transponder as permissible. For example, hexadecimal numbers 1 to 7FFF can be set on one side of the transponder information structure, and 8000 to FFFF can be used for the reader transponder information structure. After the queried data is tested for errors with the CRC, the record type code is checked and the comparator circuit 142 sets a flag according to the record type code. The main controller 104 acts on the flag generated by the comparator circuit 142, and performs appropriate actions, analyzes the content of the data in the inquiry signal, generates the response data of the transmitter 14, and sends the data to an optional external microcontroller (not shown) Send out a signal, or implement an ASIC sustain function (discussed below under the header "Sustain Modes and Messages"). The main controller 104 also provides the address of the main memory block 148 where the data is stored, and the main memory block 148 (see FIG. 8 ) is loaded with information. Typically, the source of this data is a received interrogating external microcontroller (not shown).

With further reference to FIG. 11 , the transaction calculator 146 is an 8-bit counter that, if the transaction is successfully completed (e.g., the interrogator 12 receives a valid ID code from the transponder 14), is the acknowledgment at the interrogator 12 (see FIG. 1 ). The counter is incremented by 1 when the message ends. Transaction calculator 146, although part of main controller 104, is still addressed within the address space of memory block A. Transaction counter 146 provides a recurring 8-bit number that can be used to track successful billing transactions and maintain bookkeeping operations (much like a "check number" is kept track of an individual's banking transactions). The transaction counter value is generally not programmed, but it can be reset to zero by resetting the ASIC through an external reset pin or other methods.

As can be seen from FIG. 11, the main controller 104 also functions as the central core of some transponders 14, in addition to performing functions related to receiving and processing interrogation information. A number of control signals pass through the main controller 104 and from it to other functional blocks 100 , 108 , 140 , 148 , 155 , 172 , 190 , 2140 . The main controller 104 receives the timing of the exemplary 3.6 MHz clock of the clock block 214 . Clock block 214 preferably continues to generate a clock signal independent of a wake-up signal received from analog ASIC 32 until a clock disable signal is received from host controller 104 .

Still referring to FIG. 11 , the host controller may receive data from the receive buffer block 100 without buffering the incoming data signal. Another way is to store and buffer the decoded signal in the receiving register 122 (not shown, see FIG. 9 ), and send an address signal radr11 through the main controller block 140 to access. Main controller 104 also sends address signal wadr21 and allows main memory block 148 to store data within main memory block 148 with a "select" signal. Once main memory block 148 is so selected, it can receive data directly from receive buffer block 100 via signal rdat11. Receiver block 100 also preferably provides an input information signal informing main controller block 140 that an inquiry is being received. In addition, receive buffer block 100 may also provide a message valid signal to main controller 140, informing it that an inquiry has been received without error. With further reference to FIG. 11, the main controller 104 receives the lane # signal from the lane discrimination block 108 to determine which lane 28 (FIG. 3) the vehicle 26 with the transmitting interrogator is traveling in (see FIG. 2). The transmit block 155 operates under the control of the main controller block 140, preferably by back-reflecting modulation of the data on the continuous wave RF signal of the interrogator 14 using a back-reflection modulator 41, in the form of a reply signal to the interrogator (not shown). Shown, see Figure 1) transmit data. Transmitter block 155 receives data from main memory block 148 via data signal rdat21 and addresses main memory block 148 with address signal radr21. The transmit block 155 communicates with the main controller block 140 with signals (Xmit data select, start, Xmit complete, transmit count, etc. signals). A detailed description of these signals will be made with reference to FIG. 14 . The main controller 104 controls the buzzer block with control signals such as utterance type, utterance permission, and utterance start. These control signals will be described in detail with reference to FIG. 15 . Memory block:

The main memory 150 shown in FIG. 12 has memory blocks A, B, C, D, and M. As shown in FIG. Preferably, each of the exemplary five memory blocks may be used to transmit information to interrogator 12 via transmit block 155 (see FIG. 8). The memory 150 is preferably a multi-port SRAM capable of simultaneous read and write operations. Preferably, the memory 150 is an SRAM with a capacity of 80 bytes, however, the memory 150 may be a non-volatile memory (eg, EEPROM, ROM). Additionally, more or less than 80 bytes of memory may be used in AVI systems or other systems in accordance with the present invention.

Still referring to FIG. 12 , select multiplexers 152 , 154 allow writing into memory from the host controller 104 , via the external interface block 172 , from an external microcontroller (not shown). The interrogator 12 can ask the memory block A, B, C, D or M of the transponder 14 to transmit 16 bytes of data by means of a query message. As an alternative, the interrogation message may instruct the transponder to send a longer data burst, such as a 32-byte data transmission. For example, the 32-byte data transfer information may include the transfer information of connecting memory blocks A and B, or the transfer information of connecting memory blocks A and C, memory blocks A and D, and memory blocks A and M.

An example of the basic functionality of each memory block (A, B, C, D, and M) is as follows:

Memory block A: basic account information;

Memory block B: regulation enforcement information;

Memory block C: toll road entrance information memory;

Memory block D: microprocessor output data transmission buffer;

Memory block M: maintenance and control functions

Two special registers are part of the address space of memory block A, they are the transaction counter 146 (not shown, see Figure 11) and the flags register. Although the transaction counter 146 is part of the main memory addressing space, it is included in FIG. 11 and its description because of its logical relationship to the main controller block 140 . The second dedicated register for memory block A is the flags register. This 8 bit register indicates the capabilities of the transponder 14 to the interrogator 12, certain bits are programmed by the service center. The special bits of the flag register are defined as follows: bit# externally writable? Function 0 yes 0 = no balance stored in the transponder 1 = account balance stored in the transponder 1 yes 0=legal account 1=illegal account 2 yes 0 = no lane discrimination 1 = lane discrimination allowed 3 yes 0 = internal label, 1 = external label 4 no 0=Legal 1=Illegal for external installation and removal 5 yes (reserve) 6 no Battery Consumption Meter LSB 7 no Battery consumption metering MSB

Bits 0 and 2 are reader information bits, set by the service center. Bits 1 and 3 correspond to enabling or disabling ASIC circuits, set by the service center. Bit 4 is set by the interrogator 12, but can be reset at the service center. Bits 7 and 6 are the high order bits for battery drain metering.

An exemplary structure of memory block A is: byte# Function 1 Account ID Byte 1, MSB 2 Account ID Byte 2 3 Account ID Byte 3 4 Account ID Byte 4 5 Account ID Byte 5 6 Account ID Byte 6, LSB 7 Account Balance Byte 1 (0 if None) MSB 8 Account Balance Byte 2 (0 if None) LSB 9 (dedicated) 10 (dedicated) 11 (dedicated) 12 (dedicated) 13 (dedicated) 14 (dedicated) 15 flag register 16 transaction#register

The structure of memory block B may be "free style", or not as rigidly defined as memory block A. The content of memory block B (16 bytes) can be written by a charging authority or other authorized entity at the service center, but can be read by the reader 12 . For example, memory block B may contain read-only type information (regulatory enforcement information, license plate number, establishment code, etc.).

The structure of the memory block C can also be "free style". The purpose of this memory block is to pass information (eg toll road entrance information) from one reader to another interrogator 12. For example, the first interrogator 12 can send data to store information in the transponder 14, and the data master block 140 (see FIG. 8) can store it in the memory block C by sending the appropriate addressing information. Another subsequent interrogator 12 may send a suitable transaction record code (for example Type 3A described in the header "Transaction Record Type Code" below) to read the contents of memory block C. Interrogators 12 that differ by these methods can communicate efficiently.

Memory block D is specified by the main controller 104 as a buffer (16 bytes) for sending information from an optional external microcontroller (not shown) to the interrogator 12 or service center. The content of memory block D (16 bytes) is mainly loaded by an external microcontroller (not shown). If the AVI system 10 has no external microcontroller (not shown), block D can be used freely as another 16-byte message that can be loaded by the service center or interrogator 12, read by the service center or device 12 to read. As an alternative to storing functions accessed by the microcontroller, block D can be used as additional memory for normal operation even when a microcontroller is present.

Maintain block register functions: byte# Function 1 Institution Code, MSB 2 Institution Code, LSB 3 configuration register 4 Analog ASIC Configuration Word, MSB 5 Analog ASIC Configuration Words 6 Analog ASIC configuration word, LSB 7 8 9 10 11 12 Battery Drain Meter Byte 1, LSB 13 battery drain gauge byte 2 14 battery consumption meter byte 3 15 battery drain gauge byte 4 16 Battery Drain Meter Byte 5, MSB emitter block

Referring now to FIG. 13 , transmitter block 155 includes multiplexer 156 , one byte register 158 , encryption circuit 160 , CRC generator 162 , header code generator 164 , FSK modulator 166 and controller 168 . Encryptor 160 encrypts the serial data stream to be transmitted, passes through CRC generator 162 , and transmits through FSK modulator 166 . Once commanded by the master controller block, the transmitter block control circuit 168 will be enabled. Transmit controller 168 then transmits a "self-synchronization" signal that receiver 54 within interrogator 12 can use to self-synchronize with transponder 14 responses. An exemplary self-synchronizing signal may be the binary and hexadecimal values: 10101010 and AA, respectively. Once self-synchronization with the interrogator receiver 54 is complete, the transmit controller 168 sends the appropriate memory block data to the master controller 104 clocked at 300KHz. The CRC circuit 162 outputs a CRC when the main controller 104 sends to the end of data. Once the transmission of the CRC bits is complete, the transmitter block 155 goes into an idle state, signaling the host controller 104 to disable the transmitter clock block 214 for minimum power consumption.

The encryption circuit 160 uses multiple keys. The encryption function can be deactivated at the service center. The CRC generator 162 calculates the CRC using the CCITT polynomial CX ¹⁶ +X ¹² +X ⁵ +1). The data input to CRC generator 162 is an encrypted data stream. The CRC value is always sent as an unencrypted message. Interface controller block:

FIG. 14 shows the external controller interface circuit 172 . Interface circuit 172 provides flexibility in the design of transponder 14, allowing further system upgrades with minimal effort. Interface circuitry 172 may enable an external microcontroller (not shown) to communicate with transponder 14 . The main controller 104 can activate the interface controller 174 with an "enable" signal between the two functional blocks (see FIG. 8). When the interface controller 174 is woken up by the external microcontroller, it detects that the "external hold" signal is active and communicates with the external microcontroller. Interface circuit 172 overcomes the problem of designing transponder 14 for future compatibility with unknown external circuits with unknown future interface requirements. In order to allow unspecified external circuitry or an external microcontroller to access the transponder's memory 150 at a clock rate of its own choice, a shift register 186 comprising an 8-bit shift register and a 138-bit shift register (146-bit bit register) are provided. ) 184 buffer memory.

Interface controller 174 forms the heart of interface circuitry 172 . In "write" mode, the transponder 14 communicates with an external microcontroller. The interface controller 174 receives information from the main controller 104 through the control line μcMSG, and wakes up the external microcontroller with the signal μcRDY. Data is loaded from main memory 150 into 8-bit shift register 186 . Once a byte is loaded into the 8-bit shift register 186 in parallel, the 8 bits are serially cycled through the multiplexer 180 into the 138-bit shift register. The function of the multiplexer 180 is to enable data to be clocked from the 8-bit shift register 186 into the 138-bit shift register 184, or to enable data to be clocked from an external microcontroller through the serial I/O buffer 178 rate entry. As can be seen from FIG. 14, data traverses from serial I/O buffer 178 through multiplexer 180 while the "cycle" signal is held low. Data is passed from the serial output of the 8-bit shift register 186 through the multiplexer 180 while the "cycle" signal is asserted high. Thus, data is loaded into 8-bit shift register 186 in groups of 8 and cycled into 138-bit shift register 184 until the information is loaded. Once the information is loaded, the "cycle" signal remains low. Alternatively, an external microcontroller can activate the interface controller regardless of whether the external RF field has activated the transponder 14 by raising the "external sustain" signal. In either case, the interface controller 174 sends a 7-bit address RADR22 to the main controller block 148 so that data can be loaded or retrieved from the 8-bit register 186 via RDAT22.

One of the advantages of inserting the interface circuit between the main controller 104 and the external microcontroller is that by buffering and clocking the 146-bit registers 186, 184, the external microcontroller is free to clock its own serial clock signal Signals are sent to or from 146-bit registers 186, 184 via multiplexers. As shown, the interface controller 174 controls the multiplexer 182 to pass the serial clock of the external microcontroller to the 146-bit registers 186, 184, or to send its own clock to the 146-bit registers 186, 184 . Therefore, you can flexibly decide to load and fetch data to and from the registers at the actual clock rate of the external microcontroller.

Serial I/O buffer 178 enables data to flow in either direction, which method relies on interface controller 174 signal control line DIR. In addition, not only can an external microcontroller wake up the transponder 14 via the "external hold" line, but the interface controller 174 can also output a signal on μc rdy to wake up the external microcontroller. Bit counting circuit 176 monitors the incoming data stream and is used to allow interface controller 174 to determine where the data within circular shift register 184 begins. The function of the interface controller 174 is to read and write 16 bytes of data to an optional external microcontroller, and perform serial programming (configuration) on the analog ASIC32.

The interface controller 174 can directly communicate with the main memory 150 through the bus μc MSG and the bus RADR22[0:6] (address), DATA[0:7] (data) and μc ADR[0:7].

The 8-bit register 186 is first loaded with a 3-bit command word. This 3-bit command word informs the external microcontroller of the attributes of the subsequent message. Subsequent bytes of information are loaded one byte at a time, then shifted out and cycled through multiplexer 180 into the 138-bit shift register. After the subsequent information load is complete, the shift registers 184, 186 count the time until the first two bits appear at the beginning of the 8-bit register 186 again. At this time, the clock select line can be maintained, so the serial clock of the external processor can be used to record the time when the data is shifted out of the shift register 184, 186, and the control line entering the serial I/O buffer 178 can be maintained so that the data can be clocked. output, and maintains μc rdy to wake up the external microcontroller.

In the first mode, upon wake-up, the R/W signal of the external microcontroller is asserted low. The external microcontroller then shifts in the first three bits serially to determine the attributes of the subsequent information. After the external microcontroller has recorded the same number of bits as the number of bits required for the three-bit message from the transponder 14, the microcontroller asserts its R/W signal high to indicate that it has finished receiving data. Once the R/W signal is seen asserted high, the interface processor sets the serial I/O buffer 178 to input mode and asserts the cycle signal low so that data can be reloaded into the shifter in a circular fashion. The bit registers 184, 186, again set the clock signal to the interface controller 174 so that it can again control the loading and unloading of the shift registers 184, 186.

In another mode, if the external microcontroller has data to send to the digital ASIC 34, it can wake up the interface controller 174 with an "external hold" signal. As before, the interface controller sets up the clock multiplexer 182 to pass the serial clock from the external microcontroller. In this mode, R/W is maintained at high level. The external microcontroller then serially shifts the data directly into the 138-bit shift register 184 and continues until the necessary data has been sent and the data has been shifted 146 times to load the first bit of information into 8-bit shift register 186 . The interface controller 174 may again control the clock by maintaining the clock select line to the clock select multiplexer 182 low. Data may then be fetched from 8-bit shift register 186 and loaded into block D of main memory 150 . One byte of data is fetched at a time, after which a new byte of 138-bit register 184 is serially shifted into 8-bit register 186 with eight clock transitions. Unloading and shifting continues until all information has been transferred to main memory 150 . ASIC command structure and protocol:

The ASIC 34 of the preferred embodiment uses the CALTRANS specification as its communication protocol. The CALTRANS specification specifies many aspects of the information content, and the ASIC command structure complies with the CALTRANS requirements.

The reader 12 uses 4 bytes to command the transponder 14: the record type (2 bytes) and the status (2 bytes). The record type is sent in the first 2 bytes, followed by the header code in the registration and confirmation message, and the status code is only included as part of the confirmation message.

Depending on whether the transponder 14 is an ASIC-only unit or whether the transponder 14 has an ASIC 34 plus an external microcontroller, the record type and status code affect the ASIC 34 differently. Figure 14, in conjunction with the description herein, illustrates an ASIC interface circuit for interfacing with an external microcontroller.

The use of CCITT·CRC polynomials and the "clearness check" on the record type and information structure ensure that there is no error and correct charging. If the ASIC conflicts with an unknown record type or message it ignores that message, rendering it useless.

Structure of the record type (all information)

The record type consists of the first two bytes and the following registration and confirmation information header codes. It can work by itself, or by sending additional commands using status codes (in confirmation messages). The basic function of a record type is to tell the receiver (transponder or interrogator) how to decode the fields within the message it has just received and transmit the resulting instructions to the ASIC.

The CALTRANS specification requires that the range 0x0001 to 0x7FFF be reserved for transponder reader information and the range 0x8000 to 0xFFFF be reserved for reader transponder information in the record type code. Transaction record type code:

It will be appreciated that the ASIC (associated with a valid institution code) has an effect on the following record types.

(If the lane discrimination is prohibited by the flag register on the transponder 14, the lane position in the record type can be ignored, and the transponder 14 can respond to the registration information regardless of the lane position.)

0×8000 Type 1 registration information—requires transponder 14 in (any lane)

The memory block A is sent in the next response message.

0×8001 Type 2 registration information—requires transponder 14 to be in (any lane)

The memory blocks A and B are sent in the next response message.

0×8002 Type 3 registration information—requires transponder 14 to be in (any lane)

The memory blocks A and C are sent in the next response message.

0×8003 Type 4 registration information—requires transponder 14 in (any lane)

The next response message is sent to memory blocks A and D.

0×8010 Type 1A registration information - requires transponder 14 to be in the next lane

A's response message is sent to memory block A.

0×8011 Type 2A registration information – requires transponder 14 to be in the next lane

A's response message is sent to memory blocks A and B.

0×8012 3A registration information - request transponder 14 in the next lane A

The response message of is sent to memory blocks A and C.

0×8013 Type 4A registration information – requires transponder 14 to be in the next lane

A's response message is sent to memory blocks A and D.

0×8020 Type 1B registration information – requires transponder 14 to be in the next lane

B's response message is sent to memory block A.

0×8021 Type 2B registration information – requires transponder 14 to be in the next lane

B sends memory blocks A and B in the response message of B.

0×8022 Type 3B registration information – requires transponder 14 to be in the next lane

B sends memory blocks A and C in the reply message.

0×8023 Type 4B registration information – requires transponder 14 to be in the next lane

B sends memory blocks A and D in the response message of B.

0×8030 Type 1C Registration Information – Transponder 14 is required to be in the next lane

C sends memory block A in the response message of C.

0×8031 Type 2C Registration Information – Transponder 14 is required to be in the next lane

C sends memory blocks A and B in the reply message.

0×8032 Type 3C registration information—requires the transponder to be in the next lane C

The memory blocks A and C are sent in the response message.

0×8033 Type 4C registration information—requires the transponder to be in the next lane C

The memory blocks A and D are sent in the reply message.

The following defines the record type of the response information

0×0001 Transaction type 1 response

The transponder 14 replies with memory block A (16 bytes).

0×0002 Transaction type 2 response

The transponder 14 replies with memory blocks A and B (32 bytes).

0×0003 transaction type 3 response

The transponder 14 replies with memory blocks A and C (32 bytes).

0×0004 Transaction type 4 response

The transponder 14 replies with memory blocks A and D (32 bytes).

The following defines the record type of confirmation information:

0×C000 Transaction type 1 confirmation information——(transaction successful).

The transaction counter 146 is incremented by 1, and the transponder 14 enters the ten second

"Control" cycle. Microcontroller message generated. Buzzer sounds three short beeps

high pitched.

0×C001 Transaction type 2 confirmation information——(transaction in progress). launch should

The responder responds with the next appropriate registration information. Status codes can contain other

Foreign instructions. Generate microcontroller information. This is the main "do not move

Make" code.

0×C002 Confirmation information of transaction type 3——(open and enter block C). Bundle

The 16 bytes after the status code are written into memory block C. transponder 14

Enter a ten-second "suppress" period. The status code and the 16 after the status code

The bytes will be formatted as microcontroller information (if there is a microcontroller

device). The buzzer will sound 1 short high tone.

0×C003 Transaction type 4 confirmation information——(load block D). put the status code after

16 bytes of are written to memory block D. transponder 14 into ten

Seconds "suppression" period. The buzzer emits a short high tone 〖ZK)〗.

0×C004 Transaction type 5 confirmation information——(bounce transaction). read

    Fetch the already read flag register and find that the bounce bit has been read by the previous

Transaction sequence settings for exporter 12. Transaction counter 146 is not incremented.

The transponder 14 enters a ten second "inhibit" period. generate microcontroller

Controller information. (This can be used to suppress the rebound of the transponder 14,

Instead of the transaction type 1 record type. ) buzzer beeps twice

Bass.

0×C005 Transaction type 6 confirmation information——(load block C). put the status code after

The 16 bytes of are written to memory block C. Transponder 14 replies

- Registration information. Put the status code and the 16-byte format after the status code

into microcontroller information.

0×C006 Transaction type 7 confirmation information——(load block D). put the status code after

16 bytes of are written to memory block D. Reflective transponder 14 answer

- Registration information.

0×C007 Transaction type 8 confirmation information——(microcontroller information). Put the state

The 16 bytes after the code and status code are formatted as microcontroller information.

The transponder 14 enters a ten second "inhibit" period. (this is used to

  Load EEPROM history files. ) The buzzer emits 3 short high-pitched beeps.

0×C008 Transaction type 9 acknowledgment information - (transponder 14 open).

Confirmation contains account for previously suppressed transmit reply 14

No. Now transponder 14 becomes active and answers the next login

Write down the information.

0×C009 Transaction type 10 confirmation information——(Transponder 14 is suppressed

System. ) does not trade. Although transponder 14 replies, it

is not the correct account for the turnpike. transponder 14 access

Ten second "suppress" period. Generate microcontroller information. Buzzer sent

Make a long bass sound.

0×C00A Transaction Type 11 Acknowledgment Information——(Transponder 14 is suppressed)

Do not trade. Transponder 14 enters ten second "suppression" cycle

Expect. No microcontroller information is generated.

0×C00F Transaction Type 16 Acknowledgment Information - (Bounce Transponder). exist

  Set the bounce bit in the flag register, and add the transaction counter 146

1. Generate microcontroller information. transponder 14 continue transponder

structure or maintain a code registration request, but the reader 12 will immediately recognize

There is a problem with the user account, the transponder 14 asks the service center to release

put. buzzer

  Make 2 long low tones. The structure of the confirmation message status code:

Use a dedicated field to encode the 16-byte status code of the acknowledgment message. The first three bits (MSB) are encoded as:

000 not working

001 (reserved)

010 (reserved)

011 (reserved)

100 Decrease account balance (μc)

Then the last thirteen digits describe the unsigned value to be subtracted from the current balance

An integer value of .

101 Microcontroller function W/O data (μc). Then the next thirteen digits describe

The microcontroller function to be implemented.

110 Microcontroller functions with data (μc). Then the last thirteen characters describe

Describe the number of data bytes following (such as n plus 1 multiplied by 2) that is: 000=following 2

data bytes; 001 = followed by 4 data bytes; 11 = followed by 16

data bytes.

111 (reserved) institution code:

The organization code is equivalent to the two bytes sent after the record type in the registration information, which consists of MSB byte and LSB byte. The ASIC34 can store user-defined two bytes for these comparisons.

In order for the transponder 14 to immediately respond to the interrogator 12, one of the following two conditions must be met:

1) The MSB and LSB bytes of the institution code entered must match the user-defined institution code, or

2) The MSB byte of the entered organization code matches the user-defined MSB organization code, and the LSB byte must match the internally defined 0xFF "group" response code.

As an example, a user-defined organization code within an ASIC could be 0x5061 with a 0xFF group response code. In this case, in order for the ASIC to respond immediately, the institution code must be entered as 0x5061 or 0x50FF. Any other input of the agency code will not cause the ASIC to respond immediately. If these conditions are not met, a microcontroller message will be generated. The microcontroller then checks its internal valid agency code table and modifies the ASIC34 user-defined agency code to the input agency code (if appropriate). The reflective transponder 14 will be able to answer the interrogator 12 after modification of the reflective transponder 14 user-defined organization code register and account balance register. Transponder 14 has an issuer identification code programmed into its account number. It is the responsibility of the lane controller or interrogator 12 to check the true validity of the reflective transponder for the assigned location and to perform the correct transaction. Better information structure:

Wake up structure:

Length: 10 bits

Sequence: wake-up modulation (ten Manchester coded "1") registration structure:

Length: 10.5 bytes

Sequence: header code (1.5 bytes)

The record type (2 bytes)

  Institution code (2 bytes)

Time (2 bytes)

Encoding key (1 byte)

CRC (2 bytes) response structure:

Length: 21.5 bytes or 37.5 bytes

Sequence: header code (1.5 bytes)

The record type (2 bytes)

  Memory block A (16 bytes)

Additional data (16 bytes) optional CRC (2 bytes) confirmation structure:

Length: 19.5 bytes or 35.5 bytes

Sequence: header code (1.5 bytes)

The record type (2 bytes)

  Reflective transponder ID (6 bytes)

  Reader ID (6 bytes)

  Status code (2 bytes)

Additional data (16 bytes) optional CRC (2 bytes)

ASIC 34 generally expects transactions to complete in the same cycle (ie, during the same wakeup-register-acknowledgement sequence). However, the ASIC will listen for a confirmation message containing a Specialized Type 9 whose account number may be open if the registration message's agency code 'quiet' period is still valid. Reader-ASIC message timing example:

(each Manchester encoding bit width is 3.333μs) cycle bit# bit#/maximum Time (μs) min Time (μs) max Open the entrance (μs) Open outlet (μs) off (μs) wake 10 33.3 33.3 33.3 time delay 100 100 100 100 to register 84 84 280 280 280 280 280 time delay 10 10 10 10 lane pulse 10 10 10 10 time delay 80 80 80 80 answer 172 300 573.3 1000 573.3 1000 573.3 time delay 100 100 100 100 confirm 156 284 520 946.7 946.7 520 520 time delay 10 10 10 10 total 1716.6 2570 2143.3 2143.3 1716.6

The timing described above is exemplary only. Additional timing protocols, procedures, and techniques can be learned through this description.

Modifications and combinations of the illustrated embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art in view of the foregoing description. Such modifications or embodiments are therefore intended to be covered by the appended claims. Special features:

Power-on reset: The digital ASIC34 includes power-on reset circuitry to properly initialize the circuit when a battery is connected. An external reset terminal is also provided for manual reset during maintenance operations/tests. A reset can be initiated by grounding the external reset terminal, which will cause the digital ASIC 34 to lose all previously programmed data, clearing all counters and registers.

Battery Consumption Metering: Measure battery consumption of power-on stages 2 and 3 with dedicated conversion/computation circuitry on the digital ASIC34. The battery drain for both stages is counted in a dedicated register whose two upper bits are included as part of the flags register. The state of the two (MSB) bits indicates:

00: Use <174mAH

01: Use 174mAH-348mAH

10: Use 348mAH-522mAH

11: Used to >522mAH buzzer output:

The digital ASIC 34 of the preferred embodiment is capable of driving a pressure transducer, enabling it to generate tones in response to certain reflective transponder functions. A high beep (1172hz) may indicate that the function is complete. Bass (586hz) can generally indicate that the function is not complete. The long sound is about 3/4 second (872ms), and the short sound is about 1/4 second (218ms), with an interval of about 1/2 second (436ms). Sound signal example: Location sound transaction Successful 3 sounds of short -sound data loading successful short treble bad debt status 2 sound long bass toll road/account loss 1 sound long bass maintenance mode and information

A maintenance mode is provided in which a charging authority or other authorized entity can permanently store subscriber information in the memory of the transponder. This information includes: encryption type; whether encryption is used; whether lane discrimination is performed; FSK frequency used; transport information about the payload, such as weight, value or toxicity, etc.; whether a microprocessor is connected to the transponder 14; user account number #; the amount of currency stored on the transponder 14. An authorized unit puts the transponder into maintenance mode at the programming station by sending an access code, before which the transponder is not activated. The transponder 14 may provide a maintenance mode confirmation signal to the interrogator 12 for confirming to the interrogator that the transponder is in maintenance mode. The agency then programs the transponder with the user information. A change in the organization code or a time longer than 10 seconds will cause the maintenance mode to stop.

The following functions are valid only when maintenance mode is valid. In maintenance mode, the lane discrimination counter 124 is disabled. The dedicated message formats used to test ASICs in maintenance mode include: Registration information: Type 1 Maintenance registration information:

The transponder is requested to transmit memory blocks A and B in the next reply message. Type 2 maintenance registration information:

The transponder is requested to send memory blocks A and C in the next reply message. Type 3 maintenance registration information:

The transponder is requested to send memory blocks A and D in the next reply message. Type 4 maintenance registration information:

The transponder is requested to send memory block A in the next reply message. Type 5 maintenance registration information:

The transponder is requested to send the memory block A and the maintenance block. Type 6 maintenance registration information:

Disconnect the battery consumption measurement clock, load the test data to the register, add a clock to the register, and read the register value in the response message. The old content must be saved, the new value calculated and stored in the battery drain register before the transponder returns to operational mode. The transponder will reply with a Type 2 reply message. Type 7 Maintenance Registration Information

Requests the transponder to send everything in the receive buffer. This proprietary registration message format is used to load test data directly into the receive buffer. The transponder will reply with an unencrypted Type 6 reply message. Response information type 5 maintenance response information:

The transponder replies with the memory block A and the maintenance block. Type 6 maintenance response information:

The transponder replies with the contents of memory block A and the receive buffer. This information is not encrypted and does not contain the tag's account number. The Interrogator has stored the Tag's account number from a previous registration/response sequence, and replies with the account number in the corresponding acknowledgment message. Confirmation information: Type 1 maintenance confirmation information

Do not work. Status codes are ignored. Type 2 maintenance confirmation message

Load the information following the status code into memory block D. Status codes are ignored. Type 3 maintenance confirmation message

Load the information following the status code into memory block C. Status codes are ignored. Type 4 maintenance confirmation message

Load the information following the status code into memory block D. Status codes are ignored. Type 5 maintenance confirmation message

Load the information following the status code into memory block A. Status codes are ignored. Type 6 maintenance confirmation message

This information indicates that the latest information of the state is written into the maintenance register. Status codes are ignored. Type 7 maintenance confirmation message

This information indicates that the status code and the information after the status code are written into the microcontroller. Status codes represent attributes of the instruction. Type 8 maintenance confirmation message

The bounce bit is reset. Do not perform other operations. The status code is ignored. low frequency modulation interrogator

Figure 18 shows another embodiment of an interrogator. This architecture can be used to reduce transponder power consumption by superimposing low frequency modulation on top of normal RF interrogation. By using this low frequency modulation, the field detector or wake-up circuit 64 can be configured to be sensitive to very low modulation frequencies, such as 90 Hz, rather than to typical communication modulation frequencies. The interrogator 12 superimposes this low frequency modulation with a heterodyne oscillator or mixer 222 as shown in FIG. In practice, the low frequency modulation can be superimposed by post-processing the RF interrogation signal, such as mixer 222 (shown in FIG. 18). In other words, it is possible to incorporate overlapping into the generation of the RF interrogation signal using, for example, a so-called "squitter" modulation technique. This technique allows high data rate signals to contain low frequency components for signal detection. Therefore, the data is transmitted with a pulse train having a pulse rate equal to the low frequency signal to be detected. For example, to achieve a low frequency (LF) component of 100Hz, one could send 5 seconds of data, then hold another 5 seconds in a known state (high or low). Then another 5 seconds of data are sent, followed by another 5 seconds of "no data". Repeating this in succession produces 100 Hz spectral lines which can be detected by a simple low pass filter 74 which passes 100 Hz and rejects high frequency signals. The gap oscillator modulation technique is preferably implemented by software residing within the host computer 16, transmitter 52 or interface circuit 56. Instead of the method gating function described above, another transmission format can also be used. The square wave gating function has alternating periods of "transmit" and "non-transmit" (so the transmission rate is modulated between 0% and 100% of maximum). The length of the data "non-transmission" period may increase in a linear fashion from minimum period to maximum period. This is triangular data rate modulation in which the pulse rate varies over time from a low (high) rate of 100 Hz to a high (low) rate such as 300 Hz as previously described. This modulation provides an additional means by which the receiver can identify interrogation signals and exclude sources of interference. Other secondary modulation waveforms such as sine waves can be used in this application. As mentioned previously the motivation for using LF modulation as the field detection signal includes saving power consumption. In order to make a sensitive field detector or wake-up circuit 64, the received signal must be amplified after detection. If amplified to DC detection levels, it is immune to interference from external sources such as cellular telephones, lightning, power grids, and other sources. The power used to detect high-speed modulation frequencies is greater than that required by other methods. Amplifier power dissipation is nearly linear with frequency; so it is important to reduce the frequency sensed by the amplifier whenever possible. Another wakeup function:

Another wake-up method and structure will now be described with reference to FIG. 19 . Another preferred embodiment of the transponder has a multi-state wakeup, low power state 1 where the threshold detector 62 waits for a received field strength greater than 500 mV/mz. Once the received field strength is greater than the threshold, the first stage threshold detector 62 will cause the second stage wake-up circuit 64 to wake up and monitor the preselected modulation in the received signal. If the second-stage wake-up circuit 64 receives a predetermined modulation signal, the wake-up circuit 64 turns on the digital ASIC 34 through the switch 98 . In this approach, the power consumed is minimal because the first stage threshold detector 62 consumes less power although it is always powered. The wake-up circuit 64 consumes somewhat more power, but it is a necessary low power device. Wake-up circuit 64 is a component that is enabled only during the generally short period of time that the received power is greater than the threshold. Finally, power is only applied to the digital ASIC 34 which consumes more power, if both the threshold condition and the modulation condition are met. The interrogator 12 then transmits an interrogation signal to the remote transponder 14, preferably by an on-off key. Once the interrogation signal has been transmitted, the transmitter 52 transmits a continuous wave RF signal to the transponder 14, which can back reflect and modulate the continuous wave RF signal to generate a reply signal. Interrogator 12 will now be described. Interrogator 12 is located at a data exchange point, such as a bridge, toll booth, or other selected point of interest. The system includes a common reference oscillator 50 which generates at its output 51 a reference carrier for synchronizing the interrogator 12 . Each interrogator 12 has an antenna 18 and a transmitter 52 which transmits a trigger signal 42 of sufficient field strength and/or of a preselected range modulation type to trigger or activate travel within the lane 28a, 28b, 28c associated with the interrogator transponder 14 in the car. Interrogator 12 further includes a receiver 54 that receives the reply signal and separates the reply signal from spurious non-modulated reflections. Interrogator transmitter 52 and receiver 54 operate under the control of control interface circuit 56 . The host controls the transmitter 52 to send the trigger signal 42 after the interrogation signal through the control interface circuit 56 . Wake up block:

Referring to FIG. 19, the multi-stage wake-up circuit 60 is shown in more detail. The first stage circuit 62 and the second stage wake-up circuit 64 are preferably implemented with an analog ASIC 32 . The inventive principles described here offer significant advantages over the prior art in terms of power consumption. This is very important for designing a toll tag or transponder with extra long battery life. Applying the principles of the invention described herein, the transponder 14 is generally placed in a sleep mode or state 1 , drawing very little power from the battery 66 . The energy dissipated in the first stage is only required by the first stage circuit 62 . The second stage 62 generally includes a DC threshold comparator 68 which receives the signal from the antenna 30 via a detector 70 . First detector 70 at node "A" fetches the 300 kbps Manchester II signal modulated onto the 915 MHz continuous wave signal. A low pass filter 72 is provided between the detector 70 and the comparator 68 since the first stage 62 only needs to detect certain levels of RF energy. Low pass filter 72 outputs a DC level signal at node "B" that is related to the average voltage level received at node "A". Since the DC threshold comparator 68 is in a substantially static state, the power consumption is relatively low. When the DC level signal on the node "B" exceeds a certain predetermined voltage threshold, the comparator 68 makes the wake-up circuit 64 detect whether there is 300kbps modulation in the received signal through its output terminal at the node "C", and makes the transmit The transponder enters state 2.

Referring further to FIG. 19, a high pass filter 74 is provided at the output of the detector 70 to filter out spurious low frequency signals from sources such as cellular telephones or others. Filter 74 provides a high pass filtered signal at node "D". Once an RF field of sufficient strength is detected, comparator 68 operates an oscillator or pulse generator 76 and modulation detector 78, which is preferably a pulse counter. Wake-up circuit 64 supplies power to digital ASIC 34 only upon detection of sufficiently strong RF signal energy and modulation at a predetermined frequency to maintain a minimum power consumption. In the first preferred embodiment, the desired modulation frequency is high speed modulation of 248 KHz or higher. In another preferred embodiment, a low frequency signal of about 90 Hz is superimposed on a carrier wave of 915 MHz.

Still referring to FIG. 19, the non-demodulated signal from the detector 70 of the transponder becomes an input signal to the analog voltage comparator 68, referred to as the signal level flag. The threshold level is determined by a 3-bit DAC (not shown). Pulse generator 76, preferably a quartz oscillator, RC oscillator or ceramic resonator, is activated for a predetermined period and loads pulse counter 78 with a reading to cause the voltage at node "B" to rise above the threshold Each pulse of the RF signal level causes the pulse counter 78 to restart while keeping the pulse generator 76 running until the predetermined period has elapsed. The predetermined period of the pulse counter may be selected based on the time between RF interrogation pulses of the interrogator. For example, the interrogator may send RF interrogation pulses every 2 ms, and the short extinction of the signal due to on-off keying of the carrier or other internal information extinction is generally much shorter than 2 ms. Therefore, the predetermined period is slightly shorter than 2 ms and greater than the inter-message blanking time to keep the digital ASIC 34 active during all interrogator messages.

As described above, the signal level flag of comparator 68 activates wake-up circuit 64 . For the first preferred embodiment, pulse counter 78 is preferably a gated 4-bit counting circuit. The gate pulse is set to 62.5μs, which means that the 4-bit counter will overflow if there is a modulation of 248KHz or higher. In order to save power consumption further, the wake-up circuit 64 has its power duty cycle, every 16ms, open 2ms time window (1/8 work cycle), in the time window of 2ms, the detector is opened 62.5 μ s, closes 125 μ s (1/3 work cycle) cycle). This duty cycle (1/8*1/3=1/24 duty cycle) effectively reduces the power consumption to 1/24 of the original value.

Still referring to Figure 19, if no modulation is detected and the RF signal falls below the threshold voltage, after a short period of time, the wake-up block 60 automatically powers down. If no wake-up modulation is detected, but the RF signal remains above the aforementioned threshold, then wake-up circuit 64 preferably continues to draw power. If modulation is detected, the main part of the digital ASIC 34 is activated and the pulse counter 78 is held active with a signal from the main controller block 80 of the digital ASIC 34 (see FIG. 11 ). If the RF signal disappears, the main controller block 80 can keep the pulse generator 76 active until the digital ASIC 34 function is complete. The master controller 80 will not stop the pulse generator 76 until all ongoing functions are complete. The pulse generator 76 is preferably disabled for a short time after the main controller 80 issues a power down. The transponder 14 is now preferably in state 4, in which all circuitry is essentially dormant for a fixed period of time, so the transponder 14 will not be activated again by the same modulating signal. After this fixed period of time, the transponder 14 goes to state 1 again, enabling it to receive interrogation signals from other interrogators 10 .

Desirable auxiliary capabilities include, but are not limited to, EEPROM memory, LCD drive capability with button selection, serial communication, and pressure buzzer drive.

The following table contains nouns used in this patent application, including some alternative and preferred nouns. Other available nouns mean none listed.

surface drawn components common noun better or proper noun optional name 10 Vehicle Identification System Vehicle Identification System AVI system 12 Interrogator Interrogator reader 14 transponder transponder transponder, tag 16 the host the host toll booth computer toll booth computer 18 antenna Directional antenna interrogator antenna 20 electronic module interrogator electronic module twenty two interconnection wire RF interconnection line RF coaxial cable twenty four cable host cable RS232 connection cable RS422 connection cable Host connection cable 26 car car car 28 Lane car driveway 30 antenna transponder antenna transponder antenna transponder antenna 31 integrated antenna Integrated transponder antenna Integrated transponder/transponder antenna 32 Control circuit Analog ASIC Analog/Digital SAIC 34 Control circuit Digital ASIC digital processing section 36 receive buffer block 38 main controller block 40 emitter block 41 launcher 42 wake-up burst trigger signal activation signal 44 field strength pulse field strength pulse 45 lane discrimination cycle First Lane Discrimination Period 46 lane discrimination cycle second lane discrimination cycle 47 lane discrimination cycle Third Lane Discrimination Period 48 memory transponder memory 50 reference oscillator Toll Office Reference Oscillator reference generator 51 output Toll Reference Oscillator Output 52 launcher launcher Luminous Emitter Emitter Module 54 receiver receiver receiver module demodulator 56 Control circuit Interface Circuit computer interface 60 wake up block Multi-state wake-up circuit 62 first stage circuit threshold detector 64 second stage circuit calling circuit modulation detector 66 power supply Battery 70 Detector 72 filter low pass filter 74 filter high pass filter 76 pulse generator 78 counter pulse counter 80 main controller block 82 rectifier 84 capacitor bypass capacitor 86 Resistor bypass resistor 88 capacitor series capacitor 90 Resistor bypass resistor 92 Comparators Gate Comparator 94 terminal counter 96 Latches gated latch 97 OR gate 98 switch switch 100 receive buffer block 102 Manchester Decoder 104 main controller 106 CRC generator 108 lane discrimination circuit 110 Receive Status Controller 112 Shift Register Serial-Parallel Shift Register 114 counter byte counter 116 register holding register Latches 118 SRAM SRAM Latches 120 Comparators address comparator 122 buffer receive buffer 124 controller Lane Discrimination Control device 126 capacitor Coupling and Hold Capacitors 130 Comparator and Decoder 132 switch Sample and hold switch 134 open tip Sample and hold switch 137 Counter short time timer 138 Counter long time timer 140 main controller block 142 Comparators 146 counter transaction counter 148 main memory block 150 memory main memory 152 address selection circuit multiplexer multiplexer 154 address selection circuit multiplexer multiplexer 156 answer selection circuit multiplexer multiplexer 158 register byte register 160 encryptor encryptor Encryptor circuit 162 CRC generator 164 header code generator 166 Modulator 168 controller launch controller 170 Clock circuit 172 external interface circuit External I/F 174 controller auxiliary controller Interface Controller IF Controller 176 bit counter 178 I/O buffer 180 Data output selection Data Output Multiplexer 182 clock selection Clock Selection Multiplexer 184 counter 138-bit counter 186 counter 8-bit counter 190 buzzer block 192 controller buzzer controller 194 Divider tone divider clock divider 196 Divider tone divider clock divider 198 Divider tone divider clock divider 200 Divider tone divider clock divider 202 Divider tone divider clock divider 204 and 206 and 208 or 210 buffer 212 buzzer speaker, piezoelectric transducer 214 clock main oscillator 216 Divider clock divider 218 Divider clock divider 220 Divider clock divider 222 Modulator mixer

Some preferred embodiments have been described in detail above. It should be understood that the scope of the present invention also includes embodiments other than those described but still falling within the scope of the claims.

For example, the display device may be a cathode ray tube or other raster scanning device, a liquid crystal display, or a plasma display. The use of "microcomputer" in this text means that a microcomputer needs to have a memory, while a "microprocessor" does not. The usage here is that these nouns can also be synonymous with and related to equivalents. The terms "controller", "processing circuit" and "control circuit" include ASIC (Application Specific Integrated Circuit), PAL (Programmable Array Logic), PLA (Programmable Logic Array), decoder, memory, non-software based processor or other Circuits, or digital computers including microprocessors and microcomputers of any structure, or combinations of these elements and components. Storage devices include SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), pseudo-static RAM, latches, EEPROM (Electrically Erasable Programmable Read-Only Memory), EPROM (Erasable Programmable Read-Only Memory) ), registers, or any other known storage device. The words contained herein are not to be construed as exhaustive of the scope of the invention.

Frequency shift keying (FSK) modulation can be seen as possible data modulation, as well as pulse-pause modulation, amplitude shift keying (ASK), quadrature AM (QAM) modulation, quadrature phase shift keying ( QPSK), or any other modulation. Different types of multiplexing such as time or frequency modulation can avoid signal cross interference. Modulation can be achieved by back reflection modulation, carrier active modulation or other methods. Discrete components or fully integrated circuits made of silicon (Si), gallium arsenide (GaAs), or other electronic material families, or based on optical or other technologies, can be used to implement the circuits described herein. It should be understood that the various embodiments of the invention may be implemented or implemented in hardware, software, or microcode firmware.

It is contemplated that the invention may be implemented as discrete components or as fully integrated circuits in forms and embodiments of silicon, gallium arsenide or other material families or based on photonics or other technologies. It should be understood that various embodiments of the invention may be realized or implemented in hardware, software, or microcode firmware.

While this invention has been described with reference to the illustrated embodiments, these descriptions are not intended to be limiting. Various modifications and combinations of the illustrated embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art having reference to the foregoing description. It is therefore intended that such variations or embodiments be covered by the appended claims.

Claims (7)

1. A transponder for radio communication with an interrogator, characterized in that the transponder comprises: a) an antenna for receiving an RF interrogation signal from the interrogator; b) a threshold detector in electrical communication with the antenna; the threshold detector is adapted to measure the power level of the RF interrogation signal, compare the power level to a threshold, and provide a signal indicative of the power Whether the level is greater than the threshold signal of the threshold; c) a modulation detector in electrical communication with the antenna, the modulation detector detecting modulation in the RF interrogation signal and providing a modulation presence signal, and d) control circuitry, upon receipt of said threshold signal and said modulation presence signal, said control circuitry receiving said RF interrogation signal from said antenna and responding with data modulated on said RF interrogation signal. 2. The transponder of claim 1, wherein said modulation detector receives said threshold signal and is activated by said signal. 3. The transponder of claim 1, wherein said threshold detector receives and is activated by said modulation presence signal. 4. The transponder of claim 1, further comprising, a carrier detector in electrical communication with said antenna and receiving an RF interrogation signal from said antenna, said The carrier detector further extracts a carrier from the RF interrogation signal and sends the carrier to the control circuit, the threshold detector and the modulation detector. 5. The transponder of claim 4, wherein said carrier detector further transmits said RF interrogation signal to said control circuit in a modulated form of said carrier. 6. The transponder of claim 1, wherein said transponder receives and demodulates said interrogator's electrical communication signal at a first modulation frequency, said modulation detector detects A second modulation frequency on the RF interrogator, the modulation detector enabling other transponder circuits to operate only when it detects the presence of the second modulation frequency, reducing activation by e.g. spurious electromagnetic interference in the absence of an RF interrogation signal Possibilities for other transponder circuits as described. 7. The transponder of claim 6, wherein said first frequency is a communication signal, said second frequency is lower than said first frequency, said second frequency serves as said electrical communication signal. The gating signal effect of the signal, the gating signal enables the communication signal to pass the RF interrogation signal during the first half period of the gating signal, and the gating signal The RF interrogation signal is held at a known value during the second half cycle of .

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