CN110349933A - A kind of encapsulating structure and preparation method of wafer bonding stacked chips - Google Patents

Abstract

The invention discloses a packaging structure and a preparation method of a wafer bonding stacked chip. The packaging structure includes a chip bonding body, including a plurality of single wafer level chips arranged in a stack, and between the single wafer level chips Bonding through the bonding layer, that is, after wafer bonding, a stacked chip is formed; conductive through holes are used to realize the connection of the lead-out terminals of the stacked chip pad function. The packaging structure provided by the embodiment of the present invention is formed by wafer bonding. Wall signal interconnection, small package size. The preparation method provided by the embodiment of the present invention does not require a complicated TSV process, avoids the problem of internal stress and damage to the chip caused by directly or indirectly making through holes on the chip, and has a simple manufacturing process and high productivity.

Description

A packaging structure and preparation method of a wafer bonded stacked chip

technical field

The invention relates to the technical field of semiconductor packaging, in particular to a packaging structure and a preparation method of a wafer-bonded stacked chip.

Background technique

In recent years, in 3D chip packaging or wafer level packaging, the emergence of the Flip-Chip (FC) process can reduce the volume of the chip package, in order to increase the input/output (Input/Output, I/O) ) interface, generally on the basis of the FC process, through silicon via (TSV) operation is performed on the chip, but the through silicon via operation on the chip or wafer will cause internal stress to the wafer and cause damage to the wafer .

SUMMARY OF THE INVENTION

Therefore, the present invention provides a wafer bonding stack chip packaging structure and preparation method, which overcomes the defects in the prior art that internal stress and damage will be generated by operating TSV on the chip during 3D chip packaging or wafer level packaging. .

In a first aspect, the present invention provides a packaging structure for wafer bonding stacked chips, including: a chip bonding body, including a plurality of single wafer-level chips arranged in a stack, and the single wafer-level chips are connected by bonds. The bonding layer is bonded; the conductive through holes are connected with the functional lead-out terminals of each single wafer-level chip.

In one embodiment, the packaging structure of the wafer-bonded stacked chip further includes: a molding material covering the chip bonding body.

In an embodiment, the packaging structure of the wafer-bonded stacked chip further includes: a redistribution layer, formed on one side of the chip-bonded body, and electrically connected to the chip-bonded body through conductive vias .

In an embodiment, the packaging structure of the wafer-bonded stacked chip further includes: a plurality of bumps disposed on the plurality of pads of the redistribution layer.

In one embodiment, the conductive through holes are filled with conductive glue or conductive metal.

In a second aspect, an embodiment of the present invention provides a method for preparing a wafer-level chip package structure, including the following steps: bonding a predetermined number of wafer-level chips through a bonding layer to form a chip bond body; bonding the chip The combination is cut to form multiple single modules; the multiple single modules are packaged to form a reconstituted wafer; conductive through holes are formed at the corresponding positions of the wafer-level chip function lead-out terminals located on the bonding layer.

In an embodiment, before the step of bonding a preset number of wafer-level chips through the bonding layer, the step further includes: thinning the opposite surface of the bonding surface of the wafer-level chips.

In an embodiment, after the step of forming conductive vias at corresponding positions of the wafer-level chip function lead-out terminals located in the bonding layer, the method further includes: filling the vias with a conductive medium, and performing electroplating on the conductive medium. connected to form a redistribution layer.

In one embodiment, after the steps of filling the conductive medium in the through holes and performing electroplating and interconnecting the conductive medium to form the redistribution layer, the method further includes: preparing bumps on the redistribution layer.

In one embodiment, after the step of preparing bumps on the redistribution layer, the method further includes: cutting the reconstituted wafer to form a single wafer-level chip structure.

1. The packaging structure of the wafer bonding stacked chip provided by the present invention includes a chip bonding body, which includes a plurality of single wafer level chips arranged in a stack, and the single wafer level chips are bonded through a bonding layer. The conductive through holes are connected with the function lead-out terminals of each single chip. The package structure provided by the embodiment of the present invention is formed by wafer bonding. The stacked chips are interconnected through sidewall signals, and the package volume is small.

2. The present invention provides a method for preparing a packaging structure of wafer-bonded stacked chips, wherein a predetermined number of wafer-level chips are bonded through a bonding layer to form a chip bonding body; the chip bonding body is cut to form a plurality of Single module; multiple single modules are packaged to form a reconstituted wafer; conductive vias are formed at the corresponding positions of the wafer-level chip function lead-out terminals located in the bonding layer, and the preparation method provided by the embodiment of the present invention does not require a TSV process , to avoid the problem of internal stress and damage of the chip caused by directly or indirectly making through holes on the chip, the manufacturing process is simple, and the production capacity is high.

Description of drawings

In order to illustrate the specific embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the specific embodiments or the prior art. Obviously, the accompanying drawings in the following description The drawings are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

FIG. 1 is a schematic diagram of a specific example of a packaging structure of a wafer-bonded stacked chip according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another specific example of a packaging structure of a wafer-bonded stacked chip provided by an embodiment of the present invention;

3 is a schematic diagram of another specific example of a packaging structure of a wafer-bonded stacked chip provided by an embodiment of the present invention;

FIG. 4 is a schematic diagram of another specific example of a packaging structure of a wafer-bonded stacked chip according to an embodiment of the present invention;

FIG. 5 is a flowchart of a specific example of a method for preparing a package structure of a wafer-bonded stacked chip according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of chip bonding before thinning according to an embodiment of the present invention;

7 is a schematic diagram of a chip after thinning processing provided by an embodiment of the present invention;

8 is a schematic diagram of a die bond body provided by an embodiment of the present invention;

FIG. 9 is a schematic diagram of a single module provided by an embodiment of the present invention;

10 is a schematic diagram of a reconstituted wafer provided by an embodiment of the present invention;

11 is a schematic diagram of forming conductive vias according to an embodiment of the present invention;

12 is a flowchart of another specific example of a method for preparing a package structure of a wafer-bonded stacked chip according to an embodiment of the present invention;

13 is a schematic diagram of forming a redistribution layer according to an embodiment of the present invention;

FIG. 14 is a schematic diagram of bump preparation on a redistribution layer according to an embodiment of the present invention.

Detailed ways

The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "installed", "connected" and "connected" should be understood in a broad sense, unless otherwise expressly specified and limited, for example, it may be a fixed connection or a detachable connection connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal connection of two components, which can be a wireless connection or a wired connection connect. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in specific situations.

In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

Example 1

The present embodiment provides a packaging structure for wafer bonding stacked chips, as shown in FIG. 1 , including: a chip bonding body 1 including a plurality of single wafer level chips 11 arranged in a stack, the single wafer level The chips are bonded through the bonding layer 12 ; the conductive vias 2 are connected to the function lead-out terminals 13 of each single wafer-level chip 11 . In the embodiment of the present invention, the chip is a memory chip, the single wafer-level chips are bonded together, and the conductive through holes 2 are connected to the function lead-out terminals 13 of each single wafer-level chip 11, which can be expanded. The memory capacity of the chip.

The packaging structure of the wafer-bonded stacked chips provided by the present invention includes a chip bonding body, which includes a plurality of single wafer-level chips arranged in a stack, and the single wafer-level chips are bonded through a bonding layer, that is, After wafer bonding, stacked chips are formed; conductive vias are connected to the functional lead-out terminals of each single chip, and the package structure provided by the embodiment of the present invention performs signal interconnection through the sidewall of the chip bonding body, and the package volume is small.

In an embodiment, the packaging structure of the wafer-bonded stacked chip, as shown in FIG. 2 , further includes: a molding material 3 , covering the chip bonding body 1 and the conductive via 2 . The die-bonded body 1 and the conductive vias 2 are encapsulated by the molding material 3 . In this embodiment, the molding material 3 is an epoxy resin molding compound, and the epoxy resin molding compound is made of epoxy resin as the matrix resin, high-performance phenolic resin as the curing agent, adding silicon micropowder as filler, and adding various Powder molding compound made of additives. The plastic packaging process is to extrude the EMC into the mold cavity by transfer molding and embed the semiconductor chips in it, and at the same time cross-link and solidify to form a semiconductor device with a certain structural appearance.

In one embodiment, the packaging structure of the wafer-bonded stacked chip, as shown in FIG. 3 , further includes: a redistribution layer 4 , which is formed on one side of the chip-bonded body 1 , and is connected to the chip-bonded body 1 through the conductive through holes 2 . electrical connection. In the embodiment of the present invention, each single wafer-level chip is electroplated and interconnected through the rewiring layer 4, and the function of the chip is led out.

In one embodiment, the packaging structure of the wafer-bonded stacked chip, as shown in FIG. 4 , further includes: a plurality of bumps 5 disposed on a plurality of pads of the redistribution layer 3 . The plurality of bumps 5 are formed to facilitate electrical connection with other devices. In this embodiment, the bumps are all tin balls, but not limited to this. In other embodiments, the bumps can also be made of other materials, such as copper balls.

In one embodiment, an under-bump metallization layer is used on the pad surface of the redistribution layer 3 to process the under-bump metallization layer for short as UBM (Under Ball Metal). Below the UBM are copper wires or copper pads. The purpose of UBM is to prevent the metal copper of the copper wire or the copper pad from forming an alloy with metal tin during the reflow of the solder balls, resulting in the failure of the solder balls to be firmly connected to the chip and the problem of reliability failure.

In the embodiment of the present invention, the bonding layer is an organic adhesive, such as organic adhesive; the conductive through hole is filled with conductive adhesive or conductive metal, wherein the conductive filler of the conductive adhesive can be silver, copper, aluminum, zinc, iron, nickel The powder and graphite and some conductive compounds, the conductive metal is copper, aluminum, zinc, iron, nickel or alloys, the above is only an example, not limited to this.

Example 2

An embodiment of the present invention provides a method for preparing a packaging structure of a wafer-bonded stacked chip, as shown in FIG. 5 , including the following steps:

Step S10 : thinning the opposite surface of the wafer-level chip bonding surface. After the thinning process, it is beneficial to reduce the size of the package. FIG. 6 is a schematic diagram before thinning, and FIG. 7 is a schematic diagram after the thinning process.

Step S11 : bonding a preset number of wafer-level chips through a bonding layer to form a chip bonding body. In the embodiment of the present invention, the wafer-level chip is a memory chip, and the bonding layer is an organic adhesive, such as organic glue, and the formed chip bonding body is shown in FIG. 8 .

Step S12 : cutting the die bonding body to form a plurality of single modules. The single module formed by the embodiment of the present invention is shown in FIG. 9 .

Step S13 : encapsulating the plurality of single modules to form a reconstituted wafer. The die bond body formed in the embodiment of the present invention is shown in FIG. 10 .

Step S14 : forming conductive vias at corresponding positions of the wafer-level chip function lead-out terminals located in the bonding layer. In the embodiment of the present invention, the conductive via is formed by laser ablation or etching, as shown in FIG. 11 .

In one embodiment, after step S14 is performed, as shown in FIG. 12 , it further includes:

Step S15: Filling the conductive medium in the through hole, and performing electroplating and interconnecting the conductive medium to form a redistribution layer. In the embodiment of the present invention, as shown in FIG. 13 , each single wafer-level chip is interconnected by electroplating through the rewiring layer, and the function of the chip is led out.

Step S16: Bump preparation is performed on the redistribution layer. In the embodiment of the present invention, as shown in FIG. 14 , bumps are fabricated as solder balls by printing solder paste or directly placing solder balls to facilitate electrical connection with other devices.

Step S17 : cutting the reconstituted wafer to form a single wafer-level chip structure. In the embodiment of the present invention, the reconstituted wafer is cut to form a single-wafer-level chip structure as shown in FIG. 4 . The present invention adopts the packaging form of wafer level, and has higher production efficiency and greater cost advantage.

The present invention provides a method for preparing a packaging structure of wafer-bonded stacked chips, wherein a predetermined number of wafer-level chips are bonded through a bonding layer to form a chip bonding body; the chip bonding body is cut to form a plurality of single chips module; encapsulate a plurality of single modules to form a reconstituted wafer; form conductive vias at the corresponding positions of the wafer-level chip function lead-out terminals located in the bonding layer, the preparation method provided by the embodiment of the present invention does not require a TSV process, avoiding The problem of internal stress and damage caused by directly or indirectly making through holes on the chip is eliminated, the manufacturing process is simple, and the productivity is high.

Obviously, the above-mentioned embodiments are only examples for clear description, and are not intended to limit the implementation manner. For those of ordinary skill in the art, changes or modifications in other different forms can also be made on the basis of the above description. There is no need and cannot be exhaustive of all implementations here. And the obvious changes or changes derived from this are still within the protection scope of the present invention.

Claims (11)

1. a packaging structure for wafer bonding stacked chips, characterized in that, comprising: The chip bonding body includes a plurality of single wafer-level chips arranged in a stack, and the single wafer-level chips are bonded through a bonding layer; The conductive through holes are connected with the function lead-out terminals of each single wafer-level chip. 2 . The packaging structure for stacked chips by wafer bonding according to claim 1 , further comprising: a molding material for covering the chip bonding body. 3 . 3. The packaging structure of wafer bonding stacked chips according to claim 1 or 2, further comprising: a redistribution layer, formed on one side of the chip bonding body, and connected to the Electrical connection of the die bond. 4 . The packaging structure for stacked chips by wafer bonding according to claim 3 , further comprising: a plurality of bumps disposed on a plurality of pads of the redistribution layer. 5 . 5 . The packaging structure of wafer-bonded stacked chips according to claim 1 , wherein the bonding layer is an organic adhesive. 6 . 6 . The packaging structure of wafer-bonded stacked chips according to claim 1 , wherein the conductive through holes are filled with conductive glue or conductive metal. 7 . 7. A method for preparing a packaging structure for wafer bonding stacked chips, characterized in that it comprises the following steps: Bonding a preset number of wafer-level chips through a bonding layer to form a chip bonding body; cutting the chip bonding body to form a plurality of single modules; packaging the plurality of single modules to form a reconstituted wafer; Conductive vias are formed at corresponding positions of the functional lead-out terminals of the wafer-level chip on the bonding layer. 8 . The method for preparing the packaging structure of wafer-bonded stacked chips according to claim 7 , wherein, before the step of bonding a preset number of wafer-level chips through a bonding layer, the method further comprises: 9 . The opposite side of the wafer-level chip bonding surface is thinned. 9 . The method for preparing the packaging structure of wafer-bonded stacked chips according to claim 7 , wherein the step of forming conductive vias at corresponding positions of the wafer-level chip function lead-out terminals located in the bonding layer. 10 . After that, also include: A conductive medium is filled in the through holes, and the conductive medium is plated and interconnected to form a redistribution layer. 10 . The method for preparing the packaging structure of wafer-bonded stacked chips according to claim 9 , wherein the conductive medium is filled in the through holes, and the conductive medium is electroplated and interconnected to form a redistribution layer. 11 . After the steps, also include: Bump preparation is performed on the redistribution layer. 11. The method for preparing a packaging structure of a wafer-bonded stacked chip according to claim 10, wherein after the step of performing bump preparation on the redistribution layer, the method further comprises: The reconstituted wafer is diced to form a single wafer-level chip structure.