CN110277490B - STT-MRAM reference cell, preparation method thereof and chip comprising reference cell - Google Patents

Abstract

A STT-MRAM reference cell, a method for manufacturing the same and a chip comprising the reference cell are provided, wherein the reference cell comprises two parallel branches, one branch comprises two tunnel junctions connected in series, the resistance states of the two tunnel junctions connected in series are different, and the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction. Through interconnection of the free layer and the free layer, the method can be realized through unidirectional current only during initialization, and is convenient and simple; in addition, when data are read, as the two tunnel junctions connected in series are connected through the free layer, when the direction of the read current is the same as that of the initialization current, the situation that one tunnel junction is turned over is avoided anyway, so that the method has high reliability, the problem that one tunnel junction is easy to turn over when the reference layer and the free layer are correspondingly read in the prior art is avoided, and in addition, the corresponding preparation process is relatively simple, and a through hole in the traditional structure is omitted.

Description

STT-MRAM reference unit, preparation method thereof, and chip comprising the reference unit

technical field

The disclosure belongs to the technical field of memory devices, and relates to an STT-MRAM reference unit, a preparation method thereof, and a chip containing the reference unit.

Background technique

As a new type of non-volatile memory, spin-transfer torque-magnetic random access memory (STT-MRAM) has both the high-speed read and write capabilities of static random access memory (SRAM) and the high integration of dynamic random access memory (DRAM). Unlimited erasing and writing, no need to refresh, but also has the advantages of long life, low power consumption, radiation resistance, and compatibility with CMOS process back-end processes, so it is considered by the industry to be ideal for building the next generation of non-volatile cache and main memory device.

The core structure of the STT-MRAM memory cell is a tunnel junction composed of magnetic layer/insulating layer/magnetic layer. When the magnetization directions of the two magnetic layers are parallel, the tunnel junction exhibits low resistance, which is recorded as "0"; otherwise, it exhibits high resistance, which is recorded as "1". By reading the resistance of the tunnel junction and judging the stored data, the readout of the data is realized.

In the actual chip, it is impossible to directly measure the resistance state of the tunnel junction. Instead, a reference unit with a fixed resistance value is designed in the circuit, and a constant current or constant voltage mode is used to compare the output voltage or current of the storage unit and the reference unit to judge the data. store state. Therefore, the design of the reference cell is also one of the key factors affecting the reliability of the chip. However, the existing reference cells have the problems of complex initialization and low readout reliability.

Contents of the invention

(1) Technical problems to be solved

The present disclosure provides an STT-MRAM reference cell, its preparation method and a chip containing the reference cell, so as to at least partly solve the technical problems raised above.

(2) Technical solution

According to one aspect of the present disclosure, an STT-MRAM reference cell is provided, the reference cell includes two parallel branches, one of which contains two series-connected tunnel junctions, and the two series-connected tunnel junctions have different resistance states , the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction.

In some embodiments of the present disclosure, the structures of the two parallel branches are the same.

In some embodiments of the present disclosure, the initialization method of the branch of the two series-connected tunnel junctions is as follows: a unidirectional current is passed through to obtain a high resistance state and a low resistance state correspondingly.

In some embodiments of the present disclosure, the initialization method of the two parallel branches is as follows: a unidirectional current is passed through the main circuit, correspondingly, a high resistance state and a low resistance state are obtained on each branch.

In some embodiments of the present disclosure, when the input direction of the unidirectional current changes, the resistance states of the two series-connected tunnel junctions are exchanged.

In some embodiments of the present disclosure, the equivalent resistance of the reference unit is 1/2 of the sum of the resistance values of the low resistance state and the high resistance state.

In some embodiments of the present disclosure, during the read operation of the reference cell, the direction of the read operation current is the same as that of the current passed during initialization.

According to another aspect of the present disclosure, a method for preparing any of the above STT-MRAM reference cells is provided, including: preparing two tunnel junctions in series, wherein the two tunnel junctions in series have different resistance states, and one tunnel junction The free layer of the junction is connected in series with the free layer of another tunnel junction.

In some embodiments of the present disclosure, the method for preparing two tunnel junctions in series is: depositing the bottom electrode layer and the thin film material of the tunnel junction, and the tunnel junction is sequentially: a reference layer, an insulating layer and a free layer; Patterning the tunnel junction and the bottom electrode layer by photolithography, so that the tunnel junction and the bottom electrode layer below it form two spaced apart parts; filling a dielectric layer on the structure with the two spaced apart parts; Holes are opened on the dielectric layer, respectively etched to the surface of the bottom electrode layer and the surface of the free layer of the tunnel junction, corresponding to the bottom electrode through hole and the top electrode through hole; electrode material is deposited; and the electrode is formed by using photolithography technology Material patterning, corresponding to the electrode material between the two spaced top electrode through holes is the top electrode, the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction by using the top electrode, corresponding to the through hole of the bottom electrode The electrode material above the hole is the bottom electrode corresponding to the bottom electrode layer for the lead.

According to yet another aspect of the present disclosure, a chip is provided, including any STT-MRAM reference unit mentioned in the present disclosure.

(3) Beneficial effects

It can be seen from the above technical solutions that the STT-MRAM reference unit provided by the present disclosure, its preparation method and the chip containing the reference unit have the following beneficial effects:

1. A branch contains two tunnel junctions in series. By setting the two tunnel junctions in series to be antiparallel to each other, the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction. Through the free layer and The interconnection of the free layer can be realized only by unidirectional current during initialization, which is convenient and simple, and does not require the relatively complicated initialization process corresponding to the connection form of the reference layer and the free layer in the prior art; in addition, when the data is read out, due to Two series-connected tunnel junctions are connected in series through the free layer. When the direction of the readout current is the same as that of the initialization current, there will be no flipping of a certain tunnel junction in any case, which has high reliability and avoids the existing In the technology, it is easy to flip one of the tunnel junctions during readout corresponding to the connection form of the reference layer and the free layer.

2. Preferably, the two parallel branches are set to the same structure, and the reference unit adopts a structure in which R _p and R _ap are connected in series and then connected in parallel, and the constant current mode is used to read out and compare the output of the reference unit and the storage unit Voltage, for data judgment, the same current flows into the storage unit and the reference unit through the current mirror, so that the equivalent resistance of the reference unit is 0.5×(R _p +R _ap ), that is, the equivalent resistance of the reference unit is low resistance and The resistance value of the high-resistance state is 1/2 of the sum, which maximizes the readout window. At the same time, the structure of the reference cell is the same as that of the memory cell, so it has the same temperature drift characteristics, which can effectively suppress the influence of temperature drift.

3. The resistance states of the two series-connected tunnel junctions are different, and the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction. The corresponding preparation process is relatively simple, and the via hole in the traditional structure is omitted.

Description of drawings

FIG. 1 is a schematic diagram of a circuit structure of an STT-MRAM reference cell according to an embodiment of the present disclosure.

FIG. 2 is a schematic diagram showing a connection relationship between two tunnel junctions on one branch of an STT-MRAM reference cell according to an embodiment of the present disclosure.

FIG. 3 is a schematic diagram of an initialization mode and a readout mode of the STT-MRAM reference cell branch corresponding to FIG. 2 .

FIG. 4 is a schematic diagram of the overall initialization mode and readout mode of the STT-MRAM reference cell corresponding to FIG. 3 .

FIG. 5 is a schematic diagram of a circuit structure of an STT-MRAM reference cell in the prior art.

FIG. 6 is a schematic diagram of the connection relationship between two tunnel junctions on one branch of the STT-MRAM reference cell corresponding to FIG. 5 .

FIG. 7 is a schematic diagram of an initialization method of an STT-MRAM reference cell in the prior art corresponding to FIG. 6 .

FIG. 8 is a schematic diagram of a readout method of an STT-MRAM reference cell in the prior art corresponding to FIG. 6 .

FIG. 9 is a flow chart of a method for preparing an STT-MRAM reference cell according to an embodiment of the present disclosure.

10a-17c are schematic structural diagrams of various stages corresponding to the preparation method of the STT-MRAM reference cell as shown in FIG. 9 .

【Symbol Description】

1 - first tunnel junction;

11-the first reference layer; 12-the first insulating layer;

13 - first free layer;

2 - second tunnel junction;

21 - second free layer; 22 - second insulating layer;

23 - Second reference layer.

Detailed ways

FIG. 4 is a schematic diagram of a circuit structure of an STT-MRAM reference cell in the prior art. FIG. 5 is a schematic diagram of the connection relationship between two tunnel junctions on one branch of the STT-MRAM reference cell corresponding to FIG. 4 . FIG. 7 is a schematic diagram of an initialization method of an STT-MRAM reference cell in the prior art corresponding to FIG. 6 . FIG. 8 is a schematic diagram of a readout method of an STT-MRAM reference cell in the prior art corresponding to FIG. 6 . Referring to FIG. 4, in the prior art, the reference unit adopts a structure in which two tunnel junctions R _H (in the circuit structure, the tunnel junction corresponding resistance value is used to represent the tunnel junction) and R _L are connected in series and then connected in parallel, Use the constant current mode to read, compare the output voltage of the reference unit and the storage unit, and judge the data. Referring to Figure 5, the series connection of two tunnel junctions is a series connection between the reference layer and the free layer. This structure is more complicated during initialization, and it is easier to flip one of the tunnel junctions on the branch road during readout. For example, when the read current is passed from top to bottom, R _H is prone to flipping; otherwise, R _L is prone to flipping, which leads to poor reliability of the reference unit.

In detail, as shown in Figure 7, when the traditional structure is initialized, the reference unit circuit needs two Vcc and two GND, and the corresponding circuit structure is relatively complicated, and the current flows from the reference layer (PL) to the tunnel of the free layer (FL). Junctions are written as high-impedance, and vice versa as low-impedance. In addition, as shown in Figure 8, when the traditional structure is read, it is necessary to read the series resistance, so one end of the write operation of the traditional structure needs to be converted to Vcc or GND, and the circuit complexity increases; in addition, regardless of the direction of the read current Whether it is bottom-up or top-down, one of the tunnel junctions may be rewritten into the opposite resistance state, resulting in lower reliability.

Based on the above existing technical problems and the structural analysis of existing reference units, this application solves the above technical problems by proposing a new reference unit structure. The initialization method corresponding to the reference unit structure of this application is simple and easy to read. The corresponding reliability is high.

In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the present disclosure will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

In a first exemplary embodiment of the present disclosure, an STT-MRAM reference cell is provided.

FIG. 1 is a schematic diagram of a circuit structure of an STT-MRAM reference cell according to an embodiment of the present disclosure. FIG. 2 is a schematic diagram showing a connection relationship between two tunnel junctions on one branch of an STT-MRAM reference cell according to an embodiment of the present disclosure.

Referring to Figures 1 and 2, the STT-MRAM reference cell of the present disclosure includes two parallel branches, one of which contains two series-connected tunnel junctions, and the two series-connected tunnel junctions have different resistance states, one The free layer of the tunnel junction is connected in series with the free layer of another tunnel junction.

The reference unit is a resistor with a certain value. Preferably, the two parallel branches have the same structure, as shown in FIG. 1 .

FIG. 3 is a schematic diagram of an initialization mode and a readout mode of the STT-MRAM reference cell branch corresponding to FIG. 2 .

In this embodiment, as shown in FIG. 3 , the two tunnel junctions connected in series are respectively a first tunnel junction 1 and a second tunnel junction 2, and the first tunnel junction 1 includes in sequence from bottom to top: a first free layer 13 , the first insulating layer 12 and the first reference layer 11; the second tunnel junction 2 sequentially includes from bottom to top: a second reference layer 23, a second insulating layer 22 and a second free layer 21; wherein the first The first free layer 13 of the tunnel junction 1 and the second free layer 21 of the second tunnel junction 2 are connected in series.

In some embodiments of the present disclosure, for example, when one branch is a tunnel junction structure in series, the structure of the other branch is not required (it may be the same as the structure including two tunnel junctions in series, or it may be different) , the initialization method of the branch of the two tunnel junctions in series is: a unidirectional current is passed through, and a high resistance state and a low resistance state are correspondingly obtained.

In some embodiments of the present disclosure, for example, when the two parallel branches have the same structure, the initialization method of the two parallel branches is as follows: a unidirectional current is passed through the main road, and a corresponding current is obtained on each branch. high-impedance state and a low-impedance state. In this case, the equivalent resistance of the reference unit is 1/2 of the sum of the resistance values of the low resistance state and the high resistance state.

In some embodiments of the present disclosure, when the input direction of the unidirectional current changes, the resistance states of the two series-connected tunnel junctions are exchanged.

In this embodiment, as shown in FIG. 3, when the direction of the initializing current I passed in is bottom-up, the electrons in the first tunnel junction 1 flow from the first reference layer 11 to the first free layer 13, which is written as Low-resistance state; at the same time, the electrons of the second tunnel junction 2 flow from the second free layer 21 to the second reference layer 23, which is written as a high-resistance state; when the initialization current direction is from top to bottom, the corresponding situation is just the opposite, and a resistance state occurs Exchange, that is, the electrons of the first tunnel junction 1 flow from the first free layer 13 to the first reference layer 11, which is written as a high resistance state; at the same time, the electrons of the second tunnel junction 2 flow from the second reference layer 23 to the second free layer 21 , is written as a low-impedance state.

It can be seen from the above that by setting the resistance states of the two series-connected tunnel junctions to be different, the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction. Through the interconnection between the free layer and the free layer, only one-way The electric current can be realized, which is convenient and simple, and does not require a relatively complicated initialization process corresponding to the connection form of the reference layer and the free layer in the prior art.

In the read operation of the reference cell, the read operation current I _read is in the same direction as the current (initialization current) I passed during initialization to realize data reading.

Since the resistance states of the two tunnel junctions in series are different, there will be no flipping of a certain tunnel junction in any case, which has high reliability and avoids the readout corresponding to the connection form of the reference layer and the free layer in the prior art It is easier to flip one of the tunnel junctions.

In the second exemplary embodiment of the present disclosure, a method for preparing a STT-MRAM reference cell is provided, including: preparing two tunnel junctions in series, wherein the two tunnel junctions in series have different resistance states, and one tunnel junction The free layer of the junction is connected in series with the free layer of another tunnel junction.

In this embodiment, the method for preparing two tunnel junctions in series includes:

Step S21: Depositing the thin film material of the bottom electrode layer and the tunnel junction, the tunnel junction is as follows from bottom to top: a reference layer, an insulating layer and a free layer;

Fig. 10c is a top view, and Fig. 10a and Fig. 10b are respectively a sectional view taken along line A-A shown in Fig. 10c and a sectional view taken along line B-B shown in Fig. 10c. Fig. 10a-Fig. 10c have shown the structure after depositing the thin film material of bottom electrode layer and tunnel junction on a substrate, and tunnel junction is successively from bottom to top: reference layer (PL), insulating layer (I) and free layer ( FL).

Step S22: patterning the tunnel junction and the bottom electrode layer by photolithography, so that the tunnel junction and the bottom electrode layer below it form two spaced apart parts;

In this embodiment, the tunnel junction is patterned first, as shown in Fig. 11a-Fig. 11c, wherein Fig. 11c is a top view after patterning the tunnel junction, and Fig. 11a and Fig. 11b are sections along the line A-A shown in Fig. 10c respectively. 11a-11c, it can be seen that the patterned tunnel junction forms two spaced apart tunnel junction parts. Then deposit a tunnel junction in-situ protective layer on the patterned tunnel junction, as shown in Figures 12a-12c, wherein Figure 12c is a top view after depositing a protective layer on the patterned tunnel junction, the tunnel junction is covered, Figure 12c is indicated by a dotted line. Figure 12a and Figure 12b are a cross-sectional view taken along line A-A shown in Figure 12c and a cross-sectional view taken along line B-B respectively. In this embodiment, the material of the tunnel junction in-situ protective layer is SiN. Then use the protective layer as a hard mask to pattern the bottom electrode layer, etch the bottom electrode layer to the substrate surface to form two spaced bottom electrode parts, as shown in Figure 13a-Figure 13c, where Figure 13c is the bottom electrode layer The top view of the electrode layer after patterning, Figure 13a and Figure 13b are the cross-sectional view taken along the line A-A shown in Figure 13c and the cross-sectional view taken along the line B-B respectively, in this embodiment, the corresponding bottom electrode length × width ( The top view) is greater than the length×width (top view) of the tunnel junction, which is convenient for the subsequent wiring of the bottom electrode layer to the upper surface of the device.

Step S23: filling a dielectric layer on the structure having two parts spaced apart;

In this embodiment, the dielectric layer is SiO ₂ , and the structure after filling the dielectric layer is shown in Fig. 14a-Fig. Dotted lines indicate that Fig. 14a and Fig. 14b are respectively a cross-sectional view along line AA shown in Fig. 14c and a cross-sectional view along line BB.

Step S24: opening holes in the dielectric layer, respectively etching the dielectric layer to the surface of the bottom electrode layer and the surface of the free layer of the tunnel junction, correspondingly obtaining bottom electrode through holes and top electrode through holes;

In this embodiment, a hole is opened on the dielectric layer, and the dielectric layer is etched to the surface of the bottom electrode layer to obtain a corresponding bottom electrode through hole, as shown in the bottom electrode through hole on the left side in FIG. 15b, and the dielectric layer is etched to the tunnel junction The surface of the free layer corresponds to the top electrode via hole, see the top electrode via hole in the two tunnel junctions shown in Figure 15a and the top electrode via hole on the right side shown in Figure 15b, Figure 15a and Figure 15b are respectively in Figure 14a and Figure 14b illustrate the corresponding structural schematic diagrams after holes are further opened in the dielectric layer.

Step S25: Depositing electrode materials;

In this embodiment, the structure after depositing the electrode material is shown in Fig. 16a and Fig. 16b.

Step S26: Use photolithography to pattern the electrode material, and the electrode material corresponding to the top electrode between the two spaced top electrode through holes is the top electrode, and use the top electrode to realize the free layer of one tunnel junction and the free layer of the other tunnel junction. The layers are connected in series, and the electrode material corresponding to the through hole of the bottom electrode is the bottom electrode for the lead corresponding to the bottom electrode layer; see Figure 17a-Figure 17c, where Figure 17c is a top view after patterning the electrode material, Fig. 17a and Fig. 17b are respectively a sectional view taken along line A-A shown in Fig. 17c and a sectional view taken along line B-B.

So far, two tunnel junction structures in series have been prepared, wherein the free layer (FL) of one tunnel junction is connected in series with the free layer (FL) of the other tunnel junction. The corresponding preparation process is relatively simple, and the through holes in the traditional structure are omitted.

In a third exemplary embodiment of the present disclosure, there is also provided a chip including the STT-MRAM reference cell of the present disclosure.

To sum up, the present disclosure provides a STT-MRAM reference cell and its preparation method and a chip containing the reference cell. One branch of the reference cell contains two tunnel junctions connected in series. By setting the two tunnel junctions connected in series Tunnel junctions have different resistance states. The free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction. Through the interconnection between the free layer and the free layer, it can be realized only by unidirectional current during initialization, which is convenient and simple, and does not require an actual There is a relatively complicated initialization process corresponding to the connection form of the reference layer and the free layer in the technology; in addition, during data readout, since two tunnel junctions connected in series are interconnected through the free layer, when the direction of the readout current is the same as that of the initialization current, In any case, there will be no flipping of a certain tunnel junction, which has high reliability and avoids the fact that one of the tunnel junctions is easily flipped during readout in the prior art corresponding to the connection form of the reference layer and the free layer. problem; in addition, the corresponding preparation process is relatively simple, eliminating the need for through holes in the traditional structure.

It should be noted that, in the drawings or descriptions of the specification, similar or identical parts all use the same figure numbers. Implementations not shown or described in the accompanying drawings are forms known to those of ordinary skill in the art. The directional terms mentioned in the embodiments, such as "upper", "lower", "front", "rear", "left", "right", etc., are only referring to the directions of the drawings. Therefore, the directional terms used are for illustration and not for limiting the protection scope of the present disclosure.

Moreover, in order to achieve the purpose of tidy drawing, some conventionally used structures and components may be shown in a simple schematic way in the accompanying drawings. In addition, some features in the drawings of this application may be slightly enlarged or their proportions or dimensions may be changed to facilitate understanding and viewing of the technical features of the present disclosure, but this is not intended to limit the present disclosure. The actual size and specifications of the products manufactured according to the content disclosed in this disclosure should be adjusted according to the requirements during production, the characteristics of the product itself, and the content of this disclosure, which are hereby declared.

Words such as "first", "second", "third" and the like used in the description and claims to modify the corresponding elements do not in themselves mean that the elements have any ordinal numbers, nor The use of these ordinal numbers to represent the sequence of an element with respect to another element, or the order of manufacturing methods, is only used to clearly distinguish one element with a certain designation from another element with the same designation.

Furthermore, the word "comprising" or "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

The specific embodiments described above further describe the purpose, technical solutions and beneficial effects of the present disclosure in detail. It should be understood that the above descriptions are only specific embodiments of the present disclosure, and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims (8)

1. a preparation method of STT-MRAM reference unit, is characterized in that, comprises: preparing two series-connected tunnel junctions, wherein the two series-connected tunnel junctions have different resistance states, and the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction; The preparation of two tunnel junctions in series includes: Deposit the bottom electrode layer and the thin film material of the tunnel junction, the tunnel junction is as follows from bottom to top: reference layer, insulating layer and free layer; patterning the tunnel junction and the bottom electrode layer by photolithography, so that the tunnel junction and the bottom electrode layer below it form two spaced apart parts; filling a dielectric layer over the structure having two portions spaced apart; Opening holes on the dielectric layer, respectively etching the dielectric layer to the surface of the bottom electrode layer and the surface of the free layer of the tunnel junction, correspondingly obtaining bottom electrode through holes and top electrode through holes; depositing electrode material; and The electrode material is patterned by photolithography technology, and the electrode material between the two spaced top electrode through holes is the top electrode, and the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction by using the top electrode , the electrode material corresponding to the through hole of the bottom electrode is the bottom electrode for the lead corresponding to the bottom electrode layer. 2. A kind of STT-MRAM reference unit, is prepared by the preparation method described in claim 1, and this reference unit comprises two parallel branches, wherein one branch comprises two tunnel junctions in series, it is characterized in that, this The resistance states of the two series-connected tunnel junctions are different, and the free layer of one tunnel junction is connected in series with the free layer of the other tunnel junction; the reference unit is initialized by passing a unidirectional current to each branch, and the reference unit passes through A read operation is implemented with the same current direction as the initialization direction. 3. The reference unit according to claim 2, wherein the two parallel branches have the same structure. 4 . The reference unit according to claim 2 , wherein the initialization method of the branch including two tunnel junctions in series is: a unidirectional current is passed through, and a high resistance state and a low resistance state are correspondingly obtained. 5. The reference unit according to claim 3, characterized in that, the initialization method of the two parallel branches is as follows: a unidirectional current is passed on the main road, and a high-impedance state is correspondingly obtained on each branch and a low impedance state. 6 . The reference unit according to claim 4 or 5 , wherein when the direction of the unidirectional current is changed, the resistance states of the two series-connected tunnel junctions are exchanged. 7 . 7. The reference unit according to claim 5, wherein the equivalent resistance of the reference unit is 1/2 of the sum of the resistance values of the low resistance state and the high resistance state. 8. A chip, comprising the STT-MRAM reference unit according to any one of claims 2 to 6.

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