CN1101992C - 8-bit D/A converter - Google Patents

Abstract

The present invention is an eight-bit D/A converter circuit, which includes four parts: effect transistor and NOT gate, input control circuit, CMOS tube analog switch, eight-bit T-type resistance network and emitter follower output. The input signal is an eight-bit digital quantity, and the output is an analog quantity of 0-5.0V; the difference between the present invention and the previous D/A converter is that it uses a CMOS tube as the analog switch circuit, which is more powerful than the bipolar D/A converter. Low power consumption, less affected by external factors such as temperature and radiation, so it is suitable for working under severe environmental changes.

Description

An Eight-bit D/A Converter Circuit

The invention relates to a D/A converter circuit, in particular to an eight-bit D/A converter circuit capable of reducing the number of components and realizing the D/A conversion function with a monolithic integrated circuit.

Space detection requires devices with low power consumption, high reliability, and adaptability to various space environments.

The existing D/A converter devices used in space environment science all have the disadvantages of complex structure and large space occupation.

The object of the present invention is to provide an eight-bit D/A converter circuit, which has the advantages of using fewer components and occupying less space.

An eight-bit D/A converter circuit of the present invention includes an effect transistor and a NOT gate, wherein the eight-bit output signals of the NOT gates N1, N3, N5, N7, N9, N11, N13, and N15 are connected to the NOT gates N2, N15, respectively. N4, N6, N8, N10, N12, N14, N16, and at the same time respectively connected to the gates of field effect transistors M1, M3, M5, M7, M9, M11, M13, M15; NOT gates N2, N4, N6, N8 , N10, N12, N14, and N16 are respectively connected to the gates of field effect transistors M2, M4, M6, M8, M10, M12, M14, and M16, and M1, M3, M5, M7, M9, M11, M13, The source of M15 and one end of R1 are connected to the ground Vss, the sources of M2, M4, M6, M8, M10, M12, M14, and M16 are connected to the reference voltage Vref; M1 is connected to the drain of M2 and connected to the resistor R1 through the resistor R2 , between R10; M3 is connected to the drain of M4 and connected between resistors R10 and R11 through resistor R3; M5 is connected to the drain of M6 and connected between resistors R11 and R12 through resistor R4; M7 is connected to the drain of M8 and connected to Connect between resistors R12 and R13 through resistor R5; M9 is connected to the drain of M10 and connected between resistors R13 and R14 through resistor R6; M11 is connected to the drain of M12 and connected between resistors R14 and R15 through resistor R7; M13 is connected to the drain of M14 and connected between resistors R15 and R16 through resistor R8; M15 is connected to the drain of M16 and connected to the other end of resistor R16 through resistor R9 and then connected to the gate of M21; M21 and M20 are connected to the drain. At the same time, it is connected to the source of M18, the gate of M18, the gate of M17 are connected to the source and the gate of M19, the drains of M17, M18, and M19 are connected to the power supply voltage Vdd, the source of M19 is connected to the drain of M22, and the source of M21 The level is connected to the drain level of M24, the gate level of M22, and the capacitor C1, the gate level of M24, M23, the drain level of M23, and the source level of M20 are connected, the source level of M23, M24, and M22 is grounded, and the gate level of M20 is connected to the other end of the capacitor C1. Output Q.

The examples of the present invention will be described in detail below in conjunction with the accompanying drawings.

FIG. 1 is a circuit schematic diagram of an embodiment of the present invention.

Please refer to the accompanying drawings, an eight-bit D/A converter circuit, which includes effect transistors and NOT gates, wherein the eight-bit output signals of the NOT gates N1, N3, N5, N7, N9, N11, N13, and N15 are respectively connected to To NOT gates N2, N4, N6, N8, N10, N12, N14, N16, and at the same time respectively connected to the gates of field effect transistors M1, M3, M5, M7, M9, M11, M13, M15; NOT gates N2, The output terminals of N4, N6, N8, N10, N12, N14, and N16 are respectively connected to the gates of field effect transistors M2, M4, M6, M8, M10, M12, M14, and M16, and M1, M3, M5, M7, and M9 The sources of M11, M13, M15 and one end of resistor R1 are connected to the ground Vss, the sources of M2, M4, M6, M8, M10, M12, M14, M16 are connected to the reference voltage Vref; M1 is connected to the drain of M2 and passed through Resistor R2 is connected between resistors R1 and R10; M3 is connected to the drain of M4 and connected between resistors R10 and R11 through resistor R3; M5 is connected to the drain of M6 and connected between resistors R11 and R12 through resistor R4; M7 It is connected to the drain of M8 and connected between resistors R12 and R13 through resistor R5; M9 is connected to the drain of M10 and connected between resistors R13 and R14 through resistor R6; M11 is connected to the drain of M12 and connected to the resistor through resistor R7 Between R14 and R15; M13 is connected to the drain of M14 and connected between resistors R15 and R16 through resistor R8; M15 is connected to the drain of M16 and connected to the other end of resistor R16 through resistor R9 and then connected to the gate of M21; M21 , M20 are connected to the drain, and are connected to the source of M18 at the same time, the gate of M18, the gate of M17 are connected to the source and the gate of M19, the drains of M17, M18, and M19 are connected to the power supply voltage Vdd, and the source of M19 is connected to the source of M22 The drain is connected, the source of M21 is connected to the drain of M24, the gate of M22, and the capacitor C1, the gate of M24, M23, the drain of M23, and the source of M20 are connected, the source of M23, M24, and M22 is grounded, and the gate of M20 is connected to the capacitor The other end of C1 is connected to the output terminal Q.

The operating principle of the example of the present invention is: when d ₇ d ₆ d ₅ d ₄ d ₃ d ₂ d ₁ d ₀ =00000001, only the analog switch A is connected to the reference voltage Vref, and BH is all connected to the common terminal, from AA' It is not difficult to see that the output voltage will be attenuated by 1/2 every time a node passes through, so the reference voltage Vref added to A will only provide the reference voltage Vref/2 at the HH' terminal ⁸ . Similarly, when the reference voltage Vref is applied to B, C, D, E, F, G, and H respectively, the voltages provided by them at the HH' terminal will be the reference voltage Vref/2 ⁷ , Vref/2 ⁶ , Vref/2 ⁵ , Vref/2 ⁴ , Vref/2 ³ , Vref/2 ² , Vref/2 ¹ , and the internal resistance seen from the HH' terminal to the left is always R. So the output voltage _Vout is equal to: $V_{\mathrm{out}}=\frac{V_{\mathrm{ref}}}{2^8}(d_7{2}^7+d_6{2}^6+d_5{2}^5+d_4{2}^4+{d_3{2}^3+d}_2{2}^2+d_1{2}^1+d_0{2}^0)$

Follower output is adopted to make the output amplitude of the Q terminal the same as that of the output Vout terminal, and its input resistance is very large, and the output resistance is very small, which ensures the driving ability of the present invention, is convenient for long-distance testing in actual use, and greatly improves the present invention. The reliability of an instance.

The invention is composed of four parts: an input control circuit, a CMOS tube analog switch, an eight-bit T-shaped resistance network and an output follower of a transmitter. The input signal is an eight-digit digital quantity, and the output is an analog quantity of 0-5.0V.

The present invention differs from the previous D/A converters in that it adopts CMOS tubes as the analog switch circuit, which has lower power consumption than bipolar D/A converters and is less affected by external factors such as temperature and radiation, so it is suitable for use in Work under severe environmental changes.

Claims (1)

1, a kind of eight D/A converter circuit, comprising effect transistor and not gate, it is characterized in that, wherein not gate N1, N3, N5, N7, N9, N11, eight output signals of N13, N15 are connected to not gate N2, N4, N6, N8, N10, N12, N14, N16 respectively, and be connected to field effect transistor M 1 respectively simultaneously, the grid level of M3, M5, M7, M9, M11, M13, M15; The output of not gate N2, N4, N6, N8, N10, N12, N14, N16 is connected to the grid level of field effect transistor M 2, M4, M6, M8, M10, M12, M14, M16 respectively, the source class of M1, M3, M5, M7, M9, M11, M13, M15 and resistance R 1 one ends link to each other with ground Vss, and the source class of M2, M4, M6, M8, M10, M12, M14, M16 is connected to reference voltage V ref; M1 links to each other with M2 leakage level and is connected between resistance R 1, the R10 by resistance R 2; M3 links to each other with M4 leakage level and is connected between resistance R 10, the R11 by resistance R 3; M5 links to each other with M6 leakage level and is connected between resistance R 11, the R12 by resistance R 4; M7 links to each other with M8 leakage level and is connected between resistance R 12, the R13 by resistance R 5; M9 links to each other with M10 leakage level and is connected between resistance R 13, the R14 by resistance R 6; M11 links to each other with M12 leakage level and is connected between resistance R 14, the R15 by resistance R 7; M13 links to each other with M14 leakage level and is connected between resistance R 15, the R16 by resistance R 8; M15 and M16 leak that level links to each other and are connected to M21 grid level again by the other end that resistance R 9 is connected to resistance R 16; M21, M20 leak level and link to each other, and link to each other with the M18 source class simultaneously, the grid level of M18 grid level, M17 grid level and source class and M19 links to each other, the leakage level of M17, M18, M19 is connected to supply voltage Vdd, and the M19 source class leaks level with M22 and links to each other, and the M21 source class leaks level, M22 grid level and capacitor C 1 with M24 and links to each other, M24, M23 grid level, M23 leak level, the M20 source class links to each other, the source class ground connection of M23, M24, M22, M20 grid level is connected with capacitor C 1 other end, is output Q.