CN110162377A - A kind of communication means and logic processor - Google Patents

Abstract

The embodiment of the present application discloses a kind of communication means and logic processor, and the processor resource for reducing to sender occupies and the final transmission delay of IPI.The embodiment of the present application provides a kind of communication means, it include: after the first logic processor enters virtualization mode, first logic processor interrupts IPI information between obtaining processor, and the IPI information includes: the mark and virtual interrupt information of target virtual processor；First logic processor carries out virtual processor address translation to the mark of the target virtual processor, obtains the target logic processor where the target virtual processor is currently run；First logic processor sends the IPI information to the target logic processor.

Description

A communication method and logic processor

technical field

The present application relates to the field of computer technology, in particular to a communication method and a logic processor.

Background technique

In a current processor (Central Processing Unit, CPU), a physical CPU module is externally presented as multiple instruction processing units, and each instruction processing unit can independently execute an instruction stream. These instruction processing components are generally called logical processors (Logical CPU). During the operation of a computer system, asynchronous communication is required between logical processors, for example, one logical processor needs to notify other logical processors to perform task switching. In another example, a logical processor needs to notify other logical processors to clear certain translation lookaside buffer (Translation Lookaside Buffer, TLB) entries. In another example, a logical processor needs to notify other logical processors to perform initialization. This asynchronous communication between logical processors is generally called an Inter Processor Interrupt (IPI), or a Software Generated Interrupt (SGI).

Computer virtualization is a technology that presents a single physical computer as multiple computers on the network. Computers that network users can use but do not actually exist are called virtual computers, or virtual machines (VMs) for short. For network users, a virtual machine, like a real physical computer, has hardware devices such as processors, memory, network cards, and disks. The processor included in the virtual machine is called a virtual processor (Virtual CPU). When the logical processor runs the entity corresponding to the virtual processor, it is externally shown that the virtual processor is running. The IPI sent by a virtual processor to other virtual processors during operation is called a virtual IPI.

In order to allow multiple virtual machines to safely co-exist on a single physical computer, it is necessary to limit the capabilities of the virtual machines without hindering the normal work of the virtual machines. This process is called computer system virtualization and is responsible for realizing the The virtualized software is called a virtual machine monitor (Virtual Machine Monitor, VMM).

Hardware Virtual Machine (Hardware Virtual Machine, HVM) is a kind of virtualization that relies on hardware CPU support. Its characteristics are: it does not require the virtual machine operating system to provide cooperation with computer system virtualization. Manage the virtual machine like a computer, such as sending IPI. Hardware support for virtualization can be embodied as: providing a specific processor operating mode, such as a virtualization mode. The hardware processor guarantees that "the state of the processor seen by the virtual machine operating system running in this mode is the same as that of the non-virtualized situation, and the privileged operations performed by the virtual machine operating system of HVM can either be completed directly or cause the logical processor to exit. In the current operating mode, go to the processing logic of the VMM". At this time, when the VMM needs to keep a virtual processor in the running state, the VMM makes the logical processor enter the virtualization mode, and the logical processor executes the code that the virtual processor needs to execute in the running state. When the logical processor sends an IPI To exit the virtualization mode, the VMM registers the "code entry that should be executed after exiting the virtualization mode" with the logical processor.

In the prior art, computer system virtualization is realized by VMM software, and the VMM software adopts the same method as in the non-virtualization situation. A virtual processor sends an IPI to a target virtual processor based on a logical processor sending an IPI, and the IPI It is an operation that causes the logical processor to exit the virtualization mode. Therefore, it takes a certain amount of time for the logical processor as the sender to switch modes when it exits the virtualization mode, which will increase the processor resource usage of the sender and the final transmission of IPI. Delay.

Contents of the invention

The embodiment of the present application provides a communication method and a logical processor, which are used to reduce processor resource occupation of the sender and final transmission delay of the IPI.

In order to solve the above technical problems, the embodiments of the present application provide the following technical solutions:

In the first aspect, the embodiment of the present application provides a communication method, which is characterized by comprising: after the first logical processor enters the virtualization mode, the first logical processor acquires inter-processor interrupt IPI information, and the IPI The information includes: the identification of the target virtual processor and virtual interrupt information; the first logical processor performs virtual processor address translation on the identification of the target virtual processor to obtain the target logic where the target virtual processor is currently running A processor: the first logical processor sends the IPI information to the target logical processor.

In this embodiment of the present application, after the first logical processor enters the virtualization mode, the first logical processor acquires processor interrupt IPI information, and the IPI information includes: the target virtual processor identifier and virtual interrupt information; the first logical processor The processor performs virtual processor address translation on the identifier of the target virtual processor to obtain the target logical processor where the target virtual processor is currently running; the first logical processor sends IPI information to the target logical processor. In this embodiment of the present application, the first logical processor can perform virtual processor address translation on the identifier of the target virtual processor, so as to determine the target logical processor where the target virtual processor is currently running. Therefore, the first logical processor can In the virtualization mode, IPI information is directly sent to the running target virtual processor, so that the target virtual processor can be injected into IPI, without the need to send IPI information through the VMM, and the first logical processor does not need to exit virtualization mode, thus reducing the processor resource occupation of the sender and the final transmission delay of the IPI.

In a possible design of the first aspect of the present application, the method further includes: after the first logical processor performs virtual processor address translation on the identifier of the target virtual processor, determine the target virtual processor When no logical processor is running, the first logical processor stores the IPI information and exits the virtualization mode; the first logical processor notifies the virtual machine monitor VMM that the first logical processor The device stores the IPI information. Wherein, after the first logical processor performs virtual processor address translation on the identification of the target virtual processor and determines that the target virtual processor is not running on any logical processor, it means that the first logical processor cannot determine the target virtual processor. The target logical processor where the processor is currently running can store the IPI information at this time, for example, in the sender exception information storage area, so that the vmm software running in the non-virtualization mode can query the IPI sending details.

In a possible design of the first aspect of the present application, the method further includes: when the first logical processor fails to send the IPI information to the target logical processor, the first logical processor stores the IPI information, and exit the virtualization mode; the first logical processor notifies the VMM that the first logical processor stores the IPI information. Wherein, the first logical processor may set the interrupt number used when "delivering interrupt", and execute the IPI information after the logical processor enters the virtualization mode. After exiting the virtualization mode, judge the exit reason. If the reason is "virtual interrupt delivery in virtualization mode", the VMM will use the interrupt number to continue executing the IPI interrupt information.

In a possible design of the first aspect of the present application, the method further includes: the first logical processor sending an identifier of the virtual machine VM where the target virtual processor is located to the target logical processor. Wherein, the first logical processor also needs to send the identifier of the VM where the target virtual processor is located to the target logical processor, so that the receiver can determine the VM where the target virtual processor is located.

In a possible design of the first aspect of the present application, the first logical processor performs virtual processor address translation on the identifier of the target virtual processor, including: the first logical processor queries the virtual processor The routing table to the logical processor performs virtual processor address translation on the identifier of the target virtual processor. Wherein, when running a virtual processor on each logical processor, each logical processor corresponds to a virtual processor-to-logical processor routing table indexed according to the virtual processor number, and a logical processor can access its corresponding The routing table from the virtual processor to the logical processor, so as to complete the address translation from the virtual processor to the corresponding logical processor.

In a possible design of the first aspect of the present application, the routing table from the virtual processor to the logical processor is stored in the storage area of the first logical processor; or, the routing table from the virtual processor to the logical processor The routing table of the virtual processor is stored in the storage area of the physically pluggable processor where the first logical processor is located; or, the routing table from the virtual processor to the logical processor is stored in the memory.

In a possible design of the first aspect of the present application, the first logical processor has an interface for modifying the routing table from the virtual processor to the logical processor.

In a second aspect, the embodiment of the present application provides a communication method, including: after the second logical processor enters the virtualization mode, the second logical processor receives processor interrupt IPI information sent by the first logical processor, and the The IPI information includes: the identification of the target virtual processor and virtual interrupt information; the second logical processor performs virtual interrupt injection processing on the second virtual processor according to the virtual interrupt information, and the second virtual processor is the The virtual processor that is running after the second logical processor enters the virtual mode.

In the foregoing embodiments of the present application, the first logical processor can perform virtual processor address translation on the identifier of the target virtual processor, so as to determine the target logical processor where the target virtual processor is currently running. Therefore, the first logical processor In the virtualization mode, the processor can directly send IPI information to the running target virtual processor. The second logical processor is used as the target logical processor, and the second logical processor runs on the target virtual processor. Therefore, the second logical processor The processor can perform IPI injection on the target virtual processor, and the IPI information does not need to be sent through the VMM, and the first logical processor does not need to exit the virtualization mode, so it can reduce the processor resource occupation and IPI of the sender. final transmission delay.

In a possible design of the second aspect of the present application, the method further includes: when the identifier of the second virtual processor is different from the identifier of the target virtual processor, the second logical processor stores the IPI information and exit the virtualization mode. Wherein, when the second logical processor determines that the currently running second virtual processor is not the target virtual processor, the second logical processor may store the IPI information, for example, in the receiver exception information storage area, so that the running The vmm software in non-virtualization mode can query the detailed information of IPI transmission.

In a possible design of the second aspect of the present application, the method further includes: after the second logical processor receives the IPI information sent by the first logical processor, the second logical processor determines the second virtual processing Whether the identifier of the second logical processor is the same as the identifier of the target virtual processor; when the identifier of the second virtual processor is the same as the identifier of the target virtual processor, trigger the execution of the following steps: the second logical processor according to The virtual interrupt information performs virtual interrupt injection processing on the second virtual processor.

In the third aspect of the present application, the constituent modules of the logic processor can also execute the steps described in the aforementioned first aspect and various possible implementations. For details, see the aforementioned first aspect and various possible implementations. instruction of.

In a third aspect, the embodiment of the present application provides a logical processor, the logical processor is a first logical processor, and the first logical processor includes: a processing module, configured to After the mode, the processor interrupt IPI information is obtained, and the IPI information includes: the identification of the target virtual processor and virtual interrupt information; the processing module is also used to translate the address of the virtual processor to the identification of the target virtual processor , to obtain the target logical processor where the target virtual processor is currently running; a sending module, configured to send the IPI information to the target logical processor.

In a possible design of the third aspect of the present application, the processing module is further configured to determine that the target virtual processor is not in any logical When the processor is running, store the IPI information and exit the virtualization mode; the sending module is further configured to notify a virtual machine monitor VMM that the first logical processor has stored the IPI information.

In a possible design of the third aspect of the present application, the processing module is further configured to store the IPI information when the first logical processor fails to send the IPI information to the target logical processor, and exit the virtualization mode; the sending module is further configured to notify the VMM that the first logical processor has stored the IPI information.

In a possible design of the third aspect of the present application, the sending module is further configured to send the identifier of the virtual machine VM where the target virtual processor is located to the target logical processor.

In a possible design of the third aspect of the present application, the processing module is specifically configured to perform virtual processor address translation on the identifier of the target virtual processor by querying a routing table from a virtual processor to a logical processor .

In a possible design of the third aspect of the present application, the routing table from the virtual processor to the logical processor is stored in the storage area of the first logical processor; or, the routing table from the virtual processor to the logical processor The routing table of the virtual processor is stored in the storage area of the physically pluggable processor where the first logical processor is located; or, the routing table from the virtual processor to the logical processor is stored in the memory.

In a possible design of the third aspect of the present application, the first logical processor has an interface for modifying the routing table from the virtual processor to the logical processor.

In a fourth aspect, the embodiment of the present application provides a logical processor, the logical processor is a second logical processor, and the second logical processor includes: a receiving module, configured to After the mode, the processor interrupt IPI information sent by the first logical processor is received, and the IPI information includes: the identification of the target virtual processor and virtual interrupt information; the processing module is configured to process the second logical processor according to the virtual interrupt information. The virtual processor performs virtual interrupt injection processing, and the second virtual processor is a running virtual processor after the second logical processor enters the virtual mode.

In a possible design of the fourth aspect of the present application, the processing module is further configured to store the IPI information when the identifier of the second virtual processor is different from the identifier of the target virtual processor, and exit the virtualization mode.

In a possible design of the fourth aspect of the present application, the processing module is further configured to, after the receiving module receives the IPI information sent by the first logical processor, determine whether the identifier of the second virtual processor is consistent with the target The identity of the virtual processors is the same;

The processing module is further configured to, when the identifier of the second virtual processor is the same as the identifier of the target virtual processor, trigger the execution of the following step: perform a virtual interrupt on the second virtual processor according to the virtual interrupt information Injection processing.

In the fourth aspect of the present application, the constituent modules of the logical processor can also execute the steps described in the aforementioned second aspect and various possible implementations. For details, refer to the aforementioned second aspect and various possible implementations. instruction of.

In the fifth aspect, the embodiment of the present application provides a computer-readable storage medium, where instructions are stored in the computer-readable storage medium, and when the computer-readable storage medium is run on a computer, it causes the computer to execute the methods described in the above aspects.

In a sixth aspect, the embodiments of the present application provide a computer program product including instructions, which, when run on a computer, cause the computer to execute the methods described in the above aspects.

In the seventh aspect, the embodiment of the present application provides a communication device, which may include entities such as terminal equipment or chips, and the communication device includes: a processor and a memory; the memory is used to store instructions; the processor is used to Executing the instructions in the memory, specifically performing the method as described in any one of the foregoing first aspect or second aspect.

In an eighth aspect, the present application provides a chip system, the chip system includes a processor, configured to support the network device to implement the functions involved in the above aspect, for example, for example, sending or processing the data involved in the above method and/or information. In a possible design, the chip system further includes a memory, and the memory is configured to store necessary program instructions and data of the network device. The system-on-a-chip may consist of chips, or may include chips and other discrete devices.

Description of drawings

FIG. 1 is a schematic diagram of a system architecture of a processor provided in an embodiment of the present application;

FIG. 2 is a schematic block diagram of a communication method provided by an embodiment of the present application;

FIG. 3 is a schematic block flow diagram of another communication method provided by an embodiment of the present application;

FIG. 4 is a schematic diagram of a basic architecture of a logic processor provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of an interaction flow between the logical processor of the sender and the logical processor of the receiver according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another interaction flow between the logical processor of the sender and the logical processor of the receiver in the embodiment of the present application;

FIG. 7 is a schematic diagram of modules included in the processor socket in the embodiment of the present application;

FIG. 8 is a schematic flow diagram of a logical processor executing IPI information in a virtualization mode provided by an embodiment of the present application;

9 is a schematic diagram of the processing flow after the logical processor detects that there is information in notify_if in the virtualization mode provided by the embodiment of the present application;

FIG. 10 is a schematic diagram of a processing flow for a notify_if request by a logical processor in virtualization mode provided by an embodiment of the present application;

FIG. 11 is a schematic diagram of the composition and structure of a first logical processor provided by the embodiment of the present application;

FIG. 12 is a schematic diagram of the composition and structure of a second logical processor provided by the embodiment of the present application.

Detailed ways

The embodiment of the present application provides a communication method and a logical processor, which are used to reduce processor resource occupation of the sender and final transmission delay of the IPI.

Embodiments of the present application are described below in conjunction with the accompanying drawings.

The terms "first", "second" and the like in the specification and claims of the present application and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, and this is merely a description of the manner in which objects with the same attribute are described in the embodiments of the present application. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, product, or apparatus comprising a series of elements is not necessarily limited to those elements, but may include elements not expressly included. Other elements listed explicitly or inherent to the process, method, product, or apparatus.

First, the important terms in the embodiments of the present application are explained as follows:

Virtual machine: In the architecture of computer science, it refers to a special software that can create an environment between the computer platform and the end user, and the end user operates the software based on the environment created by the software . In computer science, a virtual machine is a software implementation of a computer that can run programs like a real machine. Refers to a complete computer system that is simulated by software and has complete hardware system functions and runs in an independent environment. One physical machine can virtualize multiple virtual machines according to application needs, so that multiple operating systems can run on one physical machine at the same time. For each operating system, users can perform virtual partitioning and configuration. At the same time, users can switch between multiple operating systems. A virtual machine is a software computer, similar to a physical machine, that runs an operating system and applications. Multiple virtual machines can run simultaneously on the same host system.

Virtual Machine Monitor (Virtual Machine Monitor, VMM): VMM is actually a simple operating system. It provides many abstract virtual machines that allow multiple operating systems to run simultaneously. Even these operating systems don't need to be the same. From the perspective of the system, each virtual machine at this time is actually equivalent to a process of the OS (operating system) of VMM.

hyper-threading: Hyper-threading: using another idea to improve the performance of the CPU, so that the CPU can execute multiple threads at the same time, so that the CPU can be more efficient, that is, the so-called "Hyper-Threading (HT" for short)" technology. Hyper-threading technology uses special hardware instructions to simulate two logical cores into two physical chips, so that a single processor can use thread-level parallel computing, which is compatible with multi-threaded operating systems and software, reducing CPU idle time. Improve CPU operating efficiency. Using hyper-threading technology can execute two threads at the same time, but it is not like two real CPUs, each CPU has independent resources. When two threads both need a certain resource at the same time, one of them should temporarily stop and give up the resource until these resources are idle before continuing. Therefore, the performance of hyperthreading is not equal to the performance of two CPUs.

Socket: socket. A receiving receptacle for a connector into which a plug is inserted.

Processor socket: A CPU hardware module that can be physically plugged and unplugged.

Inter-Processor Interrupt (IPI): An asynchronous notification from one processor to another. On some systems, this is called SGI/Software Interrupt. IPI is a special interrupt. In a symmetric multiprocessing (SMP, symmetric multiprocessing) environment, it can be used by any processor to interrupt another processor. IPI is typically used to achieve coherent synchronization between caches (Cache CoherencySynchronization) and notify the other party for task scheduling/preemption.

Symmetric multiprocessing (symmetric multiprocessing, SMP): SMP refers to the collection of a group of processors (multiple CPUs) on a computer, and the memory subsystem and bus structure are shared between each CPU. The system distributes task queues symmetrically over multiple CPUs, and all CPUs can equally access memory, input/output (Input/Output, I/O) and external devices.

Each will be described in detail below.

Please refer to FIG. 1 , which is a schematic diagram of a system architecture of a processor provided by an embodiment of the present application. The system architecture may include: a processor and a virtual machine, wherein the processor is hardware, and the virtual machine is software. The processor, also known as the central processing unit, is the calculation and control unit of the computer. It is a component that interprets and executes instructions. ), to exchange information with other components. The processor may include a plurality of logical processors (logical processor, LP), and the logical processor may also be called a physical processor, such as LP1, LP2, ..., LPn, n represents the number of logical processors, and the value of n It can be a positive integer, and a logical processor is a processor unit included in a processor socket with independent execution threads. The virtual machine may include multiple virtual processors (virtual processors, VPs), such as Vp1, VP2, ..., VPn, and the value of n may be a positive integer.

As shown in Figure 2, a communication method provided by the embodiment of this application includes:

201. After the first logical processor enters the virtualization mode, the first logical processor acquires IPI information, where the IPI information includes: an identifier of a target virtual processor and virtual interrupt information.

In this embodiment of the present application, a virtual processor is currently running on the first logical processor, and the virtual processor running on the first logical processor is defined as the first virtual processor. When the processor injects the IPI, the first virtual processor may use the first logical processor to send IPI information, where the IPI information includes: an identifier of the target virtual processor and virtual interrupt information. The identifier of the target virtual processor may be the number of the target virtual processor, and the virtual interrupt information may be detailed information of the virtual IPI, for example, the virtual interrupt information may include an interrupt number and an interrupt sending method.

202. The first logical processor performs virtual processor address translation on the identifier of the target virtual processor to obtain the target logical processor where the target virtual processor is currently running.

In the embodiment of the present application, the first logical processor can realize the translation from the virtual processor number to the logical processor number, and its function includes maintaining and querying the correspondence table between the virtual processor number and the logical processor number. Therefore, after the first logical processor obtains the identifier of the target virtual processor, it may perform virtual processor address translation on the identifier of the target virtual processor to obtain the target logical processor where the target virtual processor is currently running.

In some embodiments of the present application, in step 202, the first logical processor performs virtual processor address translation on the identification of the target virtual processor, including:

The first logical processor performs virtual processor address translation on the identifier of the target virtual processor by querying a virtual processor-to-logical processor routing table.

Wherein, when running a virtual processor on each logical processor, each logical processor corresponds to a virtual processor-to-logical processor routing table indexed according to the virtual processor number, and a logical processor can access its corresponding The routing table from the virtual processor to the logical processor, so as to complete the address translation from the virtual processor to the corresponding logical processor.

In some embodiments of the present application, the routing table from the virtual processor to the logical processor is stored in the storage area of the first logical processor; or,

The routing table from the virtual processor to the logical processor is stored in the storage area of the processor where the first logical processor is located and can be used for physical plugging; or,

The virtual processor to logical processor routing table is stored in memory.

Wherein, the processor that can be used for physical plugging refers to the aforementioned processor socket. That is, the routing table from a virtual processor to a logical processor can be stored independently by a logical processor, or it can be shared globally within the scope of the processor socket to which the logical processor belongs, or stored in memory, so that each logical processor The virtual processor can use a virtual processor pointer to read the virtual processor to logical processor routing table from this memory.

In some embodiments of the present application, the first logical processor has an interface for modifying a virtual processor to logical processor routing table.

Among them, the logical processor can also provide a support mechanism for modifying the routing table from the virtual processor to the logical processing. Revise. As another example, a logical processor may use an inter-processor communication mechanism to notify other logical processors to modify a routing table from a virtual processor to a logical processor, and the specific implementation manner is not limited here.

203. The first logical processor sends the IPI information to the target logical processor.

In this embodiment of the application, after the first logical processor determines the target logical processor where the target virtual processor is currently running, the first logical processor can send IPI information to the target logical processor, so that the target logical processor can Perform IPI injection according to IPI information.

In some embodiments of the present application, the communication method provided in the embodiment of the present application may further include the following steps:

After the first logical processor performs virtual processor address translation on the identification of the target virtual processor, and determines that the target virtual processor is not running on any logical processor, the first logical processor stores the IPI information and exits the virtualization mode;

The first logical processor notifies the VMM that the first logical processor stores the IPI information.

Wherein, after the first logical processor performs virtual processor address translation on the identification of the target virtual processor and determines that the target virtual processor is not running on any logical processor, it means that the first logical processor cannot determine the target virtual processor. The target logical processor where the processor is currently running can store the IPI information at this time, for example, in the sender exception information storage area, so that the vmm software running in the non-virtualization mode can query the IPI sending details.

In some embodiments of the present application, the communication method provided in the embodiment of the present application may further include the following steps:

When the first logical processor fails to send the IPI information to the target logical processor, the first logical processor stores the IPI information and exits the virtualization mode;

The first logical processor notifies the VMM that the first logical processor stores the IPI information.

Wherein, the first logical processor may set the interrupt number used when "delivering interrupt", and execute the IPI information after the logical processor enters the virtualization mode. After exiting the virtualization mode, judge the exit reason. If the reason is "virtual interrupt delivery in virtualization mode", the VMM will use the interrupt number to continue executing the IPI interrupt information.

In some embodiments of the present application, the communication method provided in the embodiment of the present application may further include the following steps:

The first logical processor sends an identifier of a virtual machine (Virtual Machine, VM) where the target virtual processor is located to the target logical processor.

Wherein, the first logical processor also needs to send the identifier of the VM where the target virtual processor is located to the target logical processor, so that the receiver can determine the VM where the target virtual processor is located.

It can be seen from the examples of the foregoing embodiments that when the first logical processor enters the virtualization mode, the first logical processor acquires processor interrupt IPI information, and the IPI information includes: the target virtual processor identifier and virtual interrupt information; The logical processor performs virtual processor address translation on the identifier of the target virtual processor to obtain the target logical processor where the target virtual processor is currently running; the first logical processor sends IPI information to the target logical processor. In this embodiment of the present application, the first logical processor can perform virtual processor address translation on the identifier of the target virtual processor, so as to determine the target logical processor where the target virtual processor is currently running. Therefore, the first logical processor can In the virtualization mode, IPI information is directly sent to the running target virtual processor, so that the target virtual processor can be injected into IPI, without the need to send IPI information through the VMM, and the first logical processor does not need to exit virtualization mode, thus reducing the processor resource occupation of the sender and the final transmission delay of the IPI.

The foregoing embodiments have described the execution flow of the logic processor of the sender, and then illustrate the execution flow of the logic processor of the receiver with an example. Please refer to FIG. 3. The communication method provided by the embodiment of the present application mainly includes Follow the steps below:

301. After the second logical processor enters the virtualization mode, the second logical processor receives IPI information sent by the first logical processor, where the IPI information includes: an identifier of a target virtual processor and virtual interrupt information.

Among them, in the embodiment of the present application, based on the communication mechanism of the processor hardware, after the first logical processor sends the IPI information, the second logical processor can receive the IPI information as the receiver, and the second logical processor can determine from the IPI information Output the identification and virtual interrupt information of the target virtual processor.

302. The second logical processor performs virtual interrupt injection processing on the second virtual processor according to the virtual interrupt information.

In this embodiment of the present application, the running second virtual processor is the virtual processor that needs to be injected with an interrupt, and the second logical processor performs virtual interrupt injection processing on the second virtual processor according to the virtual interrupt information. Through the hardware direct communication between the first logical processor and the second logical processor, in the embodiment of the present application, the virtual terminal injection process to the target virtual processor can be realized. The whole process does not require the access of VMM software, and the second logical processor The processor also does not need to exit virtualization mode.

In some embodiments of the present application, after step 301 is performed, the following steps may also be performed:

The second logical processor determines whether the identifier of the second virtual processor is the same as the identifier of the target virtual processor, and the second virtual processor is the running virtual processor after the second logical processor enters the virtual mode.

When the identifier of the second virtual processor is the same as the identifier of the target virtual processor, the aforementioned step 302 is triggered: the second logical processor performs virtual interrupt injection processing on the second virtual processor according to the virtual interrupt information.

In this embodiment of the present application, the second logical processor judges whether the second virtual processor currently running on the second logical processor is the target virtual processor, for example, the second logical processor may determine the Whether the identifier is the same as the identifier of the target virtual processor, the second virtual processor is the running virtual processor after the second logical processor enters the virtual mode.

In the embodiment of the present application, when the ID of the second virtual processor is the same as the ID of the target virtual processor, it means that the running second virtual processor is the virtual processor that needs to be interrupted. At this time, the second The logical processor performs virtual interrupt injection processing on the second virtual processor according to the virtual interrupt information. Through the hardware direct communication between the first logical processor and the second logical processor, in the embodiment of the present application, the virtual terminal injection process to the target virtual processor can be realized. The whole process does not require the access of VMM software, and the second logical processor The processor also does not need to exit virtualization mode.

In some embodiments of the present application, the communication method provided in the embodiment of the present application may further include the following steps:

When the identifier of the second virtual processor is different from the identifier of the target virtual processor, the second logical processor stores the IPI information and exits the virtualization mode.

Wherein, when the second logical processor determines that the currently running second virtual processor is not the target virtual processor, the second logical processor may store the IPI information, for example, in the receiver exception information storage area, so that the running The vmm software in non-virtualization mode can query the detailed information of IPI transmission.

In some embodiments of the present application, the communication method provided in the embodiment of the present application may further include the following steps:

After the second logical processor enters the non-virtualization mode, the second logical processor receives the IPI information sent by the first logical processor, and the IPI information includes: the identification of the target virtual processor and virtual interrupt information;

the second logical processor determines whether the identity of the second virtual processor is the same as the identity of the target virtual processor;

When the identifier of the second virtual processor is the same as the identifier of the target virtual processor, the second logical processor updates the correspondence between the second logical processor and the second virtual processor to the routing table from the virtual processor to the logical processor middle.

Wherein, after the second logical processor enters the non-virtualization mode, that is, the second logical processor is not in the virtualization mode, the second logical processor can update the corresponding relationship between the second logical processor and the second virtual processor Into the routing table from the virtual processor to the logical processor, so as to realize the dynamic update of the routing table by the logical processor.

It can be known from the examples of the foregoing embodiments that in the embodiment of the present application, the first logical processor can perform virtual processor address translation on the identification of the target virtual processor, so as to determine the target logical processor where the target virtual processor is currently running. Therefore, the first logical processor can directly send IPI information to the running target virtual processor in the virtualization mode, and the second logical processor acts as the target logical processor on which the target virtual processor runs Therefore, the second logical processor can perform IPI injection on the target virtual processor without sending the IPI information through the VMM, and the first logical processor does not need to exit the virtualization mode, so the sending party can be reduced The processor resource usage and the final transmission delay of IPI.

In order to facilitate a better understanding and implementation of the above-mentioned solutions in the embodiments of the present application, the corresponding application scenarios are exemplified below for specific description.

The technical problem that the embodiments of the present application can solve is that the virtual processors of the HVM must send IPIs through the VMM, but cannot communicate directly, which leads to problems of CPU resource occupation and final transmission delay of IPIs. In subsequent embodiments, the meanings of sending IPI and sending IPI interrupt are the same.

The main reason for "the problem of CPU resource occupation and the final transmission delay of IPI" in the process of sending IPI between virtual processors with the help of VMM is that during the process of "IPI communication with the help of VMM", the logical processor will exit the virtualization mode. The specific reasons are as follows:

1) When sending an IPI interrupt, you need to specify the logical processor number of the receiver, but the virtual processor number perceived by HVM is generally different from the logical processor number of the physical computer. If HVM uses standard IPI sending logic, IPI will was sent to the wrong logical processor;

2) If the virtual processor is allowed to directly send IPI interrupts, a malicious virtual machine may send IPI to a logical processor not used by the virtual machine, causing the system to crash or affect the normal operation of other virtual machines;

3) The logical processor cannot correctly handle the situation that "the virtual processor receiving the virtual IPI interrupt is currently not running, or even in a blocked state".

In the embodiment of the present application, the logical processor has a mechanism of "obtaining the corresponding relationship between virtual processors and logical processors". The logical processor can monitor whether the target virtual processor is running through the newly added "virtual processor address translation module" of the target logical processor without the help of VMM in virtualization mode, so as to judge whether the intervention of VMM software is needed. When the logical processor exits the virtualization mode due to the virtual processor executing the IPI sending instruction, it has a mechanism to expose the target virtual processor number and virtual IPI interrupt details to the VMM software, so that the VMM software can exit the virtualization mode when the logical processor exits the virtualization mode. After the mode is changed, the reason for the exit is obtained by querying, and then the sending process of the virtual IPI is completed by the VMM software.

It should be noted that, in the embodiment of the present application, the logical processor does not need to exit the virtualization mode when sending the IPI sending command.

The application scenario of the embodiment of the present application is a CPU of a computer system, such as an x86 processor, an ARM processor, and the like.

FIG. 4 is a schematic diagram of a basic architecture of a logic processor provided by an embodiment of the present application. The embodiment of the present application mainly optimizes the CPU hardware. As shown in Figure 4, the embodiment of the present application is aimed at the CPU hardware. In addition to the instruction processing logic module, it also includes the following modules: a virtual processor address translation module, a virtual processor interrupt transceiver module, a target matching module, and sender exception information A storage module, a receiver exception information storage module, a sender exception information query module, a receiver exception information query module, and a receiver exception report module.

Next, the functions and interrelationships of the above modules are described as follows:

Virtual processor address translation module: responsible for realizing the translation from virtual processor numbers to logical processor numbers, and its functions include maintaining and querying the correspondence table between virtual processor numbers and logical processor numbers. When the logical processor runs in the virtualization mode and cannot obtain an effective logical processor number through the virtual processor address translation module due to the execution of the IPI sending instruction, the logical processor records the details of the IPI to be sent in the sender exception information storage module, and exit virtualization mode;

Target matching module: responsible for judging whether the target recipient of the virtual interrupt injection request received by the logical processor is the currently running virtual processor;

Virtual processor interrupt transceiver module: includes two parts, the sender interface and the interrupt injection sub-module. The instruction processing logic module notifies the interrupt injection submodule of the logic processor that needs to receive the IPI interrupt by sending a request to the sender interface of the current logic processor. When the interrupt injection sub-module of the virtual processor interrupt transceiver module receives an interrupt injection request from other logical processors, if the current logical processor is in the non-virtualization mode, it will trigger the exception report module of the receiver to work. If the current logical processor is in the virtualization mode, it is determined whether to send an interrupt to the virtual processor according to the determination result of the target matching module. Alternatively, the current logical processor records the details of the received interrupt injection request in the receiver exception information storage module, and turns into a non-virtualization mode.

The abnormal information query module of the sender and the abnormal information query module of the receiver can provide support for querying IPI sending details for the VMM software running in the non-virtualization mode.

After the exception reporting module of the receiver is triggered, it executes the exception handling process registered with the logic processor by the VMM software before that.

In the logical processor described in the embodiment of the present application, when the virtual processor VP_x located in the logical processor LP_X sends an IPI interrupt to the virtual processor VP_y, the main process may include the following steps:

Step 1 mainly includes the following two situations: 1) and 2).

1) The virtual processor address translation module of the logical processor LP_X displays "the virtual processor VP_y is currently running on the logical processor LP_Y".

When the virtual processor VP_x executes the instruction "send an IPI interrupt to the virtual processor VP_y", the instruction processing logic module of LP_X obtains that VP_y is located on the effective logical processor LP_Y through its virtual processor address translation module, and the instruction processing logic The module notifies the virtual processor to interrupt the sender interface of the transceiver module to deliver the interrupt, or the virtual processor address translation module notifies the virtual processor to interrupt the sender interface of the transceiver module to deliver the interrupt. The sender interface of the logical processor LP_X sends the virtual interrupt injection request to the interrupt injection submodule of the logical processor LP_Y.

2) The virtual processor address translation module of the logical processor LP_X displays "the virtual processor VP_y is not currently running on the logical processor":

After the instruction processing logic module learns that "the virtual processor VP_y is not currently running on the logical processor" through the virtual processor address translation module, it writes the details of the instruction sent by the IPI into the exception information storage module of the sender, and the logical processor LP_X exits the virtual processor LP_X. mode. The VMM software can obtain the information that the instruction processing logic module put in the sender exception information storage module before through the sender exception information query module.

After step 1 is executed, execute step 2:

When the interrupt injection module of the logical processor LP_Y receives the interrupt injection message from other logical processors, it mainly includes the following two situations 1) and 2). :

1) The target matching module determines that "the virtual processor corresponding to the interrupt injection message is currently running".

After receiving the interrupt injection message, the interrupt injection sub-module finds that the virtual processor corresponding to the interrupt injection message is currently running through the target matching module, and then directly notifies the instruction processing logic module to inject an IPI interrupt into the current virtual processor.

2) The target matching module determines that "the virtual processor corresponding to the interrupt injection message is not currently running".

After the interrupt injection sub-module receives the interrupt injection message, it finds that the IPI interrupt should be received by the virtual processor that is not currently running on the logical processor through the target matching module, and then records the details of the interrupt injection message to the receiver's exception information storage module, and notify the instruction processing logic module to perform exception handling through the exception reporting module of the receiver. After receiving the exception report, the instruction processing logic module exits the virtualization mode if it is currently in the virtualization mode; otherwise, it directly transfers to the abnormal situation (such as interruption) processing flow. The VMM software can obtain the information that the instruction processing logic module put into the receiver exception information storage module before through the receiver exception information query module.

It should be pointed out that the virtual processor address translation module, the virtual processor interrupt transceiver module, the target matching module, the receiver exception information storage module, the sender exception information storage module, the receiver exception information query module, and the sender exception information query module The exception reporting module of the receiver is a logical module, and two or more logical processors can completely share the implementation of one or some of the logical modules, for example: logical processor LP_X and logical processor LP_Y may share virtual processing Interrupt transceiver module.

The logical processor provided in the embodiment of the present application may specifically be ARM processor hardware. As shown in FIG. 5 , it is a schematic diagram of an interaction flow between the logic processor of the sender and the logic processor of the receiver in the embodiment of the present application. After the logical processor of the IPI sender enters the virtualization mode, if the IPI sending command is obtained, it will first search for the logical processor where the target virtual processor is located, and if the valid logical processor number cannot be obtained, the IPI interrupt will be sent The information is recorded to an area accessible by the VMM software, and then the virtualization mode is exited, and the exit reason is exposed to the VMM software. When a valid logical processor can be obtained, the interrupt information transmission mechanism is used to notify the recipient logical processor to perform virtual interrupt injection, wherein the transmitted interrupt information may also include information related to the virtual interrupt. After the receiver's logic processor receives the interrupt information, it judges whether the target virtual processor is currently running through the matching logic of the target matching module, and if so, injects the virtual interrupt, otherwise it turns to exception handling.

Fig. 6 is a schematic diagram of another interaction flow between the logic processor of the sender and the logic processor of the receiver in the embodiment of the present application. It mainly includes the following processes:

Step 1: Set the interrupt number used when "delivering interrupts", for example, assume that the set interrupt number is interrupt vec. After the logical processor enters the virtualization mode, it executes the IPI to send instructions or other instructions, such as computing cpu instructions and timer instructions. Wherein, the interrupt number is used to distinguish interrupts of different virtual processors.

Step 2: If the virtualization mode is exited after executing the IPI sending command, determine the reason for the exit. If the reason is "virtual interrupt delivery in virtualization mode", use the interrupt number to continue executing the IPI interrupt sending command; if it is for other reasons, then Execute other processing logic.

Step 3: Use the interrupt number to continue to execute the IPI interrupt sending command, and judge whether the IPI delivery failed in the virtualization mode before, and if the IPI delivery fails, update the route from the virtual processor to the logical processor according to the current target logical processor information, then clear the injection failure information, and finally inject the virtual interrupt; if it is not a failure to deliver the IPI, then directly inject the virtual interrupt.

FIG. 7 is a schematic diagram of modules included in the processor socket in the embodiment of the present application. The main related modules included in the processor socket:

Each processor socket corresponds to a bitmap lp_bitmap used to indicate "the logical processor number contained in this socket".

Each logical processor corresponds to a delivery interrupt storage area pintr_info that stores <vmid, virtual processor, ntr>, where the "virtual processor" stored in the interrupt storage area is the target virtual processor number of the virtual IPI interrupt, vmid is the number of the vm where the target virtual processor is located, and intr is the relevant information contained in the delivered virtual IPI interrupt, such as the virtual IPI interrupt number and delivery method.

When running a virtual processor, each logical processor corresponds to a delivery failure storage area f_info that stores <virtual processor, vmid, intr>, where "virtual processor" is the target virtual processor number of the virtual IPI interrupt , vmid is the number of the virtual machine where the target virtual processor is located, and intr is the relevant information contained in the delivered virtual IPI interrupt, such as the virtual IPI interrupt number and delivery method. In addition, the embodiment of the present application also has a mechanism for exposing this information to the VMM software.

When running a virtual processor, each logical processor records the number of the current virtual processor and the number vmid of the VM where the current virtual processor is located.

When running virtual processors, each logical processor corresponds to a virtual processor to logical processor routing table indexed according to the virtual processor number, and the logical processor can only access its corresponding virtual processor to logical processor routing surface.

The logical processor provides the hardware interface notify_if of the receiving end of "virtual interrupt injection notification", and the receiving end and the sending end are located in the same processor socket.

The logical processor provides the setting interface failed_vec of "virtual interrupt injection notification transfer to IPI interrupt number".

The logical processor provides the hardware interface recv_if for "receiving virtual interrupt injection messages", and the receiving end and sending end are located in different processor sockets. The lpcpu where the sender of the virtual IPI is located can pass this interface, including the number of the logical processor where the receiver is located, the number of the virtual processor that receives the virtual IPI, the number of the VM where the virtual processor that receives the virtual IPI is located, and the details of the virtual IPI ( Such as interrupt number, sending method);

Each logical processor corresponds to a pintr_info arbitration logic. The input of the arbitration logic is the pintr_info request line of other logical processors in each socket and the recv_if processing logic of this logical processor. For example, for a socket with 24 logical processors Specifically, the arbitration logic of each logical processor includes 23 pintr_info request lines from other logical processors and 1 request line from the recv_if processing logic. When the pintr_info arbitration logic receives multiple pintr_info sending requests at the same time, it releases a certain pintr_info sending request in a turn-by-turn manner, so as to avoid information loss caused by multiple senders writing the pintr_info storage area at the same time.

It should be noted that there is not necessarily a one-to-one correspondence between delivery failure storage area f_info, virtual processor to physical processor (that is, logical processor) routing table, virtual processor id, vmid and logical processors. For example, for For X86 processors, f_info, virtual processor to logical processor routing table, virtual processor id, and vmid can be defined in the vmcs control structure, so that when executing different virtual processors, due to the switching of vmcs, the logical processing The processor automatically switches to a different f_info, virtual processor to logical processor routing table, virtual processor id, and vmid. In addition, the lp_bitmap corresponding to the processor socket can be automatically maintained by the logical processor when executing the "instruction for setting logical processor number", or can be maintained by system software or virtualization management software.

As shown in FIG. 8 , it is a schematic flowchart of a logical processor executing an IPI sending instruction in a virtualization mode provided by the embodiment of the present application. A processor running in virtualization mode executes the IPI interrupt sending instruction as follows:

1) If the recipient specified in the IPI interrupt sending instruction cannot be uniquely determined, go to step 11).

2) Find the logical processor lpcpu where the target virtual processor is located according to the routing table from the virtual processor to the physical processor.

3), if the lp_bitmap corresponding to the current socket does not include the lpcpu obtained in step 1), then go to step 8), if it includes the lpCPU obtained in step 1), go to step 4).

4) The instruction processing logic module sends a request to the pintr_info arbitration logic of the lpcpu, and waits for its release signal.

5), put the vmid corresponding to the current logical processor, the target virtual processor number specified by the IPI sending instruction, and the IPI interrupt details (such as interrupt number, sending method) specified by the IPI sending instruction into the delivery interrupt storage area of lpcpu pintr_info. After step 5 is executed, step 9) is executed.

6) Use notify_if to notify lpcpu to inject virtual IPI interrupt.

7) The execution of the IPI interrupt sending instruction ends.

8). If lpcpu is not a legal logical processor number, go to step 11).

9). Using recv_if, send a virtual interrupt injection message to the target lpcpu.

10). The execution of the IPI interrupt sending instruction ends.

11) Record the target virtual processor number (or a set of numbers) and the IPI interrupt details specified by the IPI sending instruction into the current delivery failure storage area f_info, and set the vmid in f_info to an invalid value.

12) Exit the virtualization mode.

As shown in FIG. 9 , it is a schematic diagram of the processing flow after the logical processor detects that there is information in notify_if in the virtualization mode provided by the embodiment of the present application. When a logical processor running in virtualization mode receives a virtual interrupt injection notification through notify_if, it executes a process including the following steps:

1), cache the pintr_info information corresponding to this logic processor in the cached_info temporary storage area;

2), if the virtual processor id corresponding to the current logical processor is not equal to the virtual processor number recorded in cached_info, or the vmid corresponding to the current logical processor is not equal to the vmid recorded in cached_info, then go to step 5);

3), according to the information recorded in cached_info, inject a virtual interrupt into the current virtual processor;

4), notify the pintr_info arbitration logic to release the next pintr_info sending request, and end the processing process;

5), according to the information in cached_info, fill in the f_info of this logical processor, and its vmid is the corresponding value in cached_info;

6) Notify the pintr_info arbitration logic to release the next pintr_info sending request, exit the virtualization operation mode, and end the processing of "virtual interrupt injection notification".

It should be noted that before running the virtual processor, the VMM uses the failed_vec interface to set notify_vector: "After the virtual interrupt injection fails, the logical processor that receives the virtual interrupt injection notification through notify_if or receives the virtual interrupt injection message through recv_if The number of the IPI interrupt received".

Next, for the two implementation scenarios of notify_if and recv_if, an example is given to illustrate the execution flow of the logical processor at the receiving end. When the logical processor running in the non-virtualization mode receives the virtual interrupt injection notification through notify_if, it executes the flow including the following steps :

1) Caching the pintr_info information corresponding to this logical processor into the cached_info temporary storage area.

2) According to the information in cached_info, fill in the f_info of this logical processor, and its vmid is the corresponding value in cached_info.

3) Notify the pintr_info arbitration logic that the next pintr_info sending request can be released.

4). Execute the interrupt handler corresponding to notify_vector.

5). End the processing of the virtual interrupt injection notification.

When the logical processor receives a virtual interrupt injection message through recv_if, it executes a process including the following steps:

1) Put the destination virtual processor number, destination vm number, and IPI interrupt details included in the message into the cached_info temporary storage area.

2) Send a request to the pintr_info arbitration logic of the destination logical processor specified in the virtual interrupt injection message, and wait for its release signal.

3) Put the information contained in the cached_info into the delivery interrupt storage area pintr_info of the lpcpu.

4) Use notify_if to notify the current logical processor to inject virtual IPI interrupts.

5). End the processing of the virtual interrupt injection message.

When a logical processor running in non-virtualization mode executes an IPI interrupt sending instruction, and finds that the execution of this instruction will cause a virtual processor to receive a virtual IPI interrupt, then in addition to executing the IPI sending instruction in a standard manner , additionally executes a process that includes the following steps:

1) If the vmid contained in the f_info information of the current logical processor is a valid value, the processing ends. Otherwise continue with the process below.

2) Obtain the logical processor number dest_cpu corresponding to the current IPI interrupt sending instruction.

3) According to the f_info information of the current logical processor, the number of the target virtual processor is obtained as dest_virtual processor.

4) Update the virtual processor of the current logical processor to the logical processor routing table, and the logical processor corresponding to the dest_virtual processor is dest_cpu.

5) The processing ends.

In the foregoing embodiments of the present application, the logical processors all include a virtual processor-to-logical processor routing table, and the virtual processor-to-logical processor routing table is transparent to the VMM software, that is, the VMM software is unaware. In the virtualization mode, when the logical processor executes the IPI sending instruction, it will translate the target virtual processor number into a logical processor number according to the routing table, and submit a virtual IPI interrupt injection notification to the translated logical processor. After the logical processor receives the virtual IPI interrupt injection notification, it injects the virtual IPI interrupt into the current virtual processor when it confirms that it is currently running the target virtual processor corresponding to the virtual IPI interrupt; in the non-virtualization mode, the logical processor When the IPI is executed to send an instruction, the corresponding entry in the routing table from the virtual processor to the logical processor will be automatically filled.

The embodiment of the present application can ensure that the logical processor can directly send an IPI interrupt to a running virtual processor in the virtualization mode, and can handle the situation that "the target virtual processor is not currently actually running".

In the embodiment of the present application, the logical processor of the sender can only obtain the logical processor where the target virtual processor is located according to the routing logic, and does not directly manipulate the interrupt description information of the target virtual processor. The advantages of this method are: 1) When the routing table is not shared globally, the embodiment of the present application can implement self-adaptive construction of the routing table. 2) During virtual interrupt delivery, there is only one information transmission channel between logical processors (that is, interrupt delivery information), so there is no need to solve the information synchronization problem that needs to be solved when transmitting multiple types of information, and the two logic processes are simplified processing between processors.

In other embodiments of the present application, the virtual processor-to-logical processor routing table of the VM is no longer a logical processor-private data structure, but a global data structure shared by all logical processors in the entire processor socket. For example, according to the hash value of <vm number, virtual processor number>, store <vm number, virtual processor number, logical processor number> in a storage area in the socket (such as in cache). When the logical processor loads and runs the virtual processor (for example, when the x86 processor loads the VMCS data structure corresponding to the virtual processor), the logical processor is based on the number of the current virtual processor, the number of the virtual machine where the current virtual processor is located, and the current logic Processor number, update the hash table. When the logical processor unloads the virtual processor (for example, when the x86 processor unloads the VMCS data structure corresponding to the virtual processor), the logical processor will process the CPU number, delete the entry corresponding to <vmid, virtual processor id> in the hash table.

In the aforementioned embodiments of the present application, the logic processor can avoid storing the virtual processor to logic processor routing table, and the routing table can be built faster.

In other embodiments of the present application, the virtual processor to logical processor routing table is stored in the memory, and when the virtual processor is running, each logical processor corresponds to a virtual processor pointer, which points to the virtual processor to the location in memory of the logical processor routing table. The virtual processor to logical processor routing table does not necessarily have a one-to-one correspondence with logical processors. For example, for X86 processors, virtual processor pointers can be defined in the vmcs structure to perform different virtual processing When the processor is switched, the logical processor automatically switches to a different virtual processor subframe due to the switching of the vmcs.

When the VP-to-LP routing table is stored in a memory area that allows the processor to cache, the processor can use its cache mechanism to quickly retrieve the VP-to-LP routing table.

When the logical processor loads and runs the virtual processor (for example, when the x86 processor loads the VMCS data structure corresponding to the virtual processor), the logical processor directly sets the virtual processor pointed to by the virtual processor pointer (ie virtual processor _rte) to the logical processor routing table. For example: if the value of the virtual processor subframe is 0x10000, and each entry in the routing table occupies 2 bytes, when the logical processor 10 is loading the virtual processor numbered 80, the logical processor 10 will use the memory 0x100a0 The 2 bytes at are set to 10.

When the logical processor unloads the virtual processor (for example, when the x86 processor unloads the VMCS data structure corresponding to the virtual processor), the logical processor directly clears the corresponding entry in the routing table from the virtual processor to the logical processor. For example: if the value of the virtual processor pointer is 0x10000, and each entry in the routing table occupies 2 bytes, when the logical processor 10 unloads the virtual processor numbered 80, the logical processor 10 will put the memory at 0x100a0 2 bytes are set to an invalid value (such as 0xffff).

In other embodiments of the present application, pintr_info includes src_cpu information, where src_cpu indicates "the logical processor number that executes the virtual IPI sending operation", for example, if the virtual processor 20 is currently running on the logical processor numbered 10 , the virtual processor 20 sends an IPI interrupt to the virtual processor 30 in the virtualization mode, the current virtual processor to the logical processor routing table indicates that "the virtual processor 30 is located on the logical processor numbered 11", and there are currently no other The logical processor sends an interrupt to the logical processor numbered 11, and the current IPI sending action of the virtual processor 20 will cause the src_cpu of the pintr_info of the logical processor numbered 11 to become 10.

As shown in FIG. 10 , it is a schematic flow diagram of a processing flow of a logical processor in a virtualization mode for a notify_if request provided by the embodiment of the present application. When a logical processor running in virtualization mode receives a virtual interrupt injection notification through notify_if, it executes a process including the following steps:

1), cache the pintr_info information corresponding to this logic processor in the cached_info temporary storage area;

2) If the virtual processor number contained in cached_info is less than 0, go to step 15). Wherein, if the number of the virtual processor is less than 0, it means that the virtual processor is illegal.

3) If the virtual processor id corresponding to the current logical processor is not equal to the virtual processor number recorded in cached_info, or the vmid corresponding to the current logical processor is not equal to the vmid recorded in cached_info, then go to step 6).

4) According to the information recorded in cached_info, a virtual interrupt is injected into the current virtual processor.

5) Notify the pintr_info arbitration logic to release the next pintr_info sending request, and complete the processing of "virtual interrupt injection notification".

6) According to the information in cached_info, fill in the f_info of this logical processor, and its vmid is the corresponding value in cached_info.

7) Obtain the src_cpu contained in cached_info.

8), if src_cpu is not located in this socket, go to step 9), otherwise go to step 11).

9) Send a recv_if message to src_cpu, and the value of the virtual processor number in cached_info contained in the message body is reversed by "bit". For example: if the processor can only support a maximum of 32767 virtual processors, when the virtual processor number in cached_info is 1, the virtual processor number in this recv_if is 0xfffe, and the vm number is the number in cached_info.

10), notify the pintr_info arbitration logic to release the next pintr_info sending request, and end the processing process.

11) Send a request to the pintr_info arbitration logic of src_cpu, and wait for its release signal.

12) Put the vmid included in cached_info and the value of the virtual processor number in cached_info inverted according to "bit" into pintr_info, the delivery interrupt storage area of src_cpu.

13) Use notify_if to notify src_cpu to inject virtual IPI interrupts.

14) Notify the pintr_info arbitration logic to release the next pintr_info sending request, exit the virtualization operation mode, and end the processing of "virtual interrupt injection notification".

15) Invert the number of the virtual processor included in the cached_info according to "bits" to obtain the real virtual processor number r virtual processor.

16), if the vmid corresponding to the current logical processor is equal to the virtual machine number specified in cached_info, then set the virtual processor used by the logical processor to the logical processor routing table, and the entry corresponding to the r virtual processor is set to Invalid value.

17) Notify the pintr_info arbitration logic to release the next pintr_info sending request, and complete the processing of the virtual interrupt injection notification.

When a logical processor running in non-virtualization mode receives a virtual interrupt injection notification through notify_if, it executes a process including the following steps:

1) Caching the pintr_info information corresponding to this logical processor into the cached_info temporary storage area.

2) If the virtual processor number contained in cached_info is less than 0, go to step 5).

3) According to the information in cached_info, fill in the f_info of this logical processor, and its vmid is the corresponding value in cached_info.

4), notify the pintr_info arbitration logic to release the next pintr_info sending request, and execute the interrupt handler corresponding to notify_vector, and end the processing of the virtual interrupt injection notification;

5) Invert the virtual processor number contained in cached_info according to "bits" to obtain the real virtual processor number r virtual processor.

6) If the vmid corresponding to the logical processor is the same as the virtual machine number specified in cached_info, set the virtual processor used by the logical processor to the logical processor routing table, and set the entry corresponding to the r virtual processor to invalid value.

7) Notify the pintr_info arbitration logic to release the next pintr_info sending request, and complete the processing of the virtual interrupt injection notification.

In other embodiments of the present application, the logical processor also provides a support mechanism (such as instructions, specific registers, etc.) for modifying the routing table from the virtual processor to the physical processor. For example, a feasible implementation manner is that when the support mechanism is triggered, the current logical processor modifies the routing table from virtual processors to physical processors accessible to itself. As another example, another feasible implementation manner is: a logical processor may use an inter-processor communication mechanism to notify other logical processors to modify the virtual processor-to-logical processor routing table.

The embodiment of the present application can give the software more freedom and facilitate the construction of the routing table from virtual processors to logical processors. Compared with the foregoing embodiments, the embodiment of the present application can implement the infrequently occurring situation of "need to notify the IPI sender to update the virtual processor to logical processor routing table" by software, thereby simplifying the hardware design of the processor.

Embodiments of the present application may include the following technical solutions:

(1) Logical processors have the mechanism of "obtaining the corresponding relationship between virtual processors and logical processors", that is, the newly added configuration of logical processors "query the logical processor number where this virtual processor is currently located according to the virtual processor number" Functions, that is, adding functions such as "virtual processor address translation module", the sender can only obtain the logical processor where the target virtual processor is located according to the routing logic, and does not directly manipulate the interrupt description information of the target virtual processor:

1. It can be a private virtual processor to logical processor routing table inside the logical processor;

2. It can be the routing table from <vm ID, virtual processor ID> shared by all logical processors in the socket to the logical processor;

3. It can be a virtual processor-to-logical processor routing table stored in memory, corresponding to each virtual machine, and the logical processor internally records the memory address of the unique routing table of this virtual machine;

4. The "virtual processor address translation module" among multiple logical processors can be shared;

5. When the routing table is not shared globally, this method can realize self-adaptive construction of the routing table (see the description of embodiment 1);

6. During virtual interrupt delivery, there is only one information transmission channel (interrupt delivery information) between logical processors.

(2) The logical processor has the ability to monitor whether the target virtual processor is running through the newly added "virtual processor address translation module" of the obtained target logical processor without the help of VMM, so as to determine whether VMM software is needed intervention:

1. If the judgment shows that the current target virtual processor is running, the sender sends the virtual IPI interrupt injection request to the target logical processor through the "send interface" sub-module of the newly added "virtual processor interrupt transceiver module". The "interrupt injection" submodule of the "virtual processor interrupt transceiver module":

When the interrupt injection submodule of the target logical processor receives an interrupt injection message from another logical processor, the newly added "target matching module" determines whether the "virtual processor corresponding to the interrupt injection message" is currently running:

1) If it is determined that it is running, the instruction processing logic module is directly notified to inject an IPI interrupt into the current virtual processor to complete the IPI interrupt pass-through;

2) If it is judged that it is not running, record the details of the interrupt injection message to the newly added "abnormal information storage module" of the receiver, and notify the instruction processing logic module to handle the exception through the newly added "abnormal report module" of the receiver. After the instruction processing logic module receives the exception report, if it is currently in the virtualization mode, it exits the virtualization mode; otherwise, it directly transfers to the abnormal situation (such as interruption) processing flow.

2. If it is determined that the current target virtual processor is not running or blocked, write the details of the IPI sending instruction into the sender exception information storage module, and exit the virtualization mode. The VMM software can obtain the information stored in the sender exception information storage module by the instruction processing logic module through the sender exception information query module.

3. The "virtual processor interrupt transceiver module" among multiple logical processors can be shared.

(3) When the logical processor exits the virtualization mode due to the execution of the IPI sending instruction by the virtual processor, referring to the above (1) (2) mechanism, the logical processor configures the "sender exception information storage/query module" newly, Functions such as "receiver exception report module" and "receiver exception information storage/query module" have the function of exposing the target virtual processor number and virtual IPI interrupt details to the VMM software, so that the VMM software can exit the virtual After the virtualization mode, query the reason for the exit, and then use the traditional mode to complete the sending process of the virtual IPI.

First of all, the embodiment of the present application solves the following problem: when sending an IPI interrupt, it is necessary to specify the logical processor number of the receiver, but the HVM cannot obtain the target processor number. If the HVM uses the standard IPI sending logic, the IPI will be sent to the wrong logical processor.

In the embodiment of this application, the logical processor has a mechanism of "obtaining the corresponding relationship between virtual processors and logical processors" through the newly added "virtual processor address translation module";

In the embodiment of the present application, the HVM can obtain the serial number of the target logical processor through the "virtual processor address translation module". The sender can only obtain the logical processor where the target virtual processor is located according to the routing logic, and does not directly manipulate the interrupt description information of the target virtual processor. The advantages of this method are: 1) When the routing table is not shared globally, this method can implement self-adaptive construction of the routing table. 2) During virtual interrupt delivery, there is only one information transmission channel (interrupt delivery information) between logical processors.

Secondly, the virtual processors in the prior art must use the VMM to send IPI interrupts. If direct sending of IPI interrupts is allowed, a malicious virtual machine may send an IPI interrupt to a logical processor not used by the virtual machine, causing the system to crash or affect other normal operation of the virtual machine;

In the embodiment of the present application, the logical processor has the newly added "virtual processor address translation module" of the obtained target logical processor to monitor whether the target virtual processor is running without the help of VMM in the virtualization mode, so as to determine whether it needs Intervention of VMM software;

In the embodiment of the present application, if the newly added "virtual processor address translation module" monitors and judges that the target virtual processor is running, a virtual IPI interrupt injection request is issued, and the newly added "target matching module" of the target logical processor determines Whether the "virtual processor corresponding to the interrupt injection message" is currently running, the direct IPI communication between the virtual processors of the HVM can be completed.

Finally, the prior art virtual processor sends an IPI interrupt by means of the VMM, which causes the logical processor to be unable to correctly handle the situation that "the virtual processor receiving the virtual IPI interrupt is currently not running or even in a blocked state";

In the embodiment of the present application, when the logical processor exits the virtualization mode because the virtual processor executes the IPI sending instruction, it has a mechanism for exposing the target virtual processor number and virtual IPI interrupt details to the VMM software;

In the embodiment of the present application, after the logical processor exits the virtualization mode, the VMM software can inquire about the exit reason, and then use the traditional mode to complete the sending process of the virtual IPI.

It should be noted that for the foregoing method embodiments, for the sake of simple description, they are expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the described action sequence. Depending on the application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification belong to preferred embodiments, and the actions and modules involved are not necessarily required by this application.

In order to facilitate better implementation of the above solutions in the embodiments of the present application, related devices for implementing the above solutions are also provided below.

The embodiment of the present application also provides a logical processor, which is specifically the aforementioned first logical processor. Please refer to FIG. 11 . The first logical processor 1100 provided in the embodiment of the present application may include: Processing module 1101, sending module 1102, wherein,

The processing module 1101 is configured to acquire processor interrupt IPI information after the first logical processor enters the virtualization mode, where the IPI information includes: an identifier of a target virtual processor and virtual interrupt information;

The processing module 1101 is further configured to perform virtual processor address translation on the identifier of the target virtual processor to obtain the target logical processor where the target virtual processor is currently running;

A sending module 1102, configured to send the IPI information to the target logical processor.

In this embodiment of the present application, a virtual processor is currently running on the first logical processor, and the virtual processor running on the first logical processor is defined as the first virtual processor. When the processor injects the IPI, the first virtual processor may use the first logical processor to send IPI information, where the IPI information includes: an identifier of the target virtual processor and virtual interrupt information. The identifier of the target virtual processor may be the number of the target virtual processor, and the virtual interrupt information may be detailed information of the virtual IPI, for example, the virtual interrupt information may include an interrupt number and an interrupt sending method.

In the embodiment of the present application, the first logical processor can realize the translation from the virtual processor number to the logical processor number, and its function includes maintaining and querying the correspondence table between the virtual processor number and the logical processor number. Therefore, after the first logical processor obtains the identifier of the target virtual processor, it may perform virtual processor address translation on the identifier of the target virtual processor to obtain the target logical processor where the target virtual processor is currently running.

In this embodiment of the application, after the first logical processor determines the target logical processor where the target virtual processor is currently running, the first logical processor can send IPI information to the target logical processor, so that the target logical processor can Perform IPI injection according to IPI information.

In some embodiments of the present application, the processing module 1101 is further configured to determine that the target virtual processor is not running on any logical processor after performing virtual processor address translation on the identification of the target virtual processor , store the IPI information, and exit the virtualization mode;

The sending module 102 is further configured to notify a virtual machine monitor VMM that the first logical processor has stored the IPI information.

Wherein, after the first logical processor performs virtual processor address translation on the identification of the target virtual processor and determines that the target virtual processor is not running on any logical processor, it means that the first logical processor cannot determine the target virtual processor. The target logical processor where the processor is currently running can store the IPI information at this time, for example, in the sender exception information storage area, so that the vmm software running in the non-virtualization mode can query the IPI sending details.

In some embodiments of the present application, the processing module 1101 is further configured to store the IPI information and exit the IPI information when the first logical processor fails to send the IPI information to the target logical processor. The virtualization mode described above;

The sending module 102 is further configured to notify the VMM that the first logic processor has stored the IPI information.

Wherein, the first logical processor may set the interrupt number used when "delivering interrupt", and execute the IPI information after the logical processor enters the virtualization mode. After exiting the virtualization mode, judge the exit reason. If the reason is "virtual interrupt delivery in virtualization mode", the VMM will use the interrupt number to continue executing the IPI interrupt information.

In some embodiments of the present application, the sending module 1102 is further configured to send the identifier of the virtual machine VM where the target virtual processor is located to the target logical processor.

Wherein, the first logical processor also needs to send the identifier of the VM where the target virtual processor is located to the target logical processor, so that the receiver can determine the VM where the target virtual processor is located.

In some embodiments of the present application, the processing module 1101 is specifically configured to perform virtual processor address translation on the identifier of the target virtual processor by querying a routing table from virtual processors to logical processors.

Wherein, when running a virtual processor on each logical processor, each logical processor corresponds to a virtual processor-to-logical processor routing table indexed according to the virtual processor number, and a logical processor can access its corresponding The routing table from the virtual processor to the logical processor, so as to complete the address translation from the virtual processor to the corresponding logical processor.

In some embodiments of the present application, the routing table from the virtual processor to the logical processor is stored in the storage area of the first logical processor; or,

The routing table from the virtual processor to the logical processor is stored in the storage area of the processor where the first logical processor is located and can be used for physical plugging; or,

The routing table from the virtual processor to the logical processor is stored in the memory.

Wherein, the processor that can be used for physical plugging refers to the aforementioned processor socket. That is, the routing table from a virtual processor to a logical processor can be stored independently by a logical processor, or it can be shared globally within the scope of the processor socket to which the logical processor belongs, or stored in memory, so that each logical processor The virtual processor can use a virtual processor pointer to read the virtual processor to logical processor routing table from this memory.

In some embodiments of the present application, the first logical processor has an interface for modifying the virtual processor-to-logical processor routing table.

Among them, the logical processor can also provide a support mechanism for modifying the routing table from the virtual processor to the logical processing. Revise. As another example, a logical processor may use an inter-processor communication mechanism to notify other logical processors to modify a routing table from a virtual processor to a logical processor, and the specific implementation manner is not limited here.

It can be seen from the examples of the foregoing embodiments that when the first logical processor enters the virtualization mode, the first logical processor acquires processor interrupt IPI information, and the IPI information includes: the target virtual processor identifier and virtual interrupt information; The logical processor performs virtual processor address translation on the identifier of the target virtual processor to obtain the target logical processor where the target virtual processor is currently running; the first logical processor sends IPI information to the target logical processor. In this embodiment of the present application, the first logical processor can perform virtual processor address translation on the identifier of the target virtual processor, so as to determine the target logical processor where the target virtual processor is currently running. Therefore, the first logical processor can In the virtualization mode, IPI information is directly sent to the running target virtual processor, so that the target virtual processor can be injected into IPI, without the need to send IPI information through the VMM, and the first logical processor does not need to exit virtualization mode, thus reducing the processor resource occupation of the sender and the final transmission delay of the IPI.

Another logical processor provided in the embodiment of the present application, the logical processor is specifically the aforementioned second logical processor, please refer to FIG. 12 , the second logical processor 1200 provided in the embodiment of the present application may include : receiving module 1201, processing module 1202, wherein,

The receiving module 1201 is configured to receive the IPI information sent by the first logical processor after the second logical processor enters the virtualization mode, where the IPI information includes: the identification of the target virtual processor and virtual interrupt information;

The processing module 1202 is configured to perform virtual interrupt injection processing on the second virtual processor according to the virtual interrupt information, and the second virtual processor is a running virtual processor after the second logical processor enters the virtual mode device.

Among them, in the embodiment of the present application, based on the communication mechanism of the processor hardware, after the first logical processor sends the IPI information, the second logical processor can receive the IPI information as the receiver, and the second logical processor can determine from the IPI information Output the identification and virtual interrupt information of the target virtual processor.

In this embodiment of the present application, the running second virtual processor is the virtual processor that needs to be injected with an interrupt, and the second logical processor performs virtual interrupt injection processing on the second virtual processor according to the virtual interrupt information. Through the hardware direct communication between the first logical processor and the second logical processor, in the embodiment of the present application, the virtual terminal injection process to the target virtual processor can be realized. The whole process does not require the access of VMM software, and the second logical processor The processor also does not need to exit virtualization mode.

In some embodiments of the present application, the processing module 1202 is further configured to store the IPI information when the identifier of the second virtual processor is different from the identifier of the target virtual processor, and exit the The virtualization mode described above.

In some embodiments of the present application, the processing module 1202 is further configured to determine whether the identifier of the second virtual processor is consistent with that of the target virtual processor after the receiving module 1201 receives the IPI information sent by the first logical processor. The identification of the device is the same;

The processing module 1202 is further configured to, when the identifier of the second virtual processor is the same as the identifier of the target virtual processor, trigger the execution of the following steps: virtualize the second virtual processor according to the virtual interrupt information Interrupt injection processing.

In this embodiment of the present application, the second logical processor judges whether the second virtual processor currently running on the second logical processor is the target virtual processor, for example, the second logical processor may determine the Whether the identifier is the same as the identifier of the target virtual processor, the second virtual processor is the running virtual processor after the second logical processor enters the virtual mode.

It can be known from the examples of the foregoing embodiments that in the embodiment of the present application, the first logical processor can perform virtual processor address translation on the identification of the target virtual processor, so as to determine the target logical processor where the target virtual processor is currently running. Therefore, the first logical processor can directly send IPI information to the running target virtual processor in the virtualization mode, and the second logical processor acts as the target logical processor on which the target virtual processor runs Therefore, the second logical processor can perform IPI injection on the target virtual processor without sending the IPI information through the VMM, and the first logical processor does not need to exit the virtualization mode, so the sending party can be reduced The processor resource usage and the final transmission delay of IPI.

It should be noted that the information interaction and execution process between the modules/units of the above-mentioned device are based on the same concept as the method embodiment of the present application, and the technical effect it brings is the same as that of the method embodiment of the present application. The specific content can be Refer to the descriptions in the foregoing method embodiments of the present application, and details are not repeated here.

The embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a program, and the program executes some or all of the steps described in the above method embodiments.

It should be noted that the processor in the embodiment of the present application may also be referred to as a central processing unit (English full name: Central Processing Unit, English abbreviation: CPU). In a specific application, various components of the processor are coupled together through a bus system. The processor can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The above-mentioned processor can be a general-purpose processor, a digital signal processor (English full name: digital signal processing, English abbreviation: DSP), an application specific integrated circuit (English full name: Application Specific Integrated Circuit, English abbreviation: ASIC), field programmable gate Array (English full name: Field-Programmable Gate Array, English abbreviation: FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. Various methods, steps, and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, or the like. The steps of the method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor.

In addition, it should be noted that the device embodiments described above are only illustrative, and the units described as separate components may or may not be physically separated, and the components shown as units may or may not be A physical unit can be located in one place, or it can be distributed to multiple network units. Part or all of the modules can be selected according to actual needs to achieve the purpose of the solution of the embodiment of the present application. In addition, in the drawings of the device embodiments provided in the present application, the connection relationship between the modules indicates that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines.

Through the above description of the implementation manners, those skilled in the art can clearly understand that the present application can be implemented by hardware, firmware, or a combination thereof. When implemented in software, the functions described above may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example but not limitation: computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage media or other magnetic storage devices, or may be used to carry or store information in the form of instructions or data structures desired program code and any other medium that can be accessed by a computer. also. Any connection can suitably be a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable , fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, wireless, and microwave are included in the fixation of the respective media. As used in this application, disk and disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disc, and blu-ray disc, where discs usually reproduce data magnetically, and discs Lasers are used to optically reproduce the data. Combinations of the above should also be included within the scope of computer-readable media.

In the above embodiments, all or part of them may be implemented by software, hardware, firmware or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product.

The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the processes or functions according to the embodiments of the present application will be generated in whole or in part. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website, computer, server, or data center Transmission to another website site, computer, server, or data center by wired (eg, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be stored by a computer, or a data storage device such as a server or a data center integrated with one or more available media. The available medium may be a magnetic medium (for example, a floppy disk, a hard disk, or a magnetic tape), an optical medium (for example, DVD), or a semiconductor medium (for example, a Solid State Disk (SSD)).

Claims (23)

1. a kind of communication means characterized by comprising

After the first logic processor enters virtualization mode, first logic processor interrupts IPI between obtaining processor Information, the IPI information include: the mark and virtual interrupt information of target virtual processor；

First logic processor carries out virtual processor address translation to the mark of the target virtual processor, obtains institute State the target logic processor where target virtual processor is currently run；

First logic processor sends the IPI information to the target logic processor.

2. the method according to claim 1, wherein the method also includes:

After first logic processor carries out virtual processor address translation to the mark of the target virtual processor, really The fixed target virtual processor is not when any one logic processor is run, described in the first logic processor storage IPI information, and exit the virtualization mode；

First logic processor described in the first logic processor notice monitor of virtual machine VMM stores the IPI information.

3. the method according to claim 1, wherein the method also includes:

When first logic processor, which sends the IPI information to the target logic processor, to fail, described first is patrolled It collects processor and stores the IPI information, and exit the virtualization mode；

First logic processor described in the first logic processor notice VMM stores the IPI information.

4. the method according to claim 1, wherein the method also includes:

First logic processor send the target virtual processor to the target logic processor where virtual machine The mark of VM.

5. method according to claim 1 to 4, which is characterized in that first logic processor is to described The mark of target virtual processor carries out virtual processor address translation, comprising:

First logic processor passes through inquiry virtual processor to the routing table of logic processor, to the destination virtual The mark of processor carries out virtual processor address translation.

6. according to the method described in claim 5, it is characterized in that, the routing table of the virtual processor to logic processor is deposited Storage is in the storage region of first logic processor；Or,

The routing table of the virtual processor to logic processor, which is stored in where first logic processor, can be used for object In the storage region for managing the processor of plug；Or,

The routing table of the virtual processor to logic processor is stored into memory.

7. according to the method described in claim 5, it is characterized in that, first logic processor has for modifying the void The interface of routing table of the quasi- processor to logic processor.

8. a kind of communication means characterized by comprising

After the second logic processor enters virtualization mode, second logic processor receives the first logic processor hair The processor sent interrupts IPI information, and the IPI information includes: the mark and virtual interrupt information of target virtual processor；

Second logic processor carries out at virtual interrupt injection the second virtual processor according to the virtual interrupt information Reason, second virtual processor is that second logic processor enters the virtual processor being currently running after Virtualization Mode.

9. according to the method described in claim 8, it is characterized in that, the method also includes:

When the mark of second virtual processor is not identical as the mark of the target virtual processor, second logic Processor stores the IPI information, and exits the virtualization mode.

10. method according to claim 8 or claim 9, which is characterized in that the method also includes:

After second logic processor receives the IPI information that the first logic processor is sent, second logic processor Determine the second virtual processor identify whether it is identical as the mark of the target virtual processor；

When the mark of second virtual processor is identical as the mark of the target virtual processor, triggering executes following step Rapid: second logic processor carries out at virtual interrupt injection the second virtual processor according to the virtual interrupt information Reason.

11. a kind of logic processor, which is characterized in that the logic processor is the first logic processor, first logic Processor includes:

Processing module interrupts IPI information, institute for after the first logic processor enters virtualization mode, obtaining processor State the mark and virtual interrupt information that IPI information includes: target virtual processor；

The processing module is also used to carry out virtual processor address translation to the mark of the target virtual processor, obtain The target virtual processor currently runs the target logic processor at place；

Sending module, for sending the IPI information to the target logic processor.

12. logic processor according to claim 11, which is characterized in that the processing module is also used to the mesh After the mark progress virtual processor address translation for marking virtual processor, determine the target virtual processor not any When one logic processor operation, the IPI information is stored, and exit the virtualization mode；

The sending module is also used to notify the first logic processor described in monitor of virtual machine VMM to store the IPI letter Breath.

13. logic processor according to claim 11, which is characterized in that the processing module is also used to when described the When one logic processor sends IPI information failure to the target logic processor, the IPI information is stored, and exit The virtualization mode；

The sending module is also used to notify the first logic processor described in VMM to store the IPI information.

14. logic processor according to claim 11, which is characterized in that the sending module is also used to the mesh Mark logic processor sends the mark of the virtual machine VM where the target virtual processor.

15. logic processor described in any one of 1 to 14 according to claim 1, which is characterized in that the processing module, tool Body is used for the routing table by inquiry virtual processor to logic processor, carries out to the mark to the target virtual processor Virtual processor address translation.

16. logic processor according to claim 15, which is characterized in that the virtual processor to logic processor Routing table is stored in the storage region of first logic processor；Or,

The routing table of the virtual processor to logic processor, which is stored in where first logic processor, can be used for object In the storage region for managing the processor of plug；Or,

The routing table of the virtual processor to logic processor is stored into memory.

17. logic processor according to claim 15, which is characterized in that first logic processor has for repairing Change the virtual processor to logic processor routing table interface.

18. a kind of logic processor, which is characterized in that the logic processor is the second logic processor, second logic Processor includes:

Receiving module, for after the second logic processor enters virtualization mode, receiving what the first logic processor was sent Processor interrupts IPI information, and the IPI information includes: the mark and virtual interrupt information of target virtual processor；

Processing module, for being carried out at virtual interrupt injection according to the virtual interrupt information to second virtual processor Reason, second virtual processor is that second logic processor enters the virtual processor being currently running after Virtualization Mode.

19. logic processor according to claim 18, which is characterized in that the processing module is also used to when described the When the mark of two virtual processors is not identical as the mark of the target virtual processor, the IPI information is stored, and exit institute State virtualization mode.

20. logic processor described in 8 or 19 according to claim 1, which is characterized in that the processing module is also used to described Receiving module receive the first logic processor send IPI information after, determine the second virtual processor identify whether and institute The mark for stating target virtual processor is identical；

The processing module is also used to mark and the mark phase of the target virtual processor when second virtual processor Meanwhile triggering and executing following steps: the second virtual processor being carried out at virtual interrupt injection according to the virtual interrupt information Reason.

21. a kind of logic processor, which is characterized in that the logic processor includes: processing module, memory module；The place Mutual communication is carried out between reason module, the memory module；

The memory module is for storing instruction；

The processing module is used to execute the described instruction in the memory module, executes such as claim 1 to 7 or right and wants Method described in asking any one of 8 to 10.

22. a kind of computer readable storage medium, including instruction, when run on a computer, so that computer executes such as Method described in any one of claim 1 to 7 or claim 8 to 10.

23. a kind of computer program product comprising instruction, when run on a computer, so that computer executes such as right It is required that 1 to 7 or the described in any item methods of claim 8 to 10.