CN110060727B - Method for testing semiconductor memory device - Google Patents
Method for testing semiconductor memory device Download PDFInfo
- Publication number
- CN110060727B CN110060727B CN201810054261.XA CN201810054261A CN110060727B CN 110060727 B CN110060727 B CN 110060727B CN 201810054261 A CN201810054261 A CN 201810054261A CN 110060727 B CN110060727 B CN 110060727B
- Authority
- CN
- China
- Prior art keywords
- voltage
- reference voltage
- resistance
- comparator
- impedance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
The embodiment of the invention discloses a detection method of a semiconductor memory device. The semiconductor memory device includes a resistance unit and a reference resistor connected in series at an impedance terminal, and the reference resistor is grounded at one end. The detection method comprises the following steps: providing a first reference voltage which is the voltage of an impedance endpoint under the condition that the resistance unit is at a desired maximum value; acquiring a first voltage of an impedance endpoint under the condition that the resistance unit is the actual maximum value; comparing the first voltage with a first reference voltage; providing a second reference voltage which is the voltage of the impedance endpoint under the condition that the resistance unit is at the expected minimum value; the first comparator obtains a second voltage of the impedance endpoint, wherein the second voltage of the impedance endpoint is the voltage of the impedance endpoint under the condition that the resistance unit is the actual minimum value; comparing the second voltage with a second reference voltage; and judging the state of the actual adjusting range of the resistance value of the resistance unit.
Description
Technical Field
The invention relates to the technical field of semiconductor storage, in particular to a detection method of a semiconductor storage device.
Background
In high-speed data transmission processes such as data transmission between a DRAM and a CPU, impedance matching becomes more and more important in order to maintain signal integrity, and thus a high-precision output port is required; wherein, DRAM is the abbreviation of Dynamic Random Access Memory, the name is DRAM, CPU is the abbreviation of Central Processing Unit, the name is CPU.
However, the output impedance of the output port varies with manufacturing processes, application environments such as voltage, temperature, and the like. Therefore, the DRAM needs to use an output port having a high precision and an impedance adjustable function, and this process of adjusting the impedance is generally called ZQ calibration (ZQ calibration), and the corresponding circuit is a ZQ calibration circuit. The judgment of the impedance endpoint (ZQ endpoint for short) state of the DRAM can only judge the situations that the ZQ endpoint is normally connected with the reference resistor, the ZQ endpoint is short-circuited to a power supply or the ground, or the ZQ endpoint is suspended due to disconnection.
Therefore, how to determine the more complicated ZQ endpoint is a technical problem that needs to be solved urgently by those skilled in the art.
The above information disclosed in the background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is known to a person of ordinary skill in the art.
Disclosure of Invention
Embodiments of the present invention provide a method for testing a semiconductor memory device, so as to at least solve the above technical problems in the prior art.
To achieve the above object, an embodiment of the present invention provides a method for testing a semiconductor memory device, the semiconductor memory device including: the resistance unit and the reference resistor are connected in series at an impedance endpoint, one end of the reference resistor is grounded, and the resistance unit is connected with a power supply;
the detection method comprises the following steps:
the first stage is as follows:
the reference voltage providing unit provides a first reference voltage to the first comparator, wherein the first reference voltage is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the expected maximum value;
the first comparator obtains a first voltage of the impedance endpoint, wherein the first voltage of the impedance endpoint is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the actual maximum value;
the first comparator compares the first voltage with the first reference voltage to obtain a first comparison result; and
and a second stage:
the reference voltage providing unit provides a second reference voltage to the first comparator, wherein the second reference voltage is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the expected minimum value;
the first comparator obtains a second voltage of the impedance endpoint, wherein the second voltage of the impedance endpoint is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the actual minimum value;
the first comparator compares the second voltage with the second reference voltage to obtain a second comparison result; and
and judging the state of the actual adjusting range of the resistance value of the resistance unit according to the first comparison result and the second comparison result.
An embodiment of the present invention further provides a method for detecting a semiconductor memory device, where the semiconductor memory device includes: the resistance unit and the reference resistor are connected in series at an impedance endpoint, one end of the reference resistor is connected with a power supply, and the resistance unit is grounded;
the detection method comprises the following steps:
the first stage is as follows: the reference voltage providing unit provides a first reference voltage to the first comparator, wherein the first reference voltage is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the expected minimum value;
the first comparator obtains a first voltage of the impedance endpoint, wherein the first voltage of the impedance endpoint is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the actual minimum value;
the first comparator compares the first voltage with the first reference voltage to obtain a first comparison result; and
and a second stage:
the reference voltage providing unit provides a second reference voltage to the first comparator, wherein the second reference voltage is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is a desired maximum value;
the first comparator obtains a second voltage of the impedance endpoint, wherein the second voltage of the impedance endpoint is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the actual maximum value;
the first comparator compares the second voltage with the second reference voltage to obtain a second comparison result; and
and judging the state of the actual adjusting range of the resistance value of the resistance unit according to the first comparison result and the second comparison result.
According to the detection method of the semiconductor memory device, provided by the embodiment of the invention, the interval where the voltage of the impedance end point is located when the resistance value of the resistance unit is between the expected minimum value and the expected maximum value is found by setting the first reference voltage and the second reference voltage, and the judgment on the state of the actual regulation range of the resistance unit can be realized by judging whether the first voltage and the second voltage are in the interval, so that conditions are provided for a circuit with accuracy requirements on the actual regulation range of the resistance unit.
The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present invention will be readily apparent by reference to the drawings and following detailed description.
Drawings
In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are therefore not to be considered limiting of its scope.
Fig. 1 is a schematic circuit connection diagram of a semiconductor memory device provided in a sensing method using an embodiment of the present invention;
FIG. 2 is a flow chart of steps of a method of testing a semiconductor memory device according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of one clock cycle of the semiconductor memory device shown in FIG. 1;
FIG. 4 is a schematic diagram of another clock cycle of the semiconductor memory device shown in FIG. 1;
fig. 5 is a circuit diagram of a reference voltage supply unit of the sensing circuit of the semiconductor memory device shown in fig. 1;
fig. 6 is a schematic diagram of a resistance unit in the semiconductor memory device shown in fig. 1;
FIG. 7 is a schematic diagram of a decode unit in the semiconductor memory device shown in FIG. 1;
fig. 8 is a circuit connection diagram of another semiconductor memory device using the sensing method of the embodiment of the present invention.
The reference numbers illustrate:
100 of the resistance units are arranged in a circuit,
200 is referenced to a resistor, and,
300 of the impedance of the end point,
400 a reference voltage supply unit for supplying a reference voltage,
410 a first output terminal of the reference voltage providing unit,
420 a second output terminal of the reference voltage providing unit,
510 a first comparator for a first one of the comparators,
511a the non-inverting input of the first comparator,
511b the inverting input of the first comparator,
512 the output of the first comparator and the second comparator,
520 of the second set of comparators is provided,
521a the non-inverting input of the second comparator,
521b the inverting input of the second comparator,
522 the output of the second comparator and the output of the second comparator,
600 of the units of the code, and,
the decoder (610) is configured to decode,
the register (620) is a register that,
711 a first pull-up resistor circuit,
712 second pull-up resistor circuits are provided,
721 a resistance circuit is pulled down by the resistor,
811 a first pull-down resistor circuit having a first pull-down resistor,
812 a second pull-down resistor circuit that,
821 a pull-up resistor circuit.
Detailed Description
In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "second" and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "second" or "third" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood according to specific situations by those skilled in the art.
In the present invention, unless otherwise expressly specified or limited, the second feature "on" or "under" the third feature may comprise the second and third features being in direct contact, or the second and third features may be in contact not directly but via another feature in between. Also, a second feature being "on," "square," and "over" a third feature includes the second feature being directly above and obliquely above the third feature, or simply means that the second feature is higher in level than the third feature. A second feature being "under," "below," and "beneath" a third feature includes the second feature being directly above and obliquely above the third feature, or simply meaning that the second feature is at a lesser level than the third feature.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, the present invention provides examples of various specific processes and materials, but those skilled in the art will recognize applications of other processes and/or use of other materials.
Example one
In one embodiment of the present invention, a method for testing a semiconductor memory device is provided, as shown in fig. 1, the semiconductor memory device includes a resistor unit 100 and a reference resistor 200, which are connected in series at an impedance terminal 300, one end of the reference resistor 200 is grounded, and the resistor unit 100 is connected to a power supply.
The semiconductor memory device further includes a reference voltage supply unit 400, a first comparator 510, and a second comparator 520.
The reference voltage providing unit 400 includes a first output terminal 410 and a second output terminal 420. The non-inverting input terminal 511a of the first comparator is connected to the impedance terminal, and the inverting input terminal 511b is connected to the first output terminal 410 of the reference voltage providing unit. The non-inverting input terminal 521a of the second comparator is connected to the impedance terminal, and the inverting input terminal 521b is connected to the second output terminal 420 of the reference voltage providing unit. The first output terminal 410 of the reference voltage providing unit is used to provide a reference voltage to the inverting input terminal 511b of the first comparator, and the second output terminal 420 of the reference voltage providing unit is used to provide a reference voltage to the inverting input terminal 521b of the second comparator.
As shown in fig. 2, the detection method includes the following steps:
step S10: the first stage is as follows:
as shown in fig. 3, the reference voltage providing unit provides a first reference voltage to the first comparator, and specifically, the first output terminal 410 of the reference voltage providing unit provides the first reference voltage to the inverting input terminal 511b of the first comparator, where the first reference voltage is a voltage of an impedance end point when the resistance value of the resistance unit is a desired maximum value;
the first comparator obtains a first voltage of the impedance endpoint, specifically, the non-inverting input terminal 511a of the first comparator obtains the first voltage of the impedance endpoint, where the first voltage of the impedance endpoint is the voltage of the impedance endpoint when the resistance value of the resistance unit is the actual maximum value;
the first comparator compares the first voltage with a first reference voltage to obtain a first comparison result; and
step S20: and a second stage:
as shown in fig. 4, the reference voltage providing unit provides a second reference voltage to the first comparator, and specifically, the first output terminal 410 of the reference voltage providing unit provides the second reference voltage to the inverting input terminal 511b of the first comparator, where the second reference voltage is a voltage of an impedance endpoint when the resistance value of the resistor unit is a desired minimum value;
the first comparator obtains a second voltage of the impedance endpoint, specifically, the non-inverting input terminal 511a of the first comparator obtains the second voltage of the impedance endpoint, where the second voltage of the impedance endpoint is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the actual minimum value;
the first comparator compares the second voltage with a second reference voltage to obtain a second comparison result; and
step S30: and judging the state of the actual adjusting range of the resistance value of the resistance unit according to the first comparison result and the second comparison result.
According to the detection method of the semiconductor memory device, the first reference voltage is set as the voltage of the impedance endpoint when the resistance value of the resistance unit is the expected maximum value, the second reference voltage is set as the voltage of the impedance endpoint when the resistance value of the resistance unit is the expected minimum value, the interval where the voltage of the impedance endpoint is located when the resistance value of the resistance unit is between the expected minimum value and the expected maximum value is found, the judgment of the state of the actual regulation range of the resistance unit can be achieved through the judgment of whether the first voltage and the second voltage are in the interval, and conditions are provided for a circuit with accuracy requirements on the actual regulation range of the resistance unit.
It should be noted that, in the detection method of the semiconductor memory device according to the embodiment of the present invention, the expressions of the first stage and the second stage are not used to describe the chronological order, and the chronological order of the first stage and the second stage may be that the first stage is performed first and then the second stage is performed, or that the second stage is performed first and then the first stage is performed.
As shown in FIG. 1, one end of the reference resistor is grounded, one end of the resistor unit is connected with the power supply, and the resistance value of the reference resistor is R0The resistance R of the resistor unit is shown, and the power supply voltage is shown as VDDAnd (4) showing.
The first stage is as follows: v for first reference voltageREF1In the representation, the number of bits in the table,
is a minimum value, RDesired MAXThe resistance of the resistance unit is the desired maximum value. The first voltage at the impedance terminal is V1It is shown that,
Vactual MAXIt is the resistance value of the resistance unit that is the actual maximum value.
In the second stage, the second reference voltage is VREF2It is shown that,
is the maximum value, RActual MINIt is the resistance value of the resistance unit that is the desired minimum value. The second voltage at the impedance terminal is V2It is shown that,
Ractual MINIt is the minimum value for which the resistance value of the resistance unit is practical.
The step of judging the state of the actual adjustment range of the resistance value of the resistance unit comprises the following steps:
when the first voltage is greater than the first reference voltage and the second voltage is less than the second reference voltage, i.e. V1>VREF1And V is2<VREF2When, substituting into the formula, then RExpected MIN<RActual MIN≤R≤RActual MAX<RDesired MAXThat is, the actual adjustment range of the resistance unit is within the preset adjustment range, which is between the expected minimum value and the expected maximum value of the resistance unit.
Further, the first stage: as shown in fig. 3, the reference voltage providing unit further provides a third reference voltage to the second comparator, and specifically, the second output terminal 420 of the reference voltage providing unit provides the third reference voltage with a voltage value V of the third reference voltage to the inverting input terminal 521b of the second comparatorREF3A voltage value V less than the first reference voltageREF1；
The second comparator obtains a first voltage of an impedance endpoint;
the first voltage V is compared by the second comparator1And a third reference voltage VREF3Obtaining a third comparison result; and
further, the step of determining the state of the actual adjustment range of the resistance value of the resistance unit includes:
when the first voltage is less than the first reference voltage and greater than the third reference voltage, i.e. V1<VREF1And V is1>VREF3When the current is detected, the reference resistor is normally connected with the impedance end point, and the actual adjusting range of the resistor unit exceeds the preset adjusting range;
when the first voltage is less than the first reference voltage and less than the third reference voltage, i.e. V1<VREF1And V is1<VREF3When the impedance is not grounded, the impedance end point is short-circuited to the ground;
when the first voltage is greater than the first reference voltage and greater than the third reference voltage, i.e. V1>VREF1And V is1>VREF3When the second voltage is less than the second reference voltage, i.e. V2<VREF2And when the current voltage is lower than the preset voltage, the actual adjusting range of the resistance unit is within the preset adjusting range.
Also, the second stage: as shown in fig. 4, the reference voltage providing unit further provides a fourth reference voltage to the second comparator, and specifically, the second output end 420 of the reference voltage providing unit provides the fourth reference voltage with a voltage value V of the fourth reference voltage to the inverting input end 521b of the second comparatorREF4A voltage value V greater than the second reference voltageREF2；
The second comparator obtains a second voltage of the impedance endpoint;
the second voltage V is compared by a second comparator2And a fourth reference voltage VREF4Obtaining a fourth comparison result; and
the step of judging the state of the actual adjustment range of the resistance value of the resistance unit comprises the following steps:
when the second voltage is greater than the second reference voltage and less than the fourth reference voltage, i.e. V2>VREF2And V is2<VREF4When the current is detected, the reference resistor is normally connected with the impedance end point, and the actual adjusting range of the resistor unit exceeds the preset adjusting range;
when the second voltage is greater than the second reference voltage and greater than the fourth reference voltage, i.e. V2>VREF2And V is2>VREF4When the impedance is detected, the impedance end point is short-circuited to a power supply or suspended;
when the second voltage is less than the second reference voltage and less than the fourth reference voltage, i.e. V2<VREF2And V is2<VREF4When the first voltage is greater than the first reference voltage, i.e. V1>VREF1And when the current voltage is lower than the preset voltage, the actual adjusting range of the resistance unit is within the preset adjusting range.
Reference resistance R of semiconductor memory device0Is preferably 240 ohms, the resistance unit is preferably 480 ohms,the preset adjusting range of the resistance unit is 480 +/-30% ohm, VREF3Take 10% VDD，VREF4Take 90% VDDAs an example. The aim of the impedance calibration circuit is to calibrate the resistance unit to an ideal value of 480 ohms as much as possible, and a range allowing floating, namely a preset adjustment range of 480 +/-30% ohms, can be provided for the resistance unit according to actual needs. By judging the actual regulating range R of the resistance value of the resistance unit RActual MIN≤R≤RActual MAXWhether the resistance value of the resistance unit R is within the preset adjusting range or not can reach or approach the ideal value as much as possible by adjusting the resistance value of the resistance unit R, and the degree of the resistance value of the resistance unit R approaching the ideal value can not meet the requirement no matter how the resistance value of the resistance unit R is adjusted.
As shown in FIG. 5, the circuit of the reference voltage providing unit is supplied with a first reference voltage VREF1Second reference voltage VREF2Third reference voltage VREF3Fourth reference voltage VREF4Will be driven from ground and supply voltage VDDFive intervals are divided into interval A, interval B, interval C, interval D and interval E. The value ranges of the third reference voltage and the fourth reference voltage can be selected according to actual needs. As an example regarding the third reference voltage and the fourth reference voltage, the third reference voltage may be 10% of the power supply voltage; the fourth reference voltage may be 90% of the supply voltage.
To compare V first1And VREF1，VREF3Size of (D), and then comparing V2And VREF2，VREF4The conditions, processes and conclusions of the detection circuit of the semiconductor memory device of the embodiment of the present invention are shown in a tabular manner in order of the sizes of the elements:
in the case where one end of the reference resistor is grounded and one end of the resistor unit is connected to a power supply as shown in fig. 1, the semiconductor memory device also has an impedance calibration circuit including a first pull-up resistor circuit 711, a second pull-up resistor circuit 712, and a pull-down resistor circuit 721; the resistance unit is a first pull-up resistor.
As for the structure of the first pull-up resistor, a structure as shown in fig. 7 may be employed. When the pull-up code zqpu <4:0> is 00000, the resistance value of the first pull-up resistor is the actual maximum value; when the pull-up code zqpu <4:0> -11111 is set, the resistance of the first pull-up resistor is the actual minimum value.
It should be noted that the structure of the first pull-up resistor circuit and the number of MON transistors are merely examples, and may be selected according to actual needs.
The sensing circuit of the semiconductor memory device according to the embodiment of the present invention, as shown in fig. 1, 3 and 4, may further include a decoding unit 600. As for the structure of the decoding unit, the structure shown in fig. 7 can be adopted as one example. The decoding unit includes a 2-4 decoder 610 and a register 620. The output 512 of the first comparator and the output 522 of the second comparator are connected to two input terminals of the decoder, respectively, and four output terminals of the decoder are connected to four input terminals of the register, respectively. The register is used for temporarily storing signals output by four output ends of the decoder in the first clock period in the register, outputting the signals together after waiting for the signals output by the four output ends of the decoder in the second clock period, and judging whether the actual regulation range of the resistor unit R is within the preset regulation range and the state of the impedance endpoint (whether the impedance endpoint is grounded, whether the impedance endpoint is short-circuited to a power supply or suspended, and whether the reference resistor and the impedance endpoint are normally connected) according to the signals output by the four output ends of the register.
Example two
An embodiment of the present invention provides a method for testing a semiconductor memory device, as shown in fig. 8, the semiconductor memory device includes: the resistance unit 100 and the reference resistor 200 are connected in series at an impedance endpoint 300, one end of the reference resistor 200 is connected with a power supply, and the resistance unit 100 is grounded;
a reference voltage providing unit 400;
a first comparator 510 having a non-inverting input terminal 511a connected to the impedance terminal, an inverting input terminal 511b connected to the first output terminal 410 of the reference voltage providing unit,
and a second comparator 520, wherein the non-inverting input terminal 521a of the second comparator is connected to the impedance terminal, and the inverting input terminal 521b is connected to the second output terminal 420 of the reference voltage providing unit.
The detection method comprises the following steps:
the first stage is as follows: the reference voltage providing unit provides a first reference voltage for the first comparator, wherein the first reference voltage is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the expected minimum value;
the first comparator obtains a first voltage of the impedance endpoint, wherein the first voltage of the impedance endpoint is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the actual minimum value;
the first comparator compares the first voltage with a first reference voltage to obtain a first comparison result; and
and a second stage: the reference voltage providing unit provides a second reference voltage to the first comparator, wherein the second reference voltage is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the expected maximum value;
the first comparator obtains a second voltage of the impedance endpoint, wherein the second voltage of the impedance endpoint is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the actual maximum value;
the first comparator compares the second voltage with a second reference voltage to obtain a second comparison result; and
and judging the state of the actual adjusting range of the resistance value of the resistance unit according to the first comparison result and the second comparison result.
According to the detection method of the semiconductor memory device, the first reference voltage is set as the voltage of the impedance endpoint when the resistance value of the resistor unit is the expected maximum value, the second reference voltage is set as the voltage of the impedance endpoint when the resistance value of the resistor unit is the expected minimum value, the interval where the voltage of the impedance endpoint is located when the resistance value of the resistor unit is between the expected minimum value and the expected maximum value is found, the judgment of the state of the actual regulation range of the resistor unit can be achieved through the judgment of whether the first voltage and the second voltage are in the interval, and conditions are provided for the accuracy of a circuit with requirements on the state of the actual regulation range of the resistor unit.
It should be noted that, in the detection method of the semiconductor memory device according to the embodiment of the present invention, the expressions of the first stage and the second stage are not used to describe the chronological order, and the chronological order of the first stage and the second stage may be the first stage of the steps and then the second stage, or the second stage and then the first stage.
As shown in FIG. 8, one end of the reference resistor is connected to the power supply, one end of the resistor unit is grounded, and the resistance value of the reference resistor is R0The resistance R of the resistor unit is shown, and the power supply voltage is shown as VDDAnd (4) showing.
The first stage is as follows: v for first reference voltageREF1In the representation, the number of bits in the table,
is a minimum value, RActual MINIt is the resistance value of the resistance unit that is the desired minimum value. The first voltage at the impedance terminal is V1It is shown that,
Ractual MINIt is the minimum value for which the resistance value of the resistance unit is practical.
And a second stage: v for the second reference voltageREF2It is shown that,
is the maximum value, RDesired MAXThe resistance of the resistance unit is the desired maximum value. The second voltage at the impedance terminal is V2It is shown that,
Ractual MAXIt is the resistance value of the resistance unit that is the actual maximum value.
The step of judging the state of the actual adjustment range of the resistance value of the resistance unit comprises the following steps:
when the first voltage is greater than the first reference voltage and the second voltage is less than the second reference voltage, i.e. V1>VREF1And V is2<VREF2When, substituting into the formula, then RExpected MIN<RActual MIN≤R≤RActual MAX<RDesired MAXThat is, the actual adjustment range of the resistance unit is within the preset adjustment range, which is between the expected minimum value and the expected maximum value of the resistance unit.
Further, the first stage: the reference voltage providing unit also provides a third reference voltage to the second comparator, and the voltage value V of the third reference voltageREF3A voltage value V less than the first reference voltageREF1；
The second comparator obtains a first voltage of an impedance endpoint;
the first voltage V is compared by the second comparatorPractice 1And a third reference voltage VREF1Obtaining a third comparison result; and
the step of further judging the state of the actual adjusting range of the resistance value of the resistance unit comprises the following steps:
when the first voltage is less than the first reference voltage and greater than the third reference voltage, i.e. V1<VREF1And V is1>VREF3When the current is detected, the reference resistor is normally connected with the impedance end point, and the actual adjusting range of the resistor unit exceeds the preset adjusting range;
when the first voltage is less than the first reference voltage and less than the third reference voltage, i.e. V1<VREF1And V is1<VREF3When the impedance is not grounded, the impedance end point is short-circuited to the ground;
when the first voltage is greater than the first reference voltage and greater than the third reference voltage, i.e. V1>VREF1And V is1>VREF3When the second voltage is less than the second reference voltage, i.e. V2<VREF2And when the current voltage is lower than the preset voltage, the actual adjusting range of the resistance unit is within the preset adjusting range.
Further, a second stage: the reference voltage providing unit also provides a fourth reference voltage to the second comparator, wherein the voltage value V of the fourth reference voltageREF4A voltage value V greater than the second reference voltageREF2；
The second comparator obtains a second voltage of the impedance endpoint;
the second voltage V is compared by a second comparator2And a fourth reference voltage VREF4Obtaining a fourth comparison result; and
the step of judging the state of the actual adjustment range of the resistance value of the resistance unit comprises the following steps:
when the second voltage is greater than the second reference voltage and less than the fourth reference voltage, i.e. V2>VREF2And V is2<VREF4When the current is detected, the reference resistor is normally connected with the impedance end point, and the actual adjusting range of the resistor unit exceeds the preset adjusting range;
when the second voltage is greater than the second reference voltage and greater than the fourth reference voltage, i.e. V2>VREF2And V is2>VREF4When the impedance is detected, the impedance end point is short-circuited to a power supply or suspended;
when the second voltage is less than the second reference voltage and less than the fourth reference voltage, i.e. V2<VREF2And V is2<VREF4When the first voltage is greater than the first reference voltage, i.e. V1>VREF1And when the current voltage is lower than the preset voltage, the actual adjusting range of the resistance unit is within the preset adjusting range.
In the case where one end of the reference resistor is connected to a power supply and one end of the resistor unit is grounded as shown in fig. 8, the semiconductor memory device also has an impedance calibration circuit including a first pull-down resistor circuit 811, a second pull-down resistor circuit 812, and a pull-up resistor circuit 821; the resistance unit is a first pull-down resistor.
The detection circuit of the semiconductor memory device according to the embodiment of the present invention, as shown in fig. 8, may further include a decoding unit 600. As for the structure of the decoding unit, the structure shown in fig. 7 can be adopted as one example. The decoding unit includes a 2-4 decoder 610 and a register 620. The output 512 of the first comparator and the output 522 of the second comparator are connected to two input terminals of the decoder, respectively, and four output terminals of the decoder are connected to four input terminals of the register, respectively. The register is used for temporarily storing signals output by four output ends of the decoder in the first clock period in the register, outputting the signals together after waiting for the signals output by the four output ends of the decoder in the second clock period, and judging whether the actual regulation range of the resistor unit R is within the preset regulation range and the state of the impedance endpoint (whether the impedance endpoint is grounded, whether the impedance endpoint is short-circuited to a power supply or suspended, and whether the reference resistor and the impedance endpoint are normally connected) according to the signals output by the four output ends of the register.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. The detection method of the semiconductor memory device is characterized in that the semiconductor memory device comprises a resistance unit and a reference resistor which are connected in series at an impedance endpoint, one end of the reference resistor is grounded, and the resistance unit is connected with a power supply; the detection method comprises the following steps:
the first stage is as follows:
the reference voltage providing unit provides a first reference voltage to the first comparator, wherein the first reference voltage is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the expected maximum value;
the first comparator obtains a first voltage of the impedance endpoint, wherein the first voltage of the impedance endpoint is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the actual maximum value;
the first comparator compares the first voltage with the first reference voltage to obtain a first comparison result; and
and a second stage:
the reference voltage providing unit provides a second reference voltage to the first comparator, wherein the second reference voltage is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the expected minimum value;
the first comparator obtains a second voltage of the impedance endpoint, wherein the second voltage of the impedance endpoint is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the actual minimum value;
the first comparator compares the second voltage with the second reference voltage to obtain a second comparison result; and
and judging the state of the actual adjusting range of the resistance value of the resistance unit according to the first comparison result and the second comparison result.
2. The method according to claim 1, wherein the step of determining the state of the actual adjustment range of the resistance value of the resistance unit includes:
when the first voltage is greater than the first reference voltage and the second voltage is less than the second reference voltage, an actual adjustment range of the resistor unit is within a preset adjustment range, and the preset adjustment range is between a minimum value expected and a maximum value expected of the resistance of the resistor unit.
3. The detection method according to claim 1, further comprising:
the first stage:
the reference voltage providing unit also provides a third reference voltage to the second comparator, wherein the voltage value of the third reference voltage is smaller than that of the first reference voltage;
the second comparator obtains the first voltage of the impedance endpoint;
comparing the first voltage with the third reference voltage by the second comparator to obtain a third comparison result; and
the step of judging the state of the actual adjustment range of the resistance value of the resistance unit comprises the following steps:
when the first voltage is smaller than the first reference voltage and larger than the third reference voltage, the reference resistor and the impedance end point are normally connected, and the actual regulation range of the resistor unit exceeds a preset regulation range;
when the first voltage is less than the first reference voltage and less than the third reference voltage, the impedance endpoint is shorted to ground;
when the first voltage is greater than the first reference voltage and greater than the third reference voltage, and the second voltage is less than the second reference voltage, the actual adjustment range of the resistance unit is within the preset adjustment range.
4. The detection method according to claim 1, 2 or 3, further comprising:
the second stage is as follows:
the reference voltage providing unit also provides a fourth reference voltage to the second comparator, wherein the voltage value of the fourth reference voltage is greater than that of the second reference voltage;
the second comparator obtains the second voltage of the impedance endpoint;
comparing the second voltage with the fourth reference voltage by the second comparator to obtain a fourth comparison result; and
the step of judging the state of the actual adjustment range of the resistance value of the resistance unit comprises the following steps:
when the second voltage is greater than the second reference voltage and less than the fourth reference voltage, the reference resistor and the impedance end point are normally connected, and the actual regulation range of the resistor unit exceeds a preset regulation range;
when the second voltage is greater than the second reference voltage and greater than the fourth reference voltage, the impedance endpoint is short-circuited to a power supply or suspended;
when the second voltage is smaller than the second reference voltage and smaller than the fourth reference voltage, and the first voltage is greater than the first reference voltage, an actual adjustment range of the resistance unit is within the preset adjustment range.
5. A method of testing a semiconductor memory device, the semiconductor memory device comprising: the resistance unit and the reference resistor are connected in series at an impedance endpoint, one end of the reference resistor is connected with a power supply, and the resistance unit is grounded;
the detection method comprises the following steps:
the first stage is as follows:
the reference voltage providing unit provides a first reference voltage to the first comparator, wherein the first reference voltage is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the expected minimum value;
the first comparator obtains a first voltage of the impedance endpoint, wherein the first voltage of the impedance endpoint is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the actual minimum value;
the first comparator compares the first voltage with the first reference voltage to obtain a first comparison result; and
and a second stage:
the reference voltage providing unit provides a second reference voltage to the first comparator, wherein the second reference voltage is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is a desired maximum value;
the first comparator obtains a second voltage of the impedance endpoint, wherein the second voltage of the impedance endpoint is the voltage of the impedance endpoint under the condition that the resistance value of the resistance unit is the actual maximum value;
the first comparator compares the second voltage with the second reference voltage to obtain a second comparison result; and
and judging the state of the actual adjusting range of the resistance value of the resistance unit according to the first comparison result and the second comparison result.
6. The method according to claim 5, wherein the step of determining the state of the actual adjustment range of the resistance value of the resistance unit comprises:
when the first voltage is greater than the first reference voltage and the second voltage is less than the second reference voltage, an actual adjustment range of the resistor unit is within a preset adjustment range, and the preset adjustment range is between a minimum value expected and a maximum value expected of the resistance of the resistor unit.
7. The detection method according to claim 5, further comprising:
the first stage:
the reference voltage providing unit also provides a third reference voltage to the second comparator, wherein the voltage value of the third reference voltage is smaller than that of the first reference voltage;
the second comparator obtains the first voltage of the impedance endpoint;
comparing the first voltage with the third reference voltage by the second comparator to obtain a third comparison result; and
the step of judging the state of the actual adjustment range of the resistance value of the resistance unit comprises the following steps:
when the first voltage is smaller than the first reference voltage and larger than the third reference voltage, the reference resistor and the impedance end point are normally connected, and the actual regulation range of the resistor unit exceeds a preset regulation range;
when the first voltage is less than the first reference voltage and less than the third reference voltage, the impedance endpoint is shorted to ground;
when the first voltage is greater than the first reference voltage and greater than the third reference voltage, and the second voltage is less than the second reference voltage, the actual adjustment range of the resistance unit is within the preset adjustment range.
8. The detection method according to claim 5, 6 or 7, further comprising:
the second stage is as follows:
the reference voltage providing unit also provides a fourth reference voltage to the second comparator, wherein the voltage value of the fourth reference voltage is greater than that of the second reference voltage;
the second comparator obtains the second voltage of the impedance endpoint;
comparing the second voltage with the fourth reference voltage by the second comparator to obtain a fourth comparison result; and
the step of judging the state of the actual adjustment range of the resistance value of the resistance unit comprises the following steps:
when the second voltage is greater than the second reference voltage and less than the fourth reference voltage, the reference resistor and the impedance end point are normally connected, and the actual regulation range of the resistor unit exceeds a preset regulation range;
when the second voltage is greater than the second reference voltage and greater than the fourth reference voltage, the impedance endpoint is short-circuited to a power supply or suspended;
when the second voltage is smaller than the second reference voltage and smaller than the fourth reference voltage, and the first voltage is greater than the first reference voltage, an actual adjustment range of the resistance unit is within the preset adjustment range.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810054261.XA CN110060727B (en) | 2018-01-19 | 2018-01-19 | Method for testing semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810054261.XA CN110060727B (en) | 2018-01-19 | 2018-01-19 | Method for testing semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110060727A CN110060727A (en) | 2019-07-26 |
| CN110060727B true CN110060727B (en) | 2021-08-10 |
Family
ID=67314955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810054261.XA Active CN110060727B (en) | 2018-01-19 | 2018-01-19 | Method for testing semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110060727B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113496719B (en) * | 2020-04-08 | 2023-06-23 | 长鑫存储技术有限公司 | Training method of semiconductor memory and related equipment |
| JP2024131669A (en) * | 2023-03-16 | 2024-09-30 | キオクシア株式会社 | Semiconductor device, semiconductor system, and method for controlling semiconductor device |
| US12254952B2 (en) * | 2023-05-16 | 2025-03-18 | Nanya Technology Corporation | Impedance adjusting circuit with connection detection function |
| CN116682476B (en) * | 2023-06-12 | 2024-10-22 | 长鑫存储技术有限公司 | Impedance calibration circuit and memory |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811059A (en) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | Reference calibration circuit of non-volatile memorizer and calibration method of reference calibration circuit |
| CN105453435A (en) * | 2014-04-01 | 2016-03-30 | 京微雅格（北京）科技有限公司 | Integrated circuit chip and impedance calibration method thereof |
| CN107102669A (en) * | 2015-12-21 | 2017-08-29 | 芯成半导体上海有限公司 | The calibration circuit of driving and on-die termination on chip |
| CN107369471A (en) * | 2016-05-12 | 2017-11-21 | 中芯国际集成电路制造(上海)有限公司 | The calibration method of memory and its reference circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7459930B2 (en) * | 2006-11-14 | 2008-12-02 | Micron Technology, Inc. | Digital calibration circuits, devices and systems including same, and methods of operation |
| KR100820783B1 (en) * | 2007-03-02 | 2008-04-11 | 주식회사 하이닉스반도체 | On-die termination with reduced mismatch |
| KR20110013704A (en) * | 2009-08-03 | 2011-02-10 | 삼성전자주식회사 | A semiconductor device including a calibration circuit and a calibration operation method thereof |
-
2018
- 2018-01-19 CN CN201810054261.XA patent/CN110060727B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103811059A (en) * | 2014-02-28 | 2014-05-21 | 北京航空航天大学 | Reference calibration circuit of non-volatile memorizer and calibration method of reference calibration circuit |
| CN105453435A (en) * | 2014-04-01 | 2016-03-30 | 京微雅格（北京）科技有限公司 | Integrated circuit chip and impedance calibration method thereof |
| CN107102669A (en) * | 2015-12-21 | 2017-08-29 | 芯成半导体上海有限公司 | The calibration circuit of driving and on-die termination on chip |
| CN107369471A (en) * | 2016-05-12 | 2017-11-21 | 中芯国际集成电路制造(上海)有限公司 | The calibration method of memory and its reference circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110060727A (en) | 2019-07-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110060727B (en) | Method for testing semiconductor memory device | |
| CN110070905B (en) | Detection circuit and detection method for semiconductor memory device | |
| US9810589B2 (en) | System and method for automatically calibrating a temperature sensor | |
| CN108511013B (en) | Driving circuit and driving method of ZQ calibration circuit | |
| US8742780B2 (en) | Semiconductor devices including design for test capabilities and semiconductor modules and test systems including such devices | |
| US7982494B2 (en) | Systems and methods for detecting terminal state and setting output driver impedance | |
| CN209803597U (en) | Control circuit for improving detection precision of NTC thermistor and electronic equipment | |
| US10268226B1 (en) | Voltage generating device and calibrating method thereof | |
| US9608632B1 (en) | Resistance calibration method and related calibration system | |
| CN102589741B (en) | A temperature detection method and device | |
| CN107764431B (en) | Chip core temperature detection circuit | |
| US9692438B2 (en) | Signal processing, amplification module, an analog to digital converter module | |
| US20120062275A1 (en) | Interface circuit | |
| US20100045338A1 (en) | Semiconductor device and data processing system including the same | |
| US7729871B2 (en) | Airflow detecting apparatus | |
| CN109994146B (en) | Detection circuit of semiconductor memory device and semiconductor memory device | |
| US9838011B2 (en) | Integrated circuit chip and its impedance calibration method | |
| CN103455078A (en) | Current-limiting circuit and current-limiting device | |
| US9536594B1 (en) | Data reception chip | |
| US9557789B2 (en) | Power control device | |
| US6897713B1 (en) | Method and apparatus for distributed voltage compensation with a voltage driver that is responsive to feedback | |
| EP3174059A1 (en) | Data reception chip | |
| US20170154654A1 (en) | Control method for data reception chip | |
| CN108667438B (en) | Bandwidth Compensable Electronic Device and Related Method | |
| US8427198B1 (en) | Reduced quantization error I/O resistor calibrator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |