CN110010495B - High-density side wall interconnection method - Google Patents
High-density side wall interconnection method Download PDFInfo
- Publication number
- CN110010495B CN110010495B CN201811596612.6A CN201811596612A CN110010495B CN 110010495 B CN110010495 B CN 110010495B CN 201811596612 A CN201811596612 A CN 201811596612A CN 110010495 B CN110010495 B CN 110010495B
- Authority
- CN
- China
- Prior art keywords
- carrier plate
- metal
- rdl
- insulating layer
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 claims description 74
- 239000002184 metal Substances 0.000 claims description 74
- 238000004519 manufacturing process Methods 0.000 claims description 23
- 238000001259 photo etching Methods 0.000 claims description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 20
- 238000009713 electroplating Methods 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 15
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 12
- 238000001312 dry etching Methods 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 12
- 238000004381 surface treatment Methods 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 239000010931 gold Substances 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 10
- 229910052709 silver Inorganic materials 0.000 claims description 10
- 239000004332 silver Substances 0.000 claims description 10
- 229910052718 tin Inorganic materials 0.000 claims description 10
- 239000011135 tin Substances 0.000 claims description 8
- 235000012431 wafers Nutrition 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 230000008020 evaporation Effects 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 6
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 6
- 239000007769 metal material Substances 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 6
- 229910052716 thallium Inorganic materials 0.000 claims description 6
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 238000005520 cutting process Methods 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229920000647 polyepoxide Polymers 0.000 claims description 3
- 239000004814 polyurethane Substances 0.000 claims description 3
- 229920002635 polyurethane Polymers 0.000 claims description 3
- 239000010453 quartz Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- 239000000463 material Substances 0.000 description 7
- 238000005034 decoration Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a high-density side wall interconnection method, which comprises the following specific processing steps of 101) processing the upper surface of a first carrier plate, 102) processing the lower surface of the first carrier plate, 103) processing the upper surface of a second carrier plate, 104) processing the lower surface of the second carrier plate and 105) interconnecting side walls; the invention provides a high-density side wall interconnection method capable of vertically placing a chip.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a high-density side wall interconnection method.
Background
For a high-frequency micro-system, the area of the antenna array is smaller and smaller, and the distance between the antennas needs to be kept within a certain specific range, so that the whole module has excellent communication capability. However, for an analog device chip such as a radio frequency chip, the area of the analog device chip cannot be reduced by the same magnification as that of a digital chip, so that a radio frequency micro system with a very high frequency will not have enough area to simultaneously place the PA/LNA, and the PA/LNA needs to be stacked or vertically placed.
For a vertically mounted chip, all metal interconnections need to be completed on the side walls of the module where the chip is located, which requires a large number of pads for soldering on the side walls of the module. The traditional process for manufacturing the bonding pad is to manufacture the bonding pad on the surface of the wafer, and the traditional process does not have the capability for manufacturing the bonding pad on the side wall of the chip or the module.
Disclosure of Invention
The invention overcomes the defects of the prior art and provides a high-density side wall interconnection method capable of vertically placing a chip.
The technical scheme of the invention is as follows:
a high-density sidewall interconnection method comprises the following steps:
101) the surface treatment step on the first carrier plate comprises the following steps: the upper surface of the first carrier plate is uniformly distributed with TSV holes through an etching process, the depth of the TSV holes is smaller than the thickness of the first carrier plate, and an insulating layer is formed on the upper surface of the first carrier plate through silicon oxide deposition, silicon nitride deposition or direct thermal oxidation; manufacturing a seed layer above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process; through metal electroplating, enabling the TSV holes to be filled with metal, densifying the metal at the temperature of 200-500 ℃ to form metal columns, and removing the metal on the upper surface of the first carrier plate through a CMP (chemical mechanical polishing) process;
manufacturing an RDL on the surface of a silicon wafer on the uppermost layer of the upper surface of the first carrier plate through photoetching and electroplating processes, depositing silicon oxide or silicon nitride on the surface to form an insulating layer, and windowing through photoetching and dry etching processes to connect the RDL with one end of the metal column; manufacturing bonding metal on the RDL through photoetching and electroplating processes to form a bonding pad;
102) the lower surface treatment step of the first carrier plate: thinning the lower surface of the first carrier plate, and exposing the other end of the metal column through grinding, wet etching and dry etching processes; depositing silicon oxide or silicon nitride on the lower surface of the first carrier plate to form an insulating layer, and windowing the surface of the insulating layer through photoetching and etching processes to expose the other end of the metal column;
manufacturing an RDL on the insulating layer on the lower surface of the first carrier plate, wherein the RDL is connected with the other end of the metal column; manufacturing a bonding metal on the RDL on the lower surface of the first carrier plate through photoetching and electroplating processes;
103) the surface treatment step on the second carrier plate comprises the following steps: arranging TSV holes in the position, corresponding to the first carrier plate, of the upper surface of the second carrier plate through an etching process, wherein the depth of each TSV hole is smaller than the thickness of the second carrier plate; forming an insulating layer on the upper surface of the second carrier plate by depositing silicon oxide and silicon nitride or directly thermally oxidizing; manufacturing a seed layer above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process; through metal electroplating, enabling the TSV holes to be filled with metal, densifying the metal at the temperature of 200-500 ℃ to form metal columns, and removing the metal on the upper surface of the second carrier plate through a CMP (chemical mechanical polishing) process; manufacturing a bonding metal on the uppermost layer of the upper surface of the second carrier plate through photoetching and electroplating processes to form a bonding pad;
104) the lower surface treatment step of the second carrier plate: thinning the lower surface of the second carrier plate, and exposing the other end of the metal column through grinding, wet etching and dry etching processes; depositing silicon oxide or silicon nitride on the lower surface of the second carrier plate to form an insulating layer, and windowing the surface of the insulating layer through photoetching and etching processes to expose the other end of the metal column; manufacturing an RDL on the insulating layer on the lower surface of the second carrier plate, wherein the RDL is connected with the other end of the metal column;
105) and a sidewall interconnection step: bonding the upper surfaces of the first carrier plate and the second carrier plate to form a carrier plate, and longitudinally cutting the carrier plate to form a single module; the side wall of the single module exposes the side face of the RDL to form a bonding pad of the carrier plate.
Furthermore, the interconnection line of the RDL is embedded in the carrier board through a damascene process.
Further, covering an insulating layer on the RDL in the step 101), the step 102) or the step 104), wherein a window is formed on the insulating layer to expose the pad, and the diameter of the pad window is 10um to 10000 um; the RDL adopts one of copper, aluminum, nickel, silver, gold and tin as a metal material; the RDL is one layer or a plurality of layers in the structure, and the thickness ranges from 10nm to 1000 um.
Furthermore, the size of the first carrier plate and the size of the second carrier plate are 4, 6, 8 or 12 inches, the thickness range is 200um to 2000um, and the materials are one of silicon wafers, glass, quartz, silicon carbide, aluminum oxide, epoxy resin and polyurethane.
Furthermore, the metal column is made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel, and the metal column has one or more layers.
Further, the bonding temperature is 200 to 500 degrees.
Further, the thickness of the insulating layer ranges from 10nm to 100 um; the thickness of the seed layer ranges from 1nm to 100 um; the seed layer is made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel; the seed layer is one or more layers.
Compared with the prior art, the invention has the advantages that: according to the invention, the multilayer bonding pads are manufactured on the side wall of the interconnecting module of the adapter plate through the TSV process and the dry etching process, so that signals on the metal surface can be exchanged with the outside through the side wall bonding pads, and the high-density interconnection requirement of vertically placing the chip is met.
Drawings
FIG. 1 is a top view of the present invention with TSV holes provided;
FIG. 2 is a cross-sectional view of the invention after electroplating of metal of FIG. 1;
FIG. 3 is a top view of the invention after electroplating of metal of FIG. 1;
FIG. 4 is a top view of the present invention after the RDL of FIG. 3 is deployed;
FIG. 5 is a cross-sectional view of the invention of FIG. 3 after the RDL has been deployed;
FIG. 6 is a bottom view of a first carrier plate with RDLs arranged on a lower surface thereof according to the present invention;
FIG. 7 is a cross-sectional view of a second carrier plate after metal plating and RDL placement in accordance with the present invention;
FIG. 8 is a top view of a second carrier plate plated with metal and having RDLs arranged in accordance with the present invention;
FIG. 9 is a left side view of the overall structure of the present invention;
fig. 10 is a cross-sectional view of the integrated structure of the invention connecting the chips.
The labels in the figure are: the structure comprises a first carrier plate 101, TSV holes 102, metal columns 103, an RDL104 and an RDL side face 105.
Detailed Description
Reference will now be made in detail to the embodiments of the present invention, wherein like or similar reference numerals refer to like or similar elements or elements of similar function throughout. The embodiments described below with reference to the drawings are exemplary only, and are not intended as limitations on the present invention.
It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Reference numerals in the various embodiments are provided for steps of the description only and are not necessarily associated in a substantially sequential manner. Different steps in each embodiment can be combined in different sequences, so that the purpose of the invention is achieved.
The invention is further described with reference to the following figures and detailed description.
As shown in fig. 1 to 10, a method for high-density sidewall interconnection specifically includes the following steps:
101) the upper surface treatment step of the first carrier 101: the TSV holes 102 are uniformly distributed on the upper surface of the first carrier 101 through photolithography and etching processes according to requirements. The depth of the TSV holes 102 is smaller than the thickness of the first carrier plate 101, the diameter range of the TSV holes 102 is 1um to 1000um, and the depth is 10um to 1000 um. Forming an insulating layer on the upper surface of the first carrier plate 101 by depositing silicon oxide, silicon nitride or direct thermal oxidation, wherein the thickness of the insulating layer is in the range of 10nm to 100 um; the seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, and the structure of the seed layer can be one layer or multiple layers. The metal material of the seed layer may be one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, etc., and when the seed layer is a multi-layer structure, each layer is made of the same material. The metal is densified at a temperature of 200 to 500 degrees to form metal pillars 103 by electroplating the metal to fill the TSV holes 102 with metal, and is more dense. The metal on the upper surface of the first carrier 101 is removed by a CMP process, so that only the filled metal remains on the upper surface of the carrier. The surface insulating layer on the first carrier 101 may be removed by a dry etching or wet etching process, or may remain.
The RDL104 is manufactured on the surface of a silicon wafer on the uppermost layer of the upper surface of the first carrier plate 101 through photoetching and electroplating processes, the process comprises the steps of depositing silicon oxide or silicon nitride on the surface to form an insulating layer, the thickness range of the insulating layer is 10nm to 1000um, and the RDL104 is connected with one end of the metal column 103 through windowing through photoetching and dry etching processes. The RDL104 includes traces and bonds, and the interconnection lines of the RDL104 are embedded in the first carrier board 101 through a damascene process. The metal material of the RDL104 may be one of copper, aluminum, nickel, silver, gold, tin, and the like. The RDL104 itself may be constructed as one or more layers, and when multiple layers are used, each layer is typically made of the same material. The overall thickness of RDL104 ranges between 10nm and 1000 um.
An insulating layer can be covered on the surface of the manufactured RDL104, a window is formed in the insulating layer to expose the position where a bonding pad needs to be manufactured, and the diameter of the window is 10um to 10000 um.
Bonding metal forming pads are manufactured on the RDL104 through photoetching and electroplating processes. The height of the bonding pad ranges from 10nm to 1000um, the metal material of the bonding pad can be one of copper, aluminum, nickel, silver, gold, tin and the like, the structure of the bonding pad can be one layer or multiple layers, and when the bonding pad is multiple layers, each layer of the bonding pad is made of the same material.
The size of the first carrier plate 101 is one of 4, 6, 8, 12 inch wafers, the thickness range is 200um to 2000um, and the silicon wafer material can be other materials including inorganic materials such as glass, quartz, silicon carbide, alumina, etc., or organic materials such as epoxy resin, polyurethane, etc., and the main function of the first carrier plate is to provide a supporting function.
102) The lower surface treatment step of the first carrier 101: thinning the lower surface of the first carrier plate 101, and exposing the other end of the metal column 103 through grinding, wet etching and dry etching processes; silicon oxide or silicon nitride is deposited on the lower surface of the first carrier 101 to form an insulating layer, and the thickness of the insulating layer ranges from 10nm to 1000 um. And (4) windowing the surface of the insulating layer through photoetching and etching processes to expose the other end of the metal column 103.
The RDL104 is formed on the insulating layer on the lower surface of the first carrier 101, and the RDL104 is connected to the other end of the metal pillar 103, and the manufacturing method is the same as the manufacturing method of the RDL104 on the upper surface of the first carrier 101. It also can cover the insulating layer on this RDL104 surface, and the position that needs the pad is exposed to the windowing on the insulating layer, and the diameter of windowing is between 10um to 10000 um. Bonding metal is manufactured on the RDL104 on the lower surface of the first carrier plate 101 through photoetching and electroplating processes to form a bonding pad, the bonding pad is the same as the bonding pad on the upper surface of the first carrier plate 101, and the height range of the bonding pad is 10nm to 1000 um.
103) The surface treatment step on the second carrier plate comprises the following steps: at the position of the upper surface of the second carrier plate corresponding to the first carrier plate 101, the TSV holes 102 are formed through an etching process, the depth of the TSV holes 102 is smaller than the thickness of the second carrier plate, the diameter range of the TSV holes 102 is 1um to 1000um, and the depth of the TSV holes 102 is 10um to 1000 um. Forming an insulating layer on the upper surface of the second carrier plate by depositing silicon oxide and silicon nitride or directly thermally oxidizing, wherein the thickness of the insulating layer is in the range of 10nm to 100 um; the seed layer is manufactured above the insulating layer through physical sputtering, magnetron sputtering or evaporation process, the thickness of the seed layer ranges from 1nm to 100um, and the structure of the seed layer can be one layer or multiple layers. The metal material of the seed layer may be one of titanium, copper, aluminum, silver, palladium, gold, thallium, tin, nickel, etc., and when the seed layer is a multi-layer structure, each layer is made of the same material. The metal is densified at a temperature of 200 to 500 degrees to form metal pillars 103 by electroplating the metal to fill the TSV holes 102 with metal, and is more dense. And removing the metal on the upper surface of the second carrier plate by a CMP process, so that only the filled metal is left on the upper surface of the carrier plate. The surface insulating layer on the first carrier 101 may be removed by a dry etching or wet etching process, or may remain. Bonding metal is manufactured on the uppermost layer of the upper surface of the second carrier plate through photoetching and electroplating processes to form a bonding pad, and the bonding pad is the same as the bonding pad on the first carrier plate 101.
104) The lower surface treatment step of the second carrier plate: thinning the lower surface of the second carrier plate, and exposing the other end of the metal column 103 through grinding, wet etching and dry etching processes; depositing silicon oxide or silicon nitride on the lower surface of the second carrier plate to form an insulating layer, and performing photoetching and etching processes to form a window on the surface of the insulating layer so as to expose the other end of the metal column 103. An RDL104 is formed on the insulating layer on the lower surface of the second carrier, and the RDL104 is connected to the other end of the metal pillar 103. The specific manufacturing process is the same as that of the first carrier 101. It can also cover the surface of this RDL104 with an insulating layer, and open a window on the insulating layer to expose the position of the required pad.
105) And a sidewall interconnection step: and bonding the first carrier plate 101 with the upper surface of the second carrier plate to form the carrier plate, wherein the bonding temperature is 200 to 500 ℃. The carrier is cut longitudinally to form a single module. The sidewalls of the single module expose the inlaid RDL side 105, forming the bond pads. Namely, the position of the carrier board to be cut is selected for longitudinal cutting, which exposes the three layers of RDL side surfaces 105 (cross sections) of the carrier board, and the side surface of the RDL104 used as a bonding pad is thickened properly, or the RDL side surface 105 is provided with an upper welding point through metal arrangement to be enlarged to be used as a bonding pad connection surface.
In conclusion, the scheme enables signals on the metal surface to be connected and exchanged with the outside through the side wall bonding pads by manufacturing the multilayer bonding pads, and the requirement of vertically placing the high-density interconnection of the chip is met.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the spirit of the present invention, and these modifications and decorations should also be regarded as being within the scope of the present invention.
Claims (1)
1. A high-density sidewall interconnection method is characterized in that the specific processing comprises the following steps:
101) the surface treatment step on the first carrier plate comprises the following steps: the upper surface of the first carrier plate is uniformly distributed with TSV holes through an etching process, the depth of the TSV holes is smaller than the thickness of the first carrier plate, and an insulating layer is formed on the upper surface of the first carrier plate through silicon oxide deposition, silicon nitride deposition or direct thermal oxidation; manufacturing a seed layer above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process; through metal electroplating, enabling the TSV holes to be filled with metal, densifying the metal at the temperature of 200-500 ℃ to form metal columns, and removing the metal on the upper surface of the first carrier plate through a CMP (chemical mechanical polishing) process;
manufacturing an RDL on the surface of a silicon wafer on the uppermost layer of the upper surface of the first carrier plate through photoetching and electroplating processes, depositing silicon oxide or silicon nitride on the surface to form an insulating layer, and windowing through photoetching and dry etching processes to connect the RDL with one end of the metal column; manufacturing bonding metal on the RDL through photoetching and electroplating processes to form a bonding pad;
102) the lower surface treatment step of the first carrier plate: thinning the lower surface of the first carrier plate, and exposing the other end of the metal column through grinding, wet etching and dry etching processes; depositing silicon oxide or silicon nitride on the lower surface of the first carrier plate to form an insulating layer, and windowing the surface of the insulating layer through photoetching and etching processes to expose the other end of the metal column;
manufacturing an RDL on the insulating layer on the lower surface of the first carrier plate, wherein the RDL is connected with the other end of the metal column; manufacturing a bonding metal on the RDL on the lower surface of the first carrier plate through photoetching and electroplating processes;
103) the surface treatment step on the second carrier plate comprises the following steps: arranging TSV holes in the position, corresponding to the first carrier plate, of the upper surface of the second carrier plate through an etching process, wherein the depth of each TSV hole is smaller than the thickness of the second carrier plate; forming an insulating layer on the upper surface of the second carrier plate by depositing silicon oxide and silicon nitride or directly thermally oxidizing; manufacturing a seed layer above the insulating layer by a physical sputtering, magnetron sputtering or evaporation process; through metal electroplating, enabling the TSV holes to be filled with metal, densifying the metal at the temperature of 200-500 ℃ to form metal columns, and removing the metal on the upper surface of the second carrier plate through a CMP (chemical mechanical polishing) process; manufacturing a bonding metal on the uppermost layer of the upper surface of the second carrier plate through photoetching and electroplating processes to form a bonding pad;
104) the lower surface treatment step of the second carrier plate: thinning the lower surface of the second carrier plate, and exposing the other end of the metal column through grinding, wet etching and dry etching processes; depositing silicon oxide or silicon nitride on the lower surface of the second carrier plate to form an insulating layer, and windowing the surface of the insulating layer through photoetching and etching processes to expose the other end of the metal column; manufacturing an RDL on the insulating layer on the lower surface of the second carrier plate, wherein the RDL is connected with the other end of the metal column;
105) and a sidewall interconnection step: bonding the upper surfaces of the first carrier plate and the second carrier plate to form a carrier plate, and longitudinally cutting the carrier plate to form a single module; the side wall of the single module exposes the side surface of the RDL on the upper surface of the first carrier plate, the side surface of the RDL on the lower surface of the upper surface of the first carrier plate and the side surface of the RDL on the lower surface of the second carrier plate to form a bonding pad of the carrier plate;
the interconnection line of the RDL is embedded in the carrier plate through a Damascus process;
covering an insulating layer on the RDL in the step 101), the step 102) or the step 104), wherein a bonding pad is exposed by a windowing on the insulating layer, and the diameter of the bonding pad windowing is 10um to 10000 um; the RDL adopts one of copper, aluminum, nickel, silver, gold and tin as a metal material; the RDL has one or more layers with the thickness ranging from 10nm to 1000 um;
the size of the first carrier plate and the size of the second carrier plate are respectively 4 inches, 6 inches, 8 inches or 12 inches, the thickness of the first carrier plate ranges from 200um to 2000um, and the first carrier plate and the second carrier plate are made of one of silicon wafers, glass, quartz, silicon carbide, aluminum oxide, epoxy resin and polyurethane;
the metal column is made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel, and has one or more layers;
the bonding temperature is 200 to 500 ℃;
the thickness of the insulating layer ranges from 10nm to 100 um; the thickness of the seed layer ranges from 1nm to 100 um; the seed layer is made of one or more of titanium, copper, aluminum, silver, palladium, gold, thallium, tin and nickel; the seed layer is one or more layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811596612.6A CN110010495B (en) | 2018-12-26 | 2018-12-26 | High-density side wall interconnection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811596612.6A CN110010495B (en) | 2018-12-26 | 2018-12-26 | High-density side wall interconnection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110010495A CN110010495A (en) | 2019-07-12 |
| CN110010495B true CN110010495B (en) | 2021-05-28 |
Family
ID=67165222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811596612.6A Active CN110010495B (en) | 2018-12-26 | 2018-12-26 | High-density side wall interconnection method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110010495B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111968961B (en) * | 2020-08-24 | 2022-08-12 | 浙江集迈科微电子有限公司 | Sidewall interconnection plate and manufacturing process thereof |
| CN113178395B (en) * | 2021-04-28 | 2023-06-13 | 浙江集迈科微电子有限公司 | Interlayer interconnection process of multi-layer stacked modules |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1194460A (en) * | 1997-03-24 | 1998-09-30 | Lg半导体株式会社 | Packaging for stacked semiconductor chip and its producing method |
| CN101465343A (en) * | 2007-12-18 | 2009-06-24 | 财团法人工业技术研究院 | Three-dimensional stack chip structure with vertical electrical self-connection and manufacturing method thereof |
| KR20090096170A (en) * | 2008-03-07 | 2009-09-10 | 주식회사 하이닉스반도체 | Stack package |
| CN101542726A (en) * | 2008-11-19 | 2009-09-23 | 香港应用科技研究院有限公司 | Semiconductor chip with through-silicon vias and side pads |
| CN106206423A (en) * | 2016-09-08 | 2016-12-07 | 华进半导体封装先导技术研发中心有限公司 | Chip package sidewall plants ball technique |
| CN108010906A (en) * | 2017-11-29 | 2018-05-08 | 上海先方半导体有限公司 | A kind of package structure of semiconductor device and method for packing |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005217268A (en) * | 2004-01-30 | 2005-08-11 | Tdk Corp | Electronic component |
| JP4934053B2 (en) * | 2005-12-09 | 2012-05-16 | スパンション エルエルシー | Semiconductor device and manufacturing method thereof |
| US20070158807A1 (en) * | 2005-12-29 | 2007-07-12 | Daoqiang Lu | Edge interconnects for die stacking |
-
2018
- 2018-12-26 CN CN201811596612.6A patent/CN110010495B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1194460A (en) * | 1997-03-24 | 1998-09-30 | Lg半导体株式会社 | Packaging for stacked semiconductor chip and its producing method |
| CN101465343A (en) * | 2007-12-18 | 2009-06-24 | 财团法人工业技术研究院 | Three-dimensional stack chip structure with vertical electrical self-connection and manufacturing method thereof |
| KR20090096170A (en) * | 2008-03-07 | 2009-09-10 | 주식회사 하이닉스반도체 | Stack package |
| CN101542726A (en) * | 2008-11-19 | 2009-09-23 | 香港应用科技研究院有限公司 | Semiconductor chip with through-silicon vias and side pads |
| CN106206423A (en) * | 2016-09-08 | 2016-12-07 | 华进半导体封装先导技术研发中心有限公司 | Chip package sidewall plants ball technique |
| CN108010906A (en) * | 2017-11-29 | 2018-05-08 | 上海先方半导体有限公司 | A kind of package structure of semiconductor device and method for packing |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110010495A (en) | 2019-07-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110010561B (en) | Radio frequency structure with stacked multilayer chips and manufacturing method thereof | |
| CN110010563B (en) | Bottom heat dissipation type radio frequency chip adapter plate packaging process | |
| CN110010548B (en) | Manufacturing method of cavity structure with bonding pad at bottom | |
| CN111653492B (en) | Method for manufacturing three-dimensional stacked radio frequency optical module | |
| CN110010574B (en) | Multilayer stacked longitudinally interconnected radio frequency structure and manufacturing method thereof | |
| CN110010490B (en) | Manufacturing process of longitudinally interconnected radio frequency cube structure | |
| CN110010547B (en) | Manufacturing method of silicon cavity structure with TSV structure at bottom | |
| CN111653489A (en) | Three-dimensional radio frequency module manufacturing method based on multilayer heat dissipation structure | |
| CN111952244B (en) | Flexible circuit board side wall interconnection process | |
| CN111952196A (en) | Groove chip embedding process | |
| CN110010500B (en) | Highly integrated radio frequency chip system-in-package process | |
| CN110010495B (en) | High-density side wall interconnection method | |
| CN111653491B (en) | Manufacturing method of three-dimensional stacked heat dissipation module aiming at radio frequency chip heat concentration point | |
| CN110010494B (en) | Method for manufacturing system-in-package interconnection structure with side wall provided with bonding pad | |
| CN110010493B (en) | Manufacturing method of interconnected inductor | |
| CN113066781B (en) | Adapter plate stacking module, three-dimensional module and stacking process | |
| CN110010504B (en) | Manufacturing process of radio frequency module with electromagnetic shielding function | |
| CN110010487B (en) | Vertical welding radio frequency chip system-in-package process | |
| CN110739227B (en) | A manufacturing method of a three-dimensional heterogeneous radio frequency module based on a three-dimensional heat dissipation structure | |
| CN110010575B (en) | Plug interconnected TSV structure and manufacturing method thereof | |
| CN110190376B (en) | Radio frequency system-in-package module with antenna combined with liquid cooling heat dissipation structure and manufacturing method thereof | |
| CN111653534B (en) | Manufacturing method of three-dimensional heterogeneous module based on graphene as heat dissipation coating | |
| CN110010475B (en) | Manufacturing process of radiating module of radio frequency chip system-in-package | |
| CN110010480B (en) | Wafer-level radio frequency chip electromagnetic shielding packaging process | |
| CN111341668A (en) | Method for embedding radio frequency chip in silicon cavity |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB03 | Change of inventor or designer information |
Inventor after: Feng Guangjian Inventor before: Feng Guangjian Inventor before: Wang Zhiyu Inventor before: Zhang Bing Inventor before: Zhou Qi Inventor before: Zhang Xun Inventor before: Yu Faxin |
|
| CB03 | Change of inventor or designer information | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200806 Address after: 313100 Workshop No. 8, North Park, Second Division of Changxing National University Science and Technology Park, Chenwang Road and Taihu Road Intersection, Changxing County Economic and Technological Development Zone, Huzhou City, Zhejiang Province Applicant after: ZHEJIANG JIMAIKE MICROELECTRONIC Co.,Ltd. Address before: 310030 Building 6, No. 3, Xiyuan Third Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province Applicant before: HANGZHOU ZHENLEI MICROWAVE TECHNOLOGY Co.,Ltd. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |