CN119997516B - Chip structure and memory - Google Patents
Chip structure and memoryInfo
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- CN119997516B CN119997516B CN202311520808.8A CN202311520808A CN119997516B CN 119997516 B CN119997516 B CN 119997516B CN 202311520808 A CN202311520808 A CN 202311520808A CN 119997516 B CN119997516 B CN 119997516B
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Abstract
The embodiment of the disclosure discloses a chip structure and a memory. The chip structure comprises a first chip and a second chip which are stacked. The first chip comprises a plurality of storage array groups arranged along a first direction, and each storage array group comprises N storage array parts arranged along a second direction. The second chip includes a plurality of first sense amplifiers and a plurality of second sense amplifiers. In each memory array group, two adjacent memory array parts are electrically connected with a corresponding first sense amplifier, and two adjacent first sense amplifiers are electrically connected with the same memory array part. The 1 st memory array part in two adjacent memory array groups is electrically connected with a corresponding second sense amplifier, the N th memory array part in two adjacent memory array groups is electrically connected with a corresponding other second sense amplifier, and the memory array parts electrically connected to different second sense amplifiers are mutually different.
Description
Technical Field
The present disclosure relates to, but is not limited to, a chip architecture and memory.
Background
With the development of semiconductor technology, the integration level of the memory is required to be higher and the performance standard is higher. Therefore, further optimization of the structure of the memory is required.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a chip structure and a memory, which can more fully utilize the area of the chip and improve the performance of the chip.
The technical scheme of the embodiment of the disclosure is realized as follows:
The embodiment of the disclosure provides a chip structure, which comprises a first chip and a second chip which are stacked, wherein the first chip comprises a plurality of storage array groups which are arranged along a first direction, each storage array group comprises N storage array parts which are arranged along a second direction, the first direction is perpendicular to the second direction, the second chip comprises a plurality of first sensing amplifiers and a plurality of second sensing amplifiers, each storage array group comprises two adjacent storage array parts which are electrically connected with a corresponding first sensing amplifier, two adjacent first sensing amplifiers which are electrically connected with one storage array part, a1 st storage array part in the two adjacent storage array groups is electrically connected with a corresponding second sensing amplifier, an N storage array part in the two adjacent storage array groups is electrically connected with a corresponding second sensing amplifier, and the two adjacent storage array parts are electrically connected with the same sensing amplifier.
In some embodiments, the 1 st one of the memory array portions in one of the memory array groups and the nth one of the memory array portions in the other of the memory array groups share the same set of row addresses.
In some embodiments, the i-th memory array part in one memory array group and the i-th memory array part in the other memory array group share a group of row addresses in every two memory array groups, wherein i is more than or equal to 2 and less than or equal to N-1.
In some embodiments, in a vertical direction, the orthographic projections of the two second sense amplifiers of the same pair of storage array groups are electrically connected and are respectively located at two opposite sides of the orthographic projections of the same pair of storage array groups along the second direction, and the first direction and the second direction are both perpendicular to the vertical direction.
In some embodiments, in the vertical direction, the orthographic projection of each of the second sense amplifiers at least partially coincides with the orthographic projections of the two storage array portions that are correspondingly connected.
In some embodiments, in the vertical direction, the orthographic projection of the two second sense amplifiers electrically connected to the same pair of the memory array groups has the same symmetry axis as the orthographic projection of the same pair of the memory array groups, and the symmetry axis extends along the second direction.
In some embodiments, each of the storage array groups further includes at least one redundant array portion located at least on one of opposite sides of the storage array group along the second direction, the orthographic projection of the second sense amplifier is at least partially coincident with the redundant array portion located on the same side in the vertical direction, and an edge of the orthographic projection of the second sense amplifier does not exceed an edge of the orthographic projection of the redundant array portion in the second direction.
In some embodiments, in a vertical direction, the front projection of the first sense amplifier is located between the front projections of the two storage array portions that are correspondingly connected, or the front projection of the first sense amplifier is located in the front projection of one of the two storage array portions that are correspondingly connected.
In some embodiments, in the vertical direction, the orthographic projection of each of the first sense amplifiers at least partially coincides with the orthographic projections of the two storage array portions that are correspondingly connected.
In some embodiments, each of the first sense amplifiers is electrically connected to the corresponding two of the memory array portions via first bit lines of equal length, and each of the second sense amplifiers is electrically connected to the corresponding two of the memory array portions via second bit lines of equal length.
The embodiment of the disclosure also provides a memory, which comprises the chip structure described in the scheme.
It can be seen that the disclosed embodiments provide a chip architecture and memory. The chip structure comprises a first chip and a second chip which are stacked. The first chip comprises a plurality of storage array groups arranged along a first direction, wherein each storage array group comprises N storage array parts arranged along a second direction, and the first direction is perpendicular to the second direction. The second chip includes a plurality of first sense amplifiers and a plurality of second sense amplifiers. In each memory array group, two adjacent memory array parts are electrically connected with a corresponding first sense amplifier, and two adjacent first sense amplifiers are electrically connected with the same memory array part. The 1 st memory array part in two adjacent memory array groups is electrically connected with a corresponding second sense amplifier, the N th memory array part in two adjacent memory array groups is electrically connected with a corresponding other second sense amplifier, and the memory array parts electrically connected to different second sense amplifiers are mutually different.
It will be appreciated that the 1 st and nth memory array portions located at the very edge of the memory array group are electrically connected to the corresponding second sense amplifiers. In this way, in the memory array part (i.e., the 1 st and the N-th memory array parts) located at the edge position, a part of the memory cells are electrically connected to the corresponding one of the first sense amplifiers, and another part of the memory cells are electrically connected to the corresponding one of the second sense amplifiers, so that unconnected memory cells in the memory array part located at the edge position are avoided, waste is avoided, and therefore, the area of the chip can be more fully utilized, and the performance of the chip is improved. Meanwhile, each first sense amplifier is electrically connected with two adjacent memory array parts nearby, and each second sense amplifier is electrically connected with two memory array parts at the edge position nearby, so that the bit line length between the sense amplifier and the corresponding memory array part is shorter, the transmission time of data in the bit line is saved, and the occupied area of the bit line to a chip is saved.
Drawings
Fig. 1 is a schematic structural diagram of a chip structure provided in an embodiment of the disclosure;
fig. 2 is a schematic diagram of a chip structure according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram III of a chip structure according to an embodiment of the disclosure;
fig. 4 is a schematic structural diagram of a chip structure according to an embodiment of the disclosure;
fig. 5 is a schematic diagram of a chip structure according to an embodiment of the disclosure;
Fig. 6 is a schematic structural diagram of a chip structure according to an embodiment of the disclosure;
fig. 7 is a schematic structural diagram seven of a chip structure provided in an embodiment of the disclosure;
fig. 8 is a schematic structural diagram eight of a chip structure provided in an embodiment of the disclosure;
fig. 9 is a schematic structural diagram of a chip structure according to an embodiment of the disclosure;
fig. 10 is a schematic structural diagram of a memory according to an embodiment of the disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
If a similar description of "first/second" appears in the application document, the following description is added, in which the terms "first/second/third" merely distinguish similar objects and do not represent a specific ordering of the objects, it being understood that "first/second/third" may, where allowed, interchange a specific order or precedence, to enable embodiments of the disclosure described herein to be practiced otherwise than as illustrated or described herein.
When a layer/element is referred to herein as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present therebetween. In addition, in one orientation, one layer/element is located "on" another layer/element, which may be located "under" the other layer/element when the orientation is reversed.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.
In the related art, an Open BL (Open bit line) architecture is adopted, and in order to ensure that two bit lines connected to a sense amplifier are symmetrical to each other, a complete memory Array chip (MAT) needs to be placed at each edge position of an Array area (Array). However, since the sense amplifier is not located at the outer side of the memory array chip at the edge position, part of the memory cells in the memory array chip at the edge position are not used, so that the waste of the chip area is caused, and the improvement of the chip integration level is not facilitated.
Fig. 1 and 2 are schematic diagrams of an alternative chip structure provided in an embodiment of the disclosure.
As shown in fig. 1, the chip structure includes a stacked first chip D1 and a second chip D2. Wherein the width of the first chip D1 and the width of the second chip D2 remain the same.
In the embodiment of the disclosure, referring to fig. 1, the first chip D1 and the second chip D2 are electrically connected through Hybrid Bonding (Hybrid Bonding), so that higher integration and performance can be achieved while chip size and power consumption are reduced. The CMOS Wafer (Wafer-on-Wafer) may be bonded to the memory array Wafer (ARRAY WAFER) by a Wafer-to-Wafer (Wafer-on-Wafer) hybrid bonding process, and then dicing is performed to cut the CMOS Wafer into the second die D2 and the memory array Wafer into the first die D1. Or the CMOS Wafer may be cut to obtain the second chip D2, the second chip D2 is bonded to the memory array Wafer through Die-on-Wafer hybrid bonding, and the memory array Wafer is cut to obtain the first chip D1.
Referring to fig. 1 and 2, the first chip D1 includes a plurality of memory Array groups 101 arranged in a first direction X, and each memory Array group 101 includes N memory Array sections (Array sections) 102 arranged in a second direction Y, wherein the first direction X is perpendicular to the second direction Y. The second chip D2 includes a plurality of first sense amplifiers 201 and a plurality of second sense amplifiers 202.
The memory Bank (Bank) may be divided into two Half banks (Half-banks) along the extending direction of the word line, and each memory array group 101 may be formed of one or a plurality of Half banks (Half-Bank) arranged along the second direction Y, and each Half Bank includes a plurality of memory array sections 102. That is, the storage capacity size of each storage array group 101 may be divided according to the need.
In the embodiment of the disclosure, with continued reference to fig. 2, on one hand, in each memory array group 101, two adjacent memory array sections 102 are electrically connected to a corresponding one of the first sense amplifiers 201, and two adjacent first sense amplifiers 201 are electrically connected to the same memory array section 102. On the other hand, the 1 st memory array section 102 in the adjacent two memory array groups 101 is electrically connected to the corresponding one of the second sense amplifiers 202, and the N-th memory array section 102 in the adjacent two memory array groups 101 is electrically connected to the corresponding other of the second sense amplifiers 202, and the memory array sections 102 electrically connected to the different second sense amplifiers 202 are different from each other. The 1 st and nth memory array portions 102 in each memory array group 101 are located at the extreme edges of the memory array group 101 in the second direction Y, respectively.
In the embodiment of the present disclosure, with continued reference to fig. 2, the sense amplifier (the first sense amplifier 201 or the second sense amplifier 202) is electrically connected to the memory cells in the memory array portion 102, so that the sense amplifier can amplify the data in the memory cells during the process of reading or writing the data in the memory cells.
Further, each sense amplifier (first sense amplifier 201 or second sense amplifier 202) may be electrically connected to an equal number of memory cells in the two memory array sections 102, respectively. That is, for the memory array sections 102 located at the non-edge position (i.e., the 2 nd to N-1 st memory array sections 102) of each memory array section 101, half of the memory cells of each memory array section 102 are electrically connected to the corresponding one of the first sense amplifiers 201, and the other half of the memory cells of each memory array section 102 are electrically connected to the corresponding other one of the first sense amplifiers 201. On the other hand, for the memory array sections 102 located at the edge position (i.e., the 1 st and nth memory array sections 102) of each memory array section 101, half of the memory cells of each memory array section 102 are electrically connected to a corresponding one of the first sense amplifiers 201, and the other half of the memory cells of each memory array section 102 are electrically connected to a corresponding one of the second sense amplifiers 202.
It will be appreciated that the 1 st and nth memory array portions 102 located at the extreme edges of the memory array group 101 are electrically connected to the corresponding second sense amplifiers 202. In this way, in the memory array portion located at the edge position (i.e., the 1 st and N-th memory array portions 102), a part of the memory cells are electrically connected to the corresponding one of the first sense amplifiers 201, and another part of the memory cells are electrically connected to the corresponding one of the second sense amplifiers 202, so that the unused memory cells in the memory array portion located at the edge position are avoided, and waste is avoided, thereby enabling more full use of the area of the chip and improving the performance of the chip.
Meanwhile, since each first sense amplifier 201 is electrically connected to adjacent two memory array sections 102 in the vicinity, each second sense amplifier 202 is electrically connected to two memory array sections 102 in the vicinity in the edge position. Thus, the bit line length between the sense amplifier and the corresponding memory array part is shorter, the transmission time of data in the bit line is saved, and the occupied area of the bit line to the chip is saved.
In some embodiments of the present disclosure, referring to fig. 3 and 4, the 1 st memory array portion in one memory array group and the nth memory array portion in the other memory array group share the same group row address in every two memory array groups U and V.
Referring to fig. 3, the row address ra_1 is decoded into a set of row addresses via the row address decoder xdec_n, and the set of row addresses may simultaneously select the nth memory array portion in the memory array group U and the 1 st memory array portion in the memory array group V, so that corresponding Word Lines (WL) in the two memory array portions may be simultaneously turned on.
Referring to fig. 4, the row address ra_2 is decoded into another group of row addresses via the row address decoder xdec_1, and this group of row addresses can simultaneously select the 1 st memory array section in the memory array group U and the nth memory array section in the memory array group V, so that the corresponding word lines in the two memory array sections can be simultaneously opened.
It will be appreciated that the 1 st memory array portion of one memory array group and the nth memory array portion of the other memory array group share the same set of row addresses in both memory array groups U and V. Therefore, the memory array groups U and V can be enabled to be activated by the word lines at the same time, namely, the two memory array groups can read and write data based on the same activation command and the same read-write command, and the read-write efficiency is improved.
It will be appreciated that each row address corresponds to a word line, and since the two memory array groups U and V share the same row address, since one word line of both memory array groups U and V will be activated when an activation command containing a row address is received, and at the same time, since the activated word line is in a memory array portion having a different position in both memory array groups U and V, the correspondingly connected second sense amplifier 202 can operate normally, so that when a read/write command is received, the charge discharged from the memory cell to the bit line is sensed and amplified based on the column address in the read/write command.
Referring to fig. 3 and 4, the memory array part located at the edge position of the two memory array groups U and V is connected to the second sense amplifier 202. Specifically, the 1 st memory array portion of the two memory array groups U and V is connected to the same second sense amplifier 202, and the corresponding N-th memory array portion of the two memory array groups U and V is connected to the same second sense amplifier 202.
It will be appreciated that the 1 st memory array portion of one memory array group and the nth memory array portion of the other memory array group share the same set of row addresses in both memory array groups U and V. In this way, the word lines of the two memory array units connected to the same second sense amplifier 202 are not turned on at the same time, that is, only one of the bit line potentials of the two memory array units connected to the second sense amplifier is changed and the other bit line potential is not changed before the second sense amplifier 202 starts to operate, thereby performing sense amplification as a reference bit line. Therefore, the method is beneficial to realizing accurate amplification of data in the storage array part positioned at the edge position, and avoids errors in the data reading and writing processes.
In some embodiments of the present disclosure, referring to fig. 5, an ith memory array section in one memory array group and an ith memory array section in another memory array group share a set of row addresses in every two memory array groups U and V, where i is equal to or greater than 2 and equal to or less than N-1.
With continued reference to fig. 5, the address decoder xdec_i decodes a set of row addresses that can simultaneously select the ith memory array section in the memory array group U and the ith memory array section in the memory array group V, so that the word lines in the two memory array sections can be simultaneously opened.
It will be appreciated that for the memory array portions located at non-edge positions (i.e., the 2 nd to N-1 st memory array portions) of the two memory array groups U and V, the memory array portions located relatively closer (i.e., the i-th memory array portion located in the same row of the two memory array groups U and V) are set to share the same group row address. Therefore, the wiring length is reduced, the transmission time of data in the wiring is saved, and the occupied area of the wiring to the chip is saved.
Meanwhile, since each first sense amplifier is connected to two adjacent memory array parts in the same memory array group, the word lines of the two memory array parts connected to the same first sense amplifier are not opened at the same time. Therefore, accurate amplification of data in the storage array part positioned at the non-edge position is realized, and errors in the data reading and writing processes are avoided.
In some embodiments of the present disclosure, referring to fig. 2 or 6, in the vertical direction Z, the orthographic projections of two second sense amplifiers 202 electrically connected to the same pair of storage array groups 101 are respectively located on opposite sides of the orthographic projections of the same pair of storage array groups 101 along the second direction Y. Wherein, the first direction X and the second direction Y are both perpendicular to the vertical direction Z.
It will be appreciated that the second sense amplifiers 202 are positioned such that the orthographic projections of two second sense amplifiers 202 electrically connected to the same pair of memory array groups 101 are respectively located on opposite sides of the orthographic projections of the same pair of memory array groups 101 in the second direction Y. In this way, the second sense amplifier 202 can be closely connected to the memory array portion 102 located at the edge position in the memory array group 101, so that the wiring length between the second sense amplifier 202 and the memory array portion 102 located at the edge position is reduced, the transmission time of data in the wiring is saved, and the occupied area of the wiring to the chip is saved.
In some embodiments of the present disclosure, referring to fig. 6, in the vertical direction Z, the orthographic projection of each second sense amplifier 202 at least partially coincides with the orthographic projections of the two storage array portions 102 that are correspondingly connected.
It will be appreciated that the second sense amplifiers 202 are positioned such that the orthographic projection of each second sense amplifier 202 at least partially coincides with the orthographic projections of the two memory array portions 102 that are correspondingly connected. In this way, the sense amplifier on the second chip can be arranged more compactly, and the integration level of the chip is improved.
In some embodiments of the present disclosure, referring to fig. 6, the orthographic projection of two second sense amplifiers 202 electrically connected to the same pair of memory array groups 101 in the vertical direction Z has the same symmetry axis as the orthographic projection of the same pair of memory array groups 101, and the symmetry axis extends in the second direction Y.
In some embodiments of the present disclosure, referring to FIG. 7, each storage array group 101 further includes at least one redundant array section 103. The redundant array portion 103 is located at least on one of opposite sides of the storage array group 101 in the second direction Y. In the vertical direction Z, the orthographic projection of the second sense amplifier 202 at least partially coincides with the redundant array portion 103 located on the same side, and in the second direction Z, the edge of the orthographic projection of the second sense amplifier 202 does not exceed the edge of the orthographic projection of the redundant array portion 103.
The redundant array portion 103 is not electrically connected to the second sense amplifier 202. The redundant array portion 103 may be a redundant design among chip designs. The sum of the number of memory array portions 102 and the number of redundant array portions 103 in the embodiments of the present disclosure may be the number of memory array portions labeled in a conventional chip design.
It will be appreciated that the second sense amplifier 202 is positioned such that the orthographic projection of the second sense amplifier 202 at least partially coincides with the redundant array portion 103 on the same side. In this way, the sense amplifier on the second chip can be arranged more compactly, and the integration level of the chip is improved.
In some embodiments of the present disclosure, referring to fig. 8, in the vertical direction Z, the orthographic projection of the first sense amplifier 201 is located between orthographic projections of the two storage array sections 102 that are correspondingly connected. Or referring to fig. 9, in the vertical direction Z, the front projection of the first sense amplifier 201 is located in the front projection of one of the two storage array sections 102 that are correspondingly connected.
In some embodiments of the present disclosure, referring to fig. 8 or 9, in the vertical direction Z, the orthographic projection of each first sense amplifier 201 at least partially coincides with the orthographic projections of the two storage array portions 102 that are correspondingly connected.
It will be appreciated that the first sense amplifier 201 is positioned such that the front projection of the first sense amplifier 201 is located between the front projections of the two correspondingly connected storage array portions 102, or such that the front projection of the first sense amplifier 201 is located in the front projection of one of the two correspondingly connected storage array portions 102. In this way, the sense amplifier on the second chip can be arranged more compactly, and the integration level of the chip is improved.
In some embodiments of the present disclosure, with continued reference to fig. 2, each first sense amplifier 201 is electrically connected to corresponding two memory array portions 102 through first bit lines (not shown) of equal length. Each of the second sense amplifiers 202 is electrically connected to the corresponding two memory array sections 102 through second bit lines (not shown) of equal length. Wherein the length of each first bit line and the length of each second bit line may be equal. In this way, the bit lines connected to both ends of each sense amplifier have equal lengths, and at the same time, the coupling capacitances on the bit lines are the same, thereby ensuring reading and writing of data.
In the embodiment of the disclosure, for each sense amplifier, the memory cell electrically connected to the first end thereof stores first data, and the memory cell electrically connected to the second end thereof stores second data, which may be the same or different. When the sense amplifier amplifies, only the memory cell electrically connected at one end is turned on, but the memory cell electrically connected at the other end is actually turned off, but the bit line electrically connected at the other end is charged to a preset potential, wherein the preset potential can be expressed as logic 0.5, i.e. between a high level (logic 1) and a low level (logic 0). In this way, one end of the sense amplifier receives a data signal (including a data signal to be written or a read data signal), and the other end is at a preset potential, so that sense amplification can be performed, and reading or writing of data can be completed.
Fig. 10 is a schematic structural diagram of a memory according to an embodiment of the present disclosure, and as shown in fig. 10, a memory 90 includes a chip structure 80. The chip structure 80 includes the structure of the previous embodiment.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.
Claims (11)
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311520808.8A CN119997516B (en) | 2023-11-13 | Chip structure and memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202311520808.8A CN119997516B (en) | 2023-11-13 | Chip structure and memory |
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| CN119997516A CN119997516A (en) | 2025-05-13 |
| CN119997516B true CN119997516B (en) | 2025-10-03 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116722008A (en) * | 2023-05-10 | 2023-09-08 | 浙江力积存储科技有限公司 | Three-dimensional memory architecture and memory |
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116722008A (en) * | 2023-05-10 | 2023-09-08 | 浙江力积存储科技有限公司 | Three-dimensional memory architecture and memory |
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