[go: up one dir, main page]

CN119965203A - Packaging structure and manufacturing method thereof - Google Patents

Packaging structure and manufacturing method thereof Download PDF

Info

Publication number
CN119965203A
CN119965203A CN202311472722.2A CN202311472722A CN119965203A CN 119965203 A CN119965203 A CN 119965203A CN 202311472722 A CN202311472722 A CN 202311472722A CN 119965203 A CN119965203 A CN 119965203A
Authority
CN
China
Prior art keywords
integrated circuit
organic
intermediaries
electrically connected
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311472722.2A
Other languages
Chinese (zh)
Inventor
刘汉诚
曾子章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unimicron Technology Corp
Original Assignee
Unimicron Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unimicron Technology Corp filed Critical Unimicron Technology Corp
Priority to CN202311472722.2A priority Critical patent/CN119965203A/en
Publication of CN119965203A publication Critical patent/CN119965203A/en
Pending legal-status Critical Current

Links

Landscapes

  • Optical Integrated Circuits (AREA)

Abstract

本发明提供一种封装结构及其制作方法。封装结构包括封装基板、专用集成电路、多个光电组件以及多个有机中介层。专用集成电路配置于封装基板上且与封装基板电性连接。光电组件彼此分离地配置于封装基板上且围绕专用集成电路。每一光电组件包括电子集成电路、光子集成电路以及多个混合接合垫。电子集成电路通过混合接合垫接合于光子集成电路上。有机中介层彼此分离地配置于封装基板上且围绕专用集成电路。光电组件通过有机中介层与封装基板电性连接。本发明的封装结构,可具有更高的密度与性能。

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a packaging substrate, a dedicated integrated circuit, a plurality of optoelectronic components and a plurality of organic interposers. The dedicated integrated circuit is arranged on the packaging substrate and electrically connected to the packaging substrate. The optoelectronic components are separately arranged on the packaging substrate and surround the dedicated integrated circuit. Each optoelectronic component includes an electronic integrated circuit, a photonic integrated circuit and a plurality of hybrid bonding pads. The electronic integrated circuit is bonded to the photonic integrated circuit through the hybrid bonding pad. The organic interposers are separately arranged on the packaging substrate and surround the dedicated integrated circuit. The optoelectronic components are electrically connected to the packaging substrate through the organic interposers. The packaging structure of the present invention can have higher density and performance.

Description

Packaging structure and manufacturing method thereof
Technical Field
The present disclosure relates to semiconductor structures and methods for fabricating the same, and more particularly, to a package structure and a method for fabricating the same.
Background
In recent years, a co-packaged optics (CPO) architecture has been developed, in which Electronic Integrated Circuits (EIC) and Photonic Integrated Circuits (PIC) are arranged side by side, with a bandwidth of 25.6T generation for a network switch (switch) produced by intel and botong. However, when the bandwidth of the network switch enters the 51.2T generation, the above packaging method cannot be satisfied, so that the optical co-packaging density encounters a bottleneck.
Disclosure of Invention
The invention is directed to a package structure with higher density and performance.
The invention also aims at a manufacturing method of the packaging structure, which is used for manufacturing the packaging structure.
According to an embodiment of the invention, a package structure includes a package substrate, an application specific integrated circuit, a plurality of optoelectronic components, and a plurality of organic intermediaries. The special integrated circuit is configured on the packaging substrate and is electrically connected with the packaging substrate. The optoelectronic components are disposed on the package substrate separately from each other and around the application specific integrated circuit. Each optoelectronic component includes an electronic integrated circuit, a photonic integrated circuit, and a plurality of hybrid bond pads. The electronic integrated circuit is bonded to the photonic integrated circuit by hybrid bond pads. The organic intermediaries are arranged on the packaging substrate separately from each other and surround the application specific integrated circuit. The photoelectric component is electrically connected with the packaging substrate through the organic medium layer.
In the package structure according to an embodiment of the present invention, each of the above-mentioned optoelectronic components further includes a fiber optic cable, and the fiber optic cable is connected to the photonic integrated circuit.
In an embodiment of the invention, each of the above-mentioned optoelectronic devices further includes an encapsulant covering the electronic integrated circuit and the photonic integrated circuit and exposing a bottom surface of the photonic integrated circuit.
In an embodiment of the present invention, the package structure further includes a plurality of conductive elements disposed between the optoelectronic device and the organic interposer. The photon integrated circuit is provided with a plurality of through silicon vias and is electrically connected with the corresponding organic medium layer through the through silicon vias and the conductive elements.
In the package structure according to the embodiment of the present invention, each of the above-described conductive members includes a bump (bump) or a copper pillar (Cu-PILLAR WITH solder bump cap) having a solder bump cap.
In the package structure according to the embodiment of the invention, the package structure further includes a plurality of first conductive members and a plurality of second conductive members. The first conductive element is configured between the application specific integrated circuit and the packaging substrate, wherein the application specific integrated circuit is electrically connected with the packaging substrate through the first conductive element. The second conductive element is arranged between the organic medium layer and the packaging substrate, wherein the organic medium layer is electrically connected with the packaging substrate through the second conductive element.
In an embodiment of the invention, the package substrate includes a connection circuit, and the first conductive member is electrically connected to the second conductive member through the connection circuit.
In an embodiment of the package structure according to the invention, each of the first conductive members and each of the second conductive members respectively include a solder ball.
In the package structure according to the embodiment of the invention, each of the organic intermediaries includes a redistribution layer structure.
In the package structure according to the embodiment of the invention, one side of the asic includes at least one of the organic intermediaries and four of the optoelectronic components.
According to an embodiment of the invention, a method for manufacturing a package structure includes the following steps. A plurality of optoelectronic components is provided. Each optoelectronic component includes an electronic integrated circuit, a photonic integrated circuit, and a plurality of hybrid bond pads. The electronic integrated circuit is bonded to the photonic integrated circuit by hybrid bond pads. A plurality of organic intermediaries is provided. The optoelectronic component is assembled on the organic interposer. The application specific integrated circuit is assembled on the package substrate, wherein the application specific integrated circuit is electrically connected with the package substrate. The organic medium layer and the photoelectric component assembled on the organic medium layer are assembled on the packaging substrate. The organic medium layer and the photoelectric component assembled on the organic medium layer surround the special integrated circuit and are electrically connected with the packaging substrate.
Based on the above, in the design of the package structure of the present invention, the electronic integrated circuit in each optoelectronic device is bonded to the photonic integrated circuit through the hybrid bonding pad, and the optoelectronic device is electrically connected to the package substrate through the organic interposer. By the design, the packaging structure of the invention can have higher density and performance.
Drawings
FIG. 1 is a schematic top view of a package structure according to an embodiment of the invention;
FIG. 2 is a schematic cross-sectional view along line I-I of FIG. 1;
FIG. 3 is a schematic cross-sectional view along line II-II of FIG. 1;
fig. 4 is a flow chart of a method of fabricating the package structure of fig. 1.
Description of the reference numerals
100, Packaging structure;
110, packaging a substrate;
112, connecting lines;
120 an application specific integrated circuit;
130, an optoelectronic assembly;
132 an electronic integrated circuit;
134 a photonic integrated circuit;
135, packaging colloid;
136, mixing the bonding pad;
138 fiber optic cable;
140 an organic interposer;
142, redistributing the lines;
144 conductive blind holes;
150, a conductive member;
160 a first conductive member;
165 a second conductive member;
A bottom surface;
s1, S2, S3 and S4 are side edges;
S10, S12, S14, S16, S20, S30, S40, S50, S52 and S60;
T is through silicon via.
Detailed Description
Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Embodiments of the invention may be understood in conjunction with the accompanying drawings, which are also considered a part of the disclosure. It should be understood that the drawings of the present invention are not drawn to scale and that virtually any enlargement or reduction of the size of the elements is possible in order to clearly demonstrate the features of the present invention.
Fig. 1 is a schematic top view of a package structure according to an embodiment of the invention. Fig. 2 is a schematic cross-sectional view along line I-I of fig. 1. Fig. 3 is a schematic cross-sectional view along line II-II of fig. 1. Fig. 4 is a flow chart of a method of fabricating the package structure of fig. 1.
Referring to fig. 1, fig. 2, and fig. 3, in the present embodiment, the package structure 100 includes a package substrate 110, an asic 120, a plurality of optoelectronic devices 130, and a plurality of organic intermediaries 140. The asic 120 is disposed on the package substrate 110 and electrically connected to the package substrate 110. The optoelectronic components 130 are disposed on the package substrate 110 separately from each other and surround the asic 120. Each optoelectronic device 130 includes an electronic integrated circuit 132, a photonic integrated circuit 134, and a plurality of hybrid bond pads 136. The electronic integrated circuit 132 is bonded to the photonic integrated circuit 134 by hybrid bond pads 136. The organic intermediaries 140 are disposed on the package substrate 110 separately from each other and surround the asic 120. The optoelectronic device 130 is electrically connected to the package substrate 110 through the organic interposer 140.
In detail, in the present embodiment, the electronic integrated circuits 132 are stacked on the photonic integrated circuits 134 through the hybrid bonding pads 136, that is, the electronic integrated circuits 132 are vertically stacked with the photonic integrated circuits 134, not arranged side by side. The photonic integrated circuit 134 is located between the electronic integrated circuit 132 and the organic interposer 140, wherein the photonic integrated circuit 134 has a plurality of through-silicon-vias T. In one embodiment, the volume of photonic integrated circuit 134 may be greater than the volume of electronic integrated circuit 132. Furthermore, each of the optoelectronic devices 130 further includes an encapsulant 135 covering the electronic integrated circuit 132 and the photonic integrated circuit 134, and exposing the bottom surface B of the photonic integrated circuit 134. That is, the encapsulant 135 encapsulates the electronic integrated circuit 132 and the photonic integrated circuit 134, exposing only the bottom surface B of the photonic integrated circuit 134 and the end of the through-silicon-via T adjacent to the organic interposer 140. In addition, each optoelectronic assembly 130 may further include a fiber optic cable 138, wherein the fiber optic cable 138 connects to the photonic integrated circuit 134. In one embodiment, the transmission speed of the optoelectronic device 130 may reach 3.2Tbps.
As shown in fig. 1 and 3, in the present embodiment, each side S1, S2, S3, S4 of the asic 120 includes at least one organic interposer 140 and four optoelectronic devices 130. That is, the four optoelectronic devices 130 are assembled on one organic interposer 140, so the package structure 100 of the present embodiment has sixteen optoelectronic devices 130 and four organic interposers 140, and the optoelectronic devices 130 surround the four sides S1, S2, S3, S4 of the dedicated body circuit 120. In one embodiment, the asic 120 may be, for example, a 51.2T switch, but not limited thereto.
Referring to fig. 2 and fig. 3, each of the organic intermediaries 140 of the present embodiment includes a redistribution layer structure, wherein the redistribution layer structure includes a plurality of redistribution lines 142 and a plurality of conductive vias 144, and the redistribution lines 142 may be electrically connected to each other through the conductive vias 144. In one embodiment, the line widths and line pitches of the redistribution lines 142 are 2 μm, i.e., the redistribution lines 142 are fine line layers.
Furthermore, the package structure 100 of the present embodiment further includes a plurality of conductive elements 150 disposed between the optoelectronic device 130 and the organic interposer 140, wherein the photonic integrated circuit 134 can be electrically connected to the corresponding organic interposer 140 through the through-silicon vias T and the conductive elements 150. In one embodiment, each conductive member 150 may be, for example, a bump or a copper pillar with a solder bump cap. In addition, the package structure 100 of the present embodiment further includes a plurality of first conductive members 160 and a plurality of second conductive members 165. The first conductive member 160 is disposed between the asic 120 and the package substrate 110, wherein the asic 120 is electrically connected to the package substrate 110 through the first conductive member 160. The second conductive member 165 is disposed between the organic interposer 140 and the package substrate 110, wherein the organic interposer 140 is electrically connected to the package substrate 110 through the second conductive member 165. In one embodiment, each of the first conductive elements 160 and each of the second conductive elements 165 may be, for example, solder balls. In addition, the package substrate 110 may include a connection line 112, and the first conductive element 160 may be electrically connected to the second conductive element 165 through the connection line 112.
In the manufacturing method, referring to fig. 2 and 4, first, step S10 provides a plurality of photonic integrated circuits 134, each of the photonic integrated circuits 134 has a plurality of through-silicon vias T, step S12 provides a plurality of electronic integrated circuits 132, step S14 provides a plurality of organic intermediaries 140, and step S16 provides an asic 120. In one embodiment, the asic 120 may be, for example, a 51.2T switch, but not limited thereto. It should be noted that the order of providing the step S10, the step S12, the step S14, and the step S16 may be adjusted according to the requirement, which is not limited herein.
Next, in step S20, the electronic integrated circuit 132 is hybrid bonded to the photonic integrated circuit 134, wherein the electronic integrated circuit 132 is bonded to the photonic integrated circuit 134 through the hybrid bond pad 136.
Next, in step S30, the electronic integrated circuit 132 and the photonic integrated circuit 134 are packaged to form the optoelectronic device 130, and the plurality of conductive elements 150 are formed on the bottom surface B of the photonic integrated circuit 134. In detail, each optoelectronic device 130 includes an electronic integrated circuit 132, a photonic integrated circuit 134, and a hybrid bond pad 136, wherein the electronic integrated circuit 132 is bonded to the photonic integrated circuit 134 through the hybrid bond pad 136. Furthermore, each of the optoelectronic devices 130 further includes an encapsulant 135 and an optical fiber cable 138. The encapsulant 135 encapsulates the electronic integrated circuit 132 and the photonic integrated circuit 134, and exposes the bottom surface B of the photonic integrated circuit 134. A fiber optic cable 138 connects photonic integrated circuit 134. In one embodiment, the transmission speed of the optoelectronic device 130 may reach 3.2Tbps.
Next, in step S40, the optoelectronic device 130 is assembled on the organic interposer 140 through the conductive element 150. The photonic integrated circuits 134 may be electrically connected to the corresponding organic interposer 140 through the through-silicon vias T and the conductive elements 150. In one embodiment, each conductive member 150 may be, for example, a bump or a copper pillar with a solder bump cap.
Then, in step S50, the first conductive element 160 is formed on the ASIC 120, and in step S52, the second conductive element 165 is formed on the organic interposer 140. It should be noted that the order of providing the step S50 and the step S52 can be adjusted according to the requirement, which is not limited herein. In one embodiment, the first conductive element 160 and the second conductive element 165 may be solder balls, respectively.
Finally, in step S60, the asic 120 is assembled on the package substrate 110 through the first conductive member 160, and the organic interposer 140 is assembled on the package substrate 110 through the second conductive member 165. The asic 120 may be electrically connected to the package substrate 110 through the first conductive member 160, and the organic interposer 140 and the optoelectronic device 130 mounted thereon surround the asic 120 and are electrically connected to the package substrate 110 through the second conductive member 165. Thus, the fabrication of the package structure 100 is completed.
In summary, in the design of the package structure of the present invention, the electronic integrated circuit of each optoelectronic device is bonded to the photonic integrated circuit through the hybrid bonding pad, and the optoelectronic device is electrically connected to the package substrate through the organic interposer. By the design, the packaging structure of the invention can have higher density and performance.
It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.

Claims (11)

1. A package structure, comprising:
Packaging a substrate;
The special integrated circuit is configured on the packaging substrate and is electrically connected with the packaging substrate;
A plurality of optoelectronic components disposed on the package substrate separately from each other and surrounding the application specific integrated circuit, wherein each of the plurality of optoelectronic components includes an electronic integrated circuit, a photonic integrated circuit, and a plurality of hybrid bond pads, the electronic integrated circuit being bonded to the photonic integrated circuit through the plurality of hybrid bond pads, and
And a plurality of organic intermediaries which are arranged on the packaging substrate in a separated way and surround the application specific integrated circuit, wherein the plurality of photoelectric components are electrically connected with the packaging substrate through the plurality of organic intermediaries.
2. The package structure of claim 1, wherein each of the plurality of optoelectronic components further comprises a fiber optic cable, and wherein the fiber optic cable connects the photonic integrated circuit.
3. The package structure of claim 1, wherein each of the plurality of optoelectronic components further comprises an encapsulant encapsulating the electronic integrated circuit and the photonic integrated circuit and exposing a bottom surface of the photonic integrated circuit.
4. The package structure of claim 1, further comprising:
A plurality of conductive elements disposed between the plurality of optoelectronic components and the plurality of organic intermediaries, wherein the photonic integrated circuit has a plurality of through-silicon vias, and the photonic integrated circuit is electrically connected with each of the corresponding plurality of organic intermediaries through the plurality of through-silicon vias and the plurality of conductive elements.
5. The package structure of claim 4, wherein each of the plurality of conductive members comprises a bump or a copper pillar with a solder bump cap.
6. The package structure of claim 1, further comprising:
A plurality of first conductive members disposed between the ASIC and the package substrate, wherein the ASIC is electrically connected to the package substrate via the plurality of first conductive members, and
The plurality of second conductive elements are arranged between the plurality of organic intermediaries and the packaging substrate, wherein the plurality of organic intermediaries are electrically connected with the packaging substrate through the plurality of second conductive elements.
7. The package structure of claim 6, wherein the package substrate includes a connection circuit, and the plurality of first conductive members are electrically connected to the plurality of second conductive members through the connection circuit.
8. The package structure of claim 6, wherein each of the plurality of first conductive members and each of the plurality of second conductive members respectively comprise solder balls.
9. The package structure of claim 1, wherein each of the plurality of organic intermediaries comprises a redistribution layer structure.
10. The package structure of claim 1, wherein a side of the asic includes at least one of the plurality of organic intermediaries and four of the plurality of optoelectronic components.
11. The manufacturing method of the packaging structure is characterized by comprising the following steps:
Providing a plurality of optoelectronic components, each of the plurality of optoelectronic components comprising an electronic integrated circuit, a photonic integrated circuit, and a plurality of hybrid bond pads, the electronic integrated circuit being bonded to the photonic integrated circuit by the plurality of hybrid bond pads;
Providing a plurality of organic intermediaries;
Assembling the plurality of optoelectronic components on the plurality of organic intermediaries;
Assembling an application specific integrated circuit on a package substrate, the application specific integrated circuit electrically connected to the package substrate, and
And assembling the plurality of organic intermediaries and the plurality of photoelectric components assembled on the organic intermediaries on the packaging substrate, wherein the plurality of organic intermediaries and the plurality of photoelectric components assembled on the organic intermediaries surround the application specific integrated circuit and are electrically connected with the packaging substrate.
CN202311472722.2A 2023-11-07 2023-11-07 Packaging structure and manufacturing method thereof Pending CN119965203A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311472722.2A CN119965203A (en) 2023-11-07 2023-11-07 Packaging structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311472722.2A CN119965203A (en) 2023-11-07 2023-11-07 Packaging structure and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN119965203A true CN119965203A (en) 2025-05-09

Family

ID=95590251

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311472722.2A Pending CN119965203A (en) 2023-11-07 2023-11-07 Packaging structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN119965203A (en)

Similar Documents

Publication Publication Date Title
TWI582858B (en) Semiconductor package assembly and method of manufacturing same
CN1148804C (en) Highly Integrated Chip-on-Chip Packaging
US20180012831A1 (en) Semiconductor device
JP2008244437A (en) Image sensor package with die receiving opening and method thereof
TW201535596A (en) Stacked package device and forming method thereof
CN110581107B (en) Semiconductor package and method of manufacturing the same
WO2011086613A1 (en) Semiconductor device and method for fabricating same
WO2016165074A1 (en) Chip
CN112234052B (en) Electronic structure and its preparation method
CN117352502A (en) Electronic packages and manufacturing methods
CN114388471B (en) Packaging structure and manufacturing method thereof
KR20070018057A (en) Vertically stacked semiconductor devices, manufacturing method and process thereof
CN111312676B (en) Fan-out type packaging part and manufacturing method thereof
CN114823589A (en) Chip set and method for manufacturing the same
CN116779589A (en) Packaged device and manufacturing method thereof
CN113192937A (en) Semiconductor device and method for manufacturing the same
CN119965203A (en) Packaging structure and manufacturing method thereof
TW202520386A (en) Package structure and manufacturing method thereof
CN113990843A (en) Chip set and method for manufacturing the same
US20250149426A1 (en) Package structure and manufacturing method thereof
US20250147249A1 (en) Package structure and manufacturing method thereof
KR102730708B1 (en) Stack package and method of manufacturing the same
US20240371714A1 (en) Chip package with a glass interposer
CN223665446U (en) Semiconductor package
US20260016647A1 (en) Packaged devices having photonic integrated circuits therein and methods of fabricating the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination