CN119945452A - A continuous-time reconfigurable sigma-delta modulator - Google Patents
A continuous-time reconfigurable sigma-delta modulator Download PDFInfo
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Abstract
The invention discloses a continuous time reconfigurable sigma-delta modulator which comprises two first-order active integrators, a reconfigurable integrator, a multi-bit quantizer, a half-period delay circuit and a DAC feedback circuit, wherein the first-order active integrator is connected with a second-order reconfigurable integrator, an integration result is sent to a third-order active integrator, the result is sent to the multi-bit quantizer, the quantization result is obtained to be output finally through the encoder, and meanwhile, the quantization result is fed back to the integration circuit through the DAC feedback circuit and the half-period demonstration circuit to realize negative feedback. The continuous time reconfigurable sigma-delta modulator provided by the invention can be applied to the field of audio.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a continuous time reconfigurable sigma-delta modulator.
Background
Almost all signals in nature are analog, such as sound, image, pressure, temperature, etc., and most of the signals used for transmission, storage, calculation and display are digital signals, so that an ADC is required to convert the processed analog signals into corresponding digital signals, and then send the corresponding digital signals to a digital chip for processing, and then output the digital signals through a DAC, thereby obtaining the information wanted by us. Analog-to-digital converters can be divided into two main types, nyquist ADC and oversampling ADC, according to the relationship between the difference in sampling frequency and the signal bandwidth. The traditional Nyquist ADC has larger bandwidth and high conversion speed, but the precision is not high, the development demands of the existing high-fidelity digital audio-video, medical and health electronic equipment and the like on the ultra-high speed and ultra-high precision and low power consumption direction cannot be met, the sampling frequency of the oversampling ADC can be far higher than twice the signal bandwidth, the resolution of the analog-to-digital converter is further improved, the Sigma-Delta ADC is represented by the Sigma-Delta ADC, the sampling frequency is improved, for example, 128 times of oversampling is adopted, the noise is distributed more evenly in a sampling frequency band to reduce in-band noise, the noise in the signal frequency band is shaped outside the signal frequency band by adopting a loop filter by adopting a noise shaping technology, the high-frequency noise is filtered by adopting the digital filter to improve the signal-to-noise ratio of the circuit, the high-precision requirement can be achieved, and the low voltage and the low power consumption are easy to realize.
However, in the actual quantization process, due to reasons such as clock jitter, extra loop delay, nonlinearity of the DAC, etc., there may be some non-ideal factors, so that the effective bit number of the modulator is reduced, the performances such as signal-to-noise ratio and power consumption are poor, the Sigma-Delta modulator with continuous time is mainly divided into two types of high precision and high speed, the Sigma-Delta modulator with high precision mainly adopts an active integrator as a loop filter, so that the excellent effective bit number can be realized, but the power consumption is sacrificed, the passive integrator has low power consumption, but the noise shaping capability is poor, which introduces the problem of compromise between the power consumption and the precision, and most Sigma-Delta modulators currently use a single working mode and cannot meet the multi-mode requirement.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a continuous time reconfigurable sigma-delta modulator so as to solve the technical problem of single working mode of the conventional continuous time sigma-delta ADC modulator, thereby realizing the sigma-delta modulator capable of switching modes between high precision and low power consumption.
Aiming at the defects in the prior art and the prior art, the invention is realized by the following design scheme:
The continuous time reconfigurable sigma-delta modulator is characterized by comprising a first-stage fully-differential active integrator, a second-stage reconfigurable integrator, a third-stage fully-differential active integrator, a multi-bit quantizer, an encoder, a feedback DAC1, a feedback DAC2, a half-period delay circuit and a delay unit, wherein a resistor Rf2, a resistor R21, a capacitor C2, a switch SW1, a switch SW2 and a switch SW3 in the second-stage reconfigurable integrator are simultaneously used for an active mode and a passive mode of the circuit;
the two differential signal input ports VINP and VINN of the first-stage fully differential active integrator are signal input ends of the continuous time reconfigurable sigma-delta modulator, an output end of the first-stage fully differential active integrator is connected with an input end of the second-stage reconfigurable integrator, an output end of the second-stage reconfigurable integrator is connected with an input end of the third-stage fully differential active integrator, an output end of the third-stage fully differential active integrator is connected with an input end of the multi-bit quantizer, an output end of the multi-bit quantizer is connected with an input end of the encoder, an output end of the multi-bit quantizer is connected with an input end of the delay unit, an output end of the delay unit is connected with an input end of the half-period delay circuit, an output end of the delay unit is connected with an input end of the feedback DAC2, an output end of the delay unit is connected with an input end of the feedback DAC1, an output end of the feedback DAC1 is connected with an input end of the first-stage fully differential active integrator, an output end of the feedback DAC2 is connected with an output end of the final-stage differential integrator;
Further, the first-stage fully differential active integrator adopts a fully differential structure and comprises a first-stage feedforward resistor Rf1, a first-stage integral resistor R1, a first-stage integral capacitor C1 and an operational amplifier op1, wherein the first-stage fully differential active integrator is used for carrying out first-stage integration on differential input signals, the first-stage feedforward resistor Rf1 comprises a resistor Rf11 and a resistor Rf12, the first-stage integral resistor R1 comprises a resistor R11 and a resistor R12, the first-stage integral capacitor C1 comprises a capacitor C11 and a capacitor C12, the signal input end VINN and VINP of the continuous time reconfigurable sigma-delta modulator are simultaneously input ends of the first-stage integral resistor R11 and the input end of the first-stage feedforward resistor Rf11 and the input end of the operational amplifier Rf12, the output end of the first-stage integral resistor R11 is simultaneously the input end of the first-stage integral capacitor C11 and the input end of the operational amplifier op1, the output end of the first-stage integral resistor R11 is simultaneously the output end of the first-stage integral resistor Rf1 and the first-stage integrator 12, the input end of the first-stage integrator R1 is simultaneously the input end of the first-stage integrator 1 and the first-stage integrator 11 is simultaneously the input end of the first-input end of the operational amplifier op 1-the first-stage integrator, the first-stage integrator is simultaneously the input end of the first-stage integrator 1-input end of the first-input end of the operational amplifier-input end of the first-stage integrator, the first-stage integrator is simultaneously the first-input end of the first-stage integrator and the first-stage integrator Constructing an output end of a third-stage feedforward resistor Rf32 in the integrator;
further, the second-stage reconfigurable integrator adopts a fully differential structure and comprises a second-stage feedforward resistor Rf2, a third-stage feedforward resistor Rf3, a second-stage integrating resistor R2, a second-stage integrating capacitor C2, a first-stage switch SW1, a second-stage switch SW2, a third-stage switch SW3, an operational amplifier op2, a connection point A and a connection point B, wherein the second-stage reconfigurable integrator is used for performing first-stage integration on an input signal, the second-stage feedforward resistor Rf2 comprises a resistor Rf21 and a resistor Rf22, the third-stage feedforward resistor Rf3 comprises a resistor Rf31 and a resistor Rf32, and the second-stage integrating resistor R2 comprises a resistor R21, A resistor R22, A resistor R23 and a resistor R24, the second stage integrating capacitor C2 includes a capacitor C21 and a capacitor C22, the first stage switch SW1 includes a switch SW11 and a switch SW12, the second stage switch SW2 includes a switch SW21 and a switch SW22, and the third stage switch SW3 includes a switch SW31 and a switch SW32; the input end of the second-stage integrating resistor R21 is the input end of the second-stage feedforward resistor Rf22 and the output end vo1+ of the operational amplifier op1 in the first-stage fully differential active integrator, the input end of the second-stage integrating resistor R22 is the output end of the second-stage integrating resistor R21 and the input end of the second-stage switch SW21, the input end of the second-stage integrating resistor R23 is the input end of the second-stage feedforward resistor Rf22 and the output end vo1+ of the operational amplifier op1 in the first-stage fully differential active integrator, the input end of the second-stage integrating resistor R24 is the output end of the second-stage integrating resistor R23 and the input end of the second-stage switch SW22, the input end of the second-stage integrating capacitor C21 is the output end of the second-stage integrating resistor R22 and the input end vi2 of the operational amplifier SW21, the second-stage integrating resistor C22 is the input end of the second-stage integrating resistor R22 and the second-stage integrating resistor R22, the input end of the second-stage integrating resistor R24 is the input end of the second-stage integrating resistor R23 and the second-stage integrating resistor R22, the input end of the second-stage integrating resistor R22 is the input end of the second-stage integrating resistor R23, the input end of the second-stage integrating resistor R22 is the second-stage integrating resistor R22, the input end of the second-stage integrating resistor R22 is the second-stage input end of the second-integrating resistor R22, the second-stage integrating resistor R2 is the second-stage input end 23, and the second-stage input end 23 is the second-stage input end 23, and the second-stage input end switch 2 is the second-stage switch 2 ① The output end ② of the first stage switch SW11 is simultaneously the output end of the third stage feedforward resistor Rf31 and the input end of a third stage integrating capacitor C31 in the third stage fully differential active integrator, the output end ② of the first stage switch SW12 is simultaneously the output end of the third stage feedforward resistor Rf32 and the input end of a third stage integrating capacitor C32 in the third stage fully differential active integrator, the output end of the second stage switch SW21 is simultaneously the output end ① of the third stage switch SW32 and the input end of a third stage integrating resistor R31 in the third stage fully differential active integrator, the output end of the second stage switch SW22 is simultaneously the output end ① of the third stage switch SW32 and the input end of a third stage integrating resistor R32 in the third stage fully differential active integrator, the input end of the third stage switch SW31 is simultaneously the output end of the second stage integrating capacitor C21 and the output end voop 2 of the operational amplifier op2, the connection point of the second stage switch SW22 is simultaneously the output end of the third stage integrating resistor C32 and the third stage integrating resistor C32, and the connection point of the third stage switch Rb2 is simultaneously the output end of the third stage integrating resistor C32 and the third stage integrating resistor C2;
Further, the third-stage fully-differential active integrator adopts a fully-differential structure and comprises a third-stage integrating resistor R3, a third-stage integrating capacitor C3, a first-stage feedback resistor Rb and an operational amplifier op3; the third-stage fully-differential active integrator is used for first-stage integration of an input signal, wherein the third-stage integrating resistor R3 comprises a resistor R31 and a resistor R32, the third-stage integrating capacitor C3 comprises an integrating capacitor C31 and an integrating capacitor C32, the first-stage feedback resistor Rb comprises a resistor Rb1 and a resistor Rb2, the input end of the third-stage integrating resistor R31 is simultaneously the output end ① of the third-stage switch SW32 and the output end of the second-stage switch SW21, the input end of the third-stage integrating resistor R32 is simultaneously the output end ① of the third-stage switch SW31 and the output end of the second-stage switch SW22, the input end of the third-stage integrating capacitor C31 is simultaneously the output end of the third-stage integrating resistor R31 and the input end vi 3-of the operational amplifier op3, the input end of the third-stage integrating capacitor C31 is simultaneously the output end ② of the third-stage switch SW11 and the output end of the feedback DAC2, the input end of the third-stage integrating capacitor C32 is simultaneously the output end of the integrating capacitor C31 and the output end of the third-stage integrating capacitor C3 and the output end of the third-integrating capacitor C32 is simultaneously the output end of the integrating capacitor C3 and the output end of the third-stage capacitor 37 is simultaneously the input end of the third-integrating capacitor C3 and the output end of the operational amplifier op3 is simultaneously The input end vo3+ of the operational amplifier op3 and the input end vo3 of the operational amplifier op3 are the output end of the third-stage fully-differential active integrator and the input end of the multi-bit quantizer at the same time;
Further, the half-period delay circuit comprises a delay unit delay1 and a compensation DACkb, wherein the input end of the multi-bit quantizer is connected with the output end of the third-stage fully-differential active integrator, the output end of the multi-bit quantizer is simultaneously the input end of the delay unit and the input end of the encoder, the positive output end of the feedback DAC1 is connected with the input end vi 1-of the operational amplifier op1 in the first-stage fully-differential active integrator in a negative feedback mode, the negative output end of the feedback DAC1 is connected with the input end vi1+ of the operational amplifier op1 in the first-stage fully-differential active integrator in a negative feedback mode, the output end of the delay unit is simultaneously the input end of the feedback DAC1, the input end of the feedback DAC2 and the input end of the half-period delay circuit, the input end of the delay unit delay1 is connected with the output end of the delay unit, the output end of the delay unit delay1 is connected with the input end vi 1-of the compensation DACkb, the negative output end of the feedback unit delay1 is connected with the input end of the negative feedback DAC 3-of the full-differential active integrator in a negative feedback mode, and the positive output end of the feedback DAC 3 is simultaneously connected with the input end 3+ of the third-stage fully-differential active integrator in a negative feedback mode, and the output 3 is simultaneously connected with the input end 3+ of the third-stage of the feedback DAC 3.
The invention has the beneficial effects that the sigma-delta modulator capable of switching two different modes is realized, compared with the traditional scheme, the invention realizes the mutual switching of the active integration mode and the passive integration mode by utilizing the reconfigurable integrator, when the sigma-delta modulator is in the active integration mode, the high-precision conversion can be realized, and when the sigma-delta modulator is in the passive integration mode, the low-power consumption mode can be realized, and because the passive integration mode adopts the integration capacitor parallel technology, the technology remarkably improves the precision of the low-power consumption mode, further improves the performance of the sigma-delta modulator, and realizes the reconfigurable sigma-delta modulator with high precision.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will briefly introduce the drawings that are required to be used in the embodiments or the description of the prior art, in which the drawings are only some embodiments recorded in the present invention, and other drawings can be obtained according to these drawings without paying any inventive effort to those skilled in the art.
FIG. 1 is a schematic circuit diagram of a continuous time reconfigurable sigma-delta modulator of the present invention;
FIG. 2 is a schematic diagram of the output spectrum of a continuous-time reconfigurable sigma-delta modulator of the present invention when a 17.5kHz signal is input in an active mode of operation;
Fig. 3 is a schematic diagram of the output spectrum of a continuous time reconfigurable sigma-delta modulator of the present invention when the 17.5kHz signal is input in a passive mode of operation.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the following detailed description of the embodiments of the present invention will be given with reference to the accompanying drawings. Examples of these preferred embodiments are illustrated in the accompanying drawings. The embodiments of the invention shown in the drawings described in accordance with the drawings are merely exemplary and are not limited to these embodiments.
It should be noted that, in order to avoid obscuring the present invention due to unnecessary details, only structures and/or processing steps closely related to the solution according to the present invention are shown in the drawings, while other details not greatly related to the present invention are omitted.
And, in the description of the present invention, the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., are directions or positional relationships based on the drawings, are merely for convenience of description of the present invention and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In order to illustrate the technical solutions of the present invention, the following description is made by specific embodiments, only the portions related to the embodiments of the present invention are shown.
Referring to FIG. 1, the continuous time reconfigurable sigma-delta modulator mainly comprises a first-stage fully differential active integrator, a second-stage reconfigurable integrator, a third-stage fully differential active integrator, a multi-bit quantizer, an encoder, a feedback DAC1, a feedback DAC2, a half-period delay circuit and a delay unit, wherein a resistor Rf2, a resistor R21, a capacitor C2, a switch SW1, a switch SW2 and a switch SW3 in the second-stage reconfigurable integrator are simultaneously used for an active mode and a passive mode of the circuit;
the two differential signal input ports VINP and VINN of the first-stage fully differential active integrator are signal input ends of the continuous time reconfigurable sigma-delta modulator, an output end of the first-stage fully differential active integrator is connected with an input end of the second-stage reconfigurable integrator, an output end of the second-stage reconfigurable integrator is connected with an input end of the third-stage fully differential active integrator, an output end of the third-stage fully differential active integrator is connected with an input end of the multi-bit quantizer, an output end of the multi-bit quantizer is connected with an input end of the encoder, an output end of the multi-bit quantizer is connected with an input end of the delay unit, an output end of the delay unit is connected with an input end of the half-period delay circuit, an output end of the delay unit is connected with an input end of the feedback DAC2, an output end of the delay unit is connected with an input end of the feedback DAC1, an output end of the feedback DAC1 is connected with an input end of the first-stage fully differential active integrator, an output end of the feedback DAC2 is connected with an output end of the final-stage differential integrator;
Specifically, the first-stage fully-differential active integrator adopts a fully-differential structure and comprises a first-stage feedforward resistor Rf1, a first-stage integrating resistor R1, a first-stage integrating capacitor C1 and an operational amplifier op1; the first-stage fully differential active integrator is used for carrying out first-stage integration on differential input signals, wherein the first-stage feedforward resistor Rf1 comprises a resistor Rf11 and a resistor Rf12, the first-stage integrating resistor R1 comprises a resistor R11 and a resistor R12, the first-stage integrating capacitor C1 comprises a capacitor C11 and a capacitor C12, the signal input ends VINN and VINP of the continuous time reconfigurable sigma-delta modulator are simultaneously the input ends of the first-stage integrating resistors R11 and R12 and the input ends of the first-stage feedforward resistors Rf11 and Rf12, the output end of the first-stage integrating resistor R11 is simultaneously the input end of the first-stage integrating capacitor C11 and the input end vi 1-of the operational amplifier op1, the output end of the first-stage integrating resistor R12 is simultaneously the output end of the first-stage integrating capacitor C11 and the output end of the operational amplifier op1, the first-stage integrating resistor R12 is simultaneously the input end of the first-integrating resistor R12 and the first-stage integrating resistor R1 is simultaneously the input end of the first-integrating resistor R1 and the first-stage integrating resistor Rf31, the output end of the first-integrating resistor R11 is simultaneously the output end of the first-stage integrating resistor R11 and the output end of the operational amplifier op1, the output end of the first-integrating resistor R12 is simultaneously the output end of the feedback DAC1, the output end of the first-stage integrating resistor C12 is simultaneously, the output end of the input end of the first-integrating resistor C12 is simultaneously, the input end of the first-stage integrator 12, and the input end is simultaneously The output end of the third stage feed-forward resistor Rf32 in the integrator;
Specifically, the second-stage reconfigurable integrator adopts a fully differential structure and comprises a second-stage feedforward resistor Rf2, a third-stage feedforward resistor Rf3, a second-stage integrating resistor R2, a second-stage integrating capacitor C2, a first-stage switch SW1, a second-stage switch SW2, a third-stage switch SW3, an operational amplifier op2, a connection point A and a connection point B, wherein the second-stage reconfigurable integrator is used for performing first-stage integration on an input signal, the second-stage feedforward resistor Rf2 comprises a resistor Rf21 and a resistor Rf22, the third-stage feedforward resistor Rf3 comprises a resistor Rf31 and a resistor Rf32, and the second-stage integrating resistor R2 comprises a resistor R21, A resistor R22, A resistor R23 and a resistor R24, the second stage integrating capacitor C2 includes a capacitor C21 and a capacitor C22, the first stage switch SW1 includes a switch SW11 and a switch SW12, the second stage switch SW2 includes a switch SW21 and a switch SW22, and the third stage switch SW3 includes a switch SW31 and a switch SW32; the input end of the second-stage integrating resistor R21 is the input end of the second-stage feedforward resistor Rf22 and the output end vo1+ of the operational amplifier op1 in the first-stage fully differential active integrator, the input end of the second-stage integrating resistor R22 is the output end of the second-stage integrating resistor R21 and the input end of the second-stage switch SW21, the input end of the second-stage integrating resistor R23 is the input end of the second-stage feedforward resistor Rf22 and the output end vo1+ of the operational amplifier op1 in the first-stage fully differential active integrator, the input end of the second-stage integrating resistor R24 is the output end of the second-stage integrating resistor R23 and the input end of the second-stage switch SW22, the input end of the second-stage integrating capacitor C21 is the output end of the second-stage integrating resistor R22 and the input end vi2 of the operational amplifier SW21, the second-stage integrating resistor C22 is the input end of the second-stage integrating resistor R22 and the second-stage integrating resistor R22, the input end of the second-stage integrating resistor R24 is the input end of the second-stage integrating resistor R23 and the second-stage integrating resistor R22, the input end of the second-stage integrating resistor R22 is the input end of the second-stage integrating resistor R23, the input end of the second-stage integrating resistor R22 is the second-stage integrating resistor R22, the input end of the second-stage integrating resistor R22 is the second-stage input end of the second-integrating resistor R22, the second-stage integrating resistor R2 is the second-stage input end 23, and the second-stage input end 23 is the second-stage input end 23, and the second-stage input end switch 2 is the second-stage switch 2 ① The output end ② of the first stage switch SW11 is simultaneously the output end of the third stage feedforward resistor Rf31 and the input end of a third stage integrating capacitor C31 in the third stage fully differential active integrator, the output end ② of the first stage switch SW12 is simultaneously the output end of the third stage feedforward resistor Rf32 and the input end of a third stage integrating capacitor C32 in the third stage fully differential active integrator, the output end of the second stage switch SW21 is simultaneously the output end ① of the third stage switch SW32 and the input end of a third stage integrating resistor R31 in the third stage fully differential active integrator, the output end of the second stage switch SW22 is simultaneously the output end ① of the third stage switch SW32 and the input end of a third stage integrating resistor R32 in the third stage fully differential active integrator, the input end of the third stage switch SW31 is simultaneously the output end of the second stage integrating capacitor C21 and the output end voop 2 of the operational amplifier op2, the connection point of the second stage switch SW22 is simultaneously the output end of the third stage integrating resistor C32 and the third stage integrating resistor C32, and the connection point of the third stage switch Rb2 is simultaneously the output end of the third stage integrating resistor C32 and the third stage integrating resistor C2;
The third-stage fully-differential active integrator adopts a fully-differential structure and comprises a third-stage integrating resistor R3, a third-stage integrating capacitor C3, a first-stage feedback resistor Rb and an operational amplifier op3, wherein the third-stage fully-differential active integrator is used for carrying out first-order integration on an input signal, the third-stage integrating resistor R3 comprises a resistor R31 and a resistor R32, the third-stage integrating capacitor C3 comprises an integrating capacitor C31 and an integrating capacitor C32, the first-stage feedback resistor Rb comprises a resistor Rb1 and a resistor Rb2, the input end of the third-stage integrating resistor R31 is simultaneously the output end ① of the third-stage switch SW32 and the output end of the second-stage switch SW21, the input end of the third-stage integrating resistor R32 is simultaneously the output end ① of the third-stage switch SW31 and the output end of the second-stage switch SW22, the input end of the third-stage integrating capacitor C31 is simultaneously the output end of the third-stage integrating resistor R31 and the input end of the operational amplifier op3, the input end of the third-stage integrating resistor Rb 3 is simultaneously the output end of the third-stage switch SW32 and the output end of the third-stage switch SW32 is simultaneously the output end ① of the third-stage switch SW21, the input end of the third-stage switch SW31 is simultaneously the output end of the third-stage switch SW31 and the output end of the third-stage switch SW32 is simultaneously the output end 35 and the output end of the third-stage switch 23 and the third-stage switch 23 is simultaneously the output end of the third-stage switch 23 and the output end 23 is simultaneously the output end of the third-stage 23 and the third-stage switch 23 and the output end of the third-stage 23 is simultaneously The input end vo3+ of the operational amplifier op3 and the input end vo3 of the operational amplifier op3 are the output end of the third-stage fully-differential active integrator and the input end of the multi-bit quantizer at the same time;
The half-period delay circuit comprises a delay unit delay1 and a compensation DACkb, wherein the input end of the multi-bit quantizer is connected with the output end of the third-stage fully-differential active integrator, the output end of the multi-bit quantizer is simultaneously the input end of the delay unit and the input end of the encoder, the positive output end of the feedback DAC1 is connected with the input end vi 1-of an operational amplifier op1 in the first-stage fully-differential active integrator in a negative feedback mode, the negative output end of the feedback DAC1 is connected with the input end vi1+ of the operational amplifier op1 in the first-stage fully-differential active integrator in a negative feedback mode, the output end of the delay unit is simultaneously the input end of the feedback DAC1, the input end of the feedback DAC2 and the input end of the half-period delay circuit, the input end of the delay unit delay1 is connected with the output end of the delay unit, the output end of the delay unit delay1 is connected with the input end vi 1-of the compensation DACkb, the negative output end of the feedback unit delay1 is connected with the input end of the negative feedback DAC 3-of the full-differential active integrator in a negative feedback mode, the positive output end of the feedback DAC 3 is simultaneously connected with the input end of the third-stage fully-differential active integrator 3 in a negative feedback mode, and the output of the three-stage differential active integrator 3 is simultaneously connected with the input end of the positive output end of the 3-stage 3-differential active integrator.
In this example, differential input signals VINP and VINN are input from one end of first-stage integrating resistors R12 and R11, the first-stage fully-differential active integrator (101) performs first-stage integration on the differential signals through capacitors C11 and C12, the integrated signals are output from the differential output end of an operational amplifier op1 to the second-stage reconfigurable integrator (102), and meanwhile, the differential input signals VINP and VINN are also input to the input ends of third-stage integrating capacitors C32 and C31 in the third-stage fully-differential active integrator (103) through first-stage feedforward resistors Rf12 and Rf11 to perform addition operation;
When the circuit works in an active integration mode, the output end ① of a first-stage switch SW1 in the second-stage reconfigurable integrator (102) is conducted, the second-stage switch SW2 is disconnected, the output end ① of a third-stage switch SW3 is conducted, the operational amplifier op2 works normally, the input end of the second-stage reconfigurable integrator (102) is connected with the output end of the first-stage fully differential active integrator (101), the second-stage reconfigurable integrator (102) carries out first-order integration on an integrated signal output by the first-stage fully differential active integrator (101) through capacitors C21 and C22, the integrated signal is output from the differential output end of an operational amplifier op2, the integrated signal is input to the third-stage fully differential active integrator (103) through a switch SW31 and a switch SW32 respectively, meanwhile, the differential signal is connected with the output end of the third-stage fully differential active integrator (103) through second-stage feedforward resistors Rf21 and Rf22 and through first-stage switches SW11 and SW12 and third-stage feedforward resistors Rf31 and Rf32, the integrated signal is output to a feedback connection point C31 and a third-stage fully differential integrator (103) for reducing the input signal to a feedback point B through a feedback resistor B and a third-stage full-differential integrator (1);
when the circuit works in a passive integration mode, the output end ② of a first-stage switch SW1 in the second-stage reconfigurable integrator (102) is conducted, the second-stage switch SW2 is closed, the output end ② of a third-stage switch SW3 is conducted, the operational amplifier op2 is closed, the input end of the second-stage reconfigurable integrator (102) is connected with the output end of the first-stage fully differential active integrator (101), the second-stage reconfigurable integrator (102) carries out first-order integration on an integrated signal output by the first-stage fully differential active integrator (101) through capacitors C21 and C22, the integrated signal is output from the input ends of resistors R22 and R24 and is input to the third-stage fully differential active integrator (103), the input end of the capacitor C21 is connected with the output end of the capacitor C22 through the output end ② of SW32, the input end of the capacitor C22 is connected with the output end ② of the capacitor C21 through the SW31, a structure of the capacitor C21 is formed, the structure is improved, the integrated signal output end of the second-stage fully differential integrator is connected with the input end of the third-stage fully differential integrator (101) through the capacitors C21 and Rb2, the integrated signal is fed back to the first-stage integrator (Rf 2) through the input end of the third-stage fully differential integrator, and the input end of the third-stage switch Rf2 is fed back to the first-stage integrator (101), and the input end of the third-stage fully differential integrator is fed back signal is fed through the third-stage differential integrator (101);
The input end of the third-stage fully-differential active integrator (103) is connected with the output end of the second-stage reconfigurable integrator (102), an integrated signal passing through the second-stage reconfigurable integrator (102) is input from one end of the third-stage integrating resistors R31 and R32, first-stage integration is realized through the capacitors C31 and C32, and an integrated signal is output from the differential output end of the operational amplifier op3 to the input end of the multi-bit quantizer (104);
The output of the third stage fully differential active integrator (103) is used as the input of the multi-bit quantizer (104), which in this example is a 4bit SAR ADC, consisting of C DAC capacitor drive, C DAC capacitor array, comparator, SAR logic and latch;
the 4-bit 2-system code output by the multi-bit quantizer (104) is input into the half-period delay circuit (108) and the delay unit (109), feedback signals are input into the input end of the feedback DAC1 (106), the input end of the feedback DAC2 (107) and the input end of the half-period delay circuit (108) after half-period delay is realized through the delay unit (109), the input end of the feedback DAC1 (106), the feedback DAC2 (107) and the feedback DACkb all adopt a current rudder DAC structure, current signals passing through the half-period delay circuit (108) are added with current signals passing through the feedback DAC2 (107), then the capacitors C31 and C32 are charged, negative feedback is realized, and the current signals passing through the feedback DAC1 (106) charge the capacitors C11 and C12, so that negative feedback is realized.
The embodiment of the invention is used in the audio frequency field, and the working frequency band is 0-20 KHz. It should be noted that the operating frequency band of the embodiment is only an example, and is not limited by a specific operating frequency, and the present invention is applicable to different frequency bands in practical designs.
Referring to fig. 2, a transient simulation FFT result of a continuous time reconfigurable sigma-delta modulator in an active mode. The resistance values of R11 and R12 are set to be the same, the resistance values of R21 and R23 are the same, the resistance values of R22 and R24 are the same, the resistance values of R31 and R32 are the same, the resistance values of Rf11 and Rf12 are the same, the resistance values of Rf21 and Rf22 are the same, the resistance values of Rf31 and Rf32 are the same, the resistance values of Rb1 and Rb2 are the same, the capacitance values of C11 and C12 are the same, the capacitance values of C21 and C22 are the same, and the capacitance values of C31 and C32 are the same. The continuous time reconfigurable sigma-delta modulator has an effective bit number (ENOB) of 16.89bits, power consumption of 767uW, a signal-to-noise ratio (SNR) of 103.46dB and a spurious-free dynamic range (SFDR) of 108.24dB in an active mode working voltage of 1.8V and a sampling frequency of 5.12MHz, and an input signal frequency of 17.5kHz and a 20K bandwidth.
Referring to fig. 3, a transient simulation FFT result of a continuous time reconfigurable sigma-delta modulator in a passive mode. The resistance values of R11 and R12 are set to be the same, the resistance values of R21 and R23 are the same, the resistance values of R22 and R24 are the same, the resistance values of R31 and R32 are the same, the resistance values of Rf11 and Rf12 are the same, the resistance values of Rf21 and Rf22 are the same, the resistance values of Rb1 and Rb2 are the same, the capacitance values of C11 and C12 are the same, the capacitance values of C21 and C22 are the same, and the capacitance values of C31 and C32 are the same. The sigma-delta modulator has an effective bit number (ENOB) of 14.2bits, power consumption of 580uW, a signal-to-noise ratio (SNR) of 87.29dB and a spurious-free dynamic range (SFDR) of 92.55dB in a bandwidth of 20K at an input signal frequency of 17.5kHz under the working voltage of 1.8V and the sampling frequency of 5.12MHz in a passive mode.
Furthermore, it should be noted that, in this specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
It should be understood that although the present disclosure describes embodiments, not every embodiment is provided with a separate embodiment, and that this description is provided for clarity only, and that the disclosure is not limited to specific embodiments, and that the embodiments may be combined appropriately to form other embodiments that will be understood by those skilled in the art.
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| CN101404503A (en) * | 2007-10-04 | 2009-04-08 | 联发科技股份有限公司 | Continuous-time sigma-delta modulator and method for compensating loop delay thereof |
| WO2012106395A1 (en) * | 2011-02-04 | 2012-08-09 | Syntropy Systems | Sampling/quantization converters |
| US20130021184A1 (en) * | 2011-01-21 | 2013-01-24 | Ashburn Jr Michael A | Direct feedback for continuous-time oversampled converters |
| WO2017037744A2 (en) * | 2015-09-03 | 2017-03-09 | Indian Institute Of Technology Madras | A delta sigma modulator with noise attenuating feedback filters |
| CN116707530A (en) * | 2023-07-04 | 2023-09-05 | 桂林电子科技大学 | A High-Order Continuous-Time Hybrid Architecture Sigma-Delta Modulator |
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| CN101404503A (en) * | 2007-10-04 | 2009-04-08 | 联发科技股份有限公司 | Continuous-time sigma-delta modulator and method for compensating loop delay thereof |
| US20130021184A1 (en) * | 2011-01-21 | 2013-01-24 | Ashburn Jr Michael A | Direct feedback for continuous-time oversampled converters |
| WO2012106395A1 (en) * | 2011-02-04 | 2012-08-09 | Syntropy Systems | Sampling/quantization converters |
| WO2017037744A2 (en) * | 2015-09-03 | 2017-03-09 | Indian Institute Of Technology Madras | A delta sigma modulator with noise attenuating feedback filters |
| CN116707530A (en) * | 2023-07-04 | 2023-09-05 | 桂林电子科技大学 | A High-Order Continuous-Time Hybrid Architecture Sigma-Delta Modulator |
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