CN119917426B - Memory management method and memory controller - Google Patents

Abstract

The present disclosure provides a memory management method and a controller thereof. The method comprises the steps of obtaining mapping table data to be stored, determining the size of an array storage group according to the total number of a plurality of chip enable pins, wherein the array storage group comprises a plurality of entity pages corresponding to the chip enable pins with the number smaller than the total number, setting a plurality of array storage groups which are arranged successively based on word line sequence, chip enable pin sequence and plane sequence, and storing the mapping table data into the plurality of array storage groups, wherein each check page of two adjacent array storage groups corresponds to different chip enable pins. Through the technical scheme, the storage distribution uniformity of the mapping table data can be improved, the parallel efficiency of data reading is ensured, and meanwhile, the reliability of data protection is maintained.

Description

Memory management method and memory controller

Technical Field

The present disclosure relates to the field of memory technology, and more particularly, to a memory management method and a controller thereof applied to a memory device configured with a rewritable nonvolatile memory module.

Background

In modern storage technology, rewritable nonvolatile memory (NAND FLASH) is widely used in storage devices such as Solid State Disks (SSD).

In existing solid state disk architectures, the mapping table is responsible for mapping logical addresses to physical addresses, through which the correct data storage locations are located. The correctness of the mapping table is critical to the data reading of the solid state disk. In order to enhance the protection capability of the mapping table, besides LDPC (Low DENSITY PARITY CHECK) protection, an Error correction Code (RAID ECC) mechanism of the redundant array of independent disks is required. The mechanism carries out multi-channel scattered storage on the mapping table data, and stores the check code coded by ECC in the last plane corresponding to the last channel. However, this approach would centralize the check code in the last plane of the last lane. When the mapping table data is written, if power failure occurs, a virtual page (dummy page) is supplemented before the last plane of the last channel, so that effective data is only stored in the chip corresponding to the previous channel, and the reading speed of the mapping table data is further affected.

Disclosure of Invention

Aiming at the problem that in the prior art, check codes of mapping table data are stored in the last plane of the last channel in a concentrated manner, so that virtual pages are needed to be supplemented when power is off to influence the data reading speed, the disclosure provides a memory management method and a controller thereof. By optimizing the storage distribution strategy of the mapping table data, the check pages can be uniformly distributed in different chip enabling pins, so that the reading efficiency of the mapping table data is improved while the data protection capability is ensured.

One or more embodiments of the present disclosure provide a memory management method suitable for a memory device configured with a rewritable nonvolatile memory module including a plurality of chips each corresponding to a chip enable pin, each chip including P planes. The method includes the steps of obtaining mapping table data to be stored, determining the size of an array storage group according to the total number N of a plurality of chip enable pins, wherein the array storage group comprises a plurality of entity pages corresponding to M chip enable pins, M is smaller than N and larger than 1, and M is equal to N minus a preset value, setting a plurality of array storage groups which are arranged successively based on a word line sequence, a chip enable pin sequence and a plane sequence, wherein the plurality of entity pages of each array storage group respectively correspond to different planes of the M chip enable pins, and storing the mapping table data into the plurality of array storage groups, wherein the plurality of entity pages of each array storage group comprise a plurality of data pages and a check page, wherein the plurality of data pages are used for storing partial mapping table data corresponding to the array storage group, and the check page is used for storing check data corresponding to the partial mapping table data, and the check pages of two adjacent array storage groups respectively correspond to different chip enable pins.

In one or more embodiments of the present disclosure, the step of setting the plurality of array memory groups arranged in succession based on the word line order, the chip enable pin order, and the plane order includes selecting a first array memory group to be set in a sequence number order of the plurality of array memory groups, selecting an available first word line based on the word line order, selecting one or more first chip enable pins from a plurality of chip enable pins corresponding to the first word line based on the chip enable pin order, and if the number of the one or more first chip enable pins is equal to M, acquiring a plurality of first physical pages corresponding to the plurality of planes in each first chip enable pin, and setting the plurality of first physical pages as the plurality of physical pages of the first array memory group.

In one or more embodiments of the present disclosure, wherein the step of setting the sequentially arranged plurality of array memory banks based on the word line order, the chip enable pin order, and the plane order further comprises, if the number of the one or more first chip enable pins selected in the first word line is smaller than M, selecting available second word lines ordered after the first word line, selecting available one or more second chip enable pins from the plurality of chip enable pins corresponding to the second word line based on the chip enable pin order, wherein the total number of the one or more first chip enable pins and the one or more second chip enable pins is M, obtaining a plurality of first physical pages corresponding to the plurality of planes in each first chip enable pin, and obtaining a plurality of second physical pages corresponding to the plurality of planes in each second chip enable pin, and setting the plurality of physical pages and the plurality of physical pages as the plurality of first array memory banks.

In one or more embodiments of the present disclosure, the check page of each array storage group is the last of the plurality of physical pages of the array storage group.

In one or more embodiments of the present disclosure, if N is an even number, then M is the divisor of N with a remainder.

In one or more embodiments of the present disclosure, wherein the predetermined value is 1.

In one or more embodiments of the present disclosure, wherein the chip enable pin following the last chip enable pin of the ith wordline is the first chip enable pin of the (i+1) th wordline, wherein the plurality of physical pages of each array memory group corresponds to the plurality of chip enable pins of the same wordline or to the plurality of chip enable pins of adjacent wordlines, wherein each wordline comprises NP physical pages.

In one or more embodiments of the present disclosure, the method further includes reconstructing target portion mapping table data stored in a target chip according to the portion mapping table data stored in other chips than the target chip and the corresponding verification data if the target chip fails.

In one or more embodiments of the present disclosure, the plane order is from the 0 th plane to the P-1 st plane within the same chip enable pin.

One or more embodiments of the present disclosure provide a memory controller for controlling a memory device configured with a rewritable non-volatile memory module. The memory controller comprises a memory interface control circuit and a processor, wherein the memory interface control circuit is used for being electrically connected to the rewritable nonvolatile memory module, the rewritable nonvolatile memory module comprises a plurality of chips, each chip corresponds to a chip enabling pin and comprises P planes, and the processor is electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to a connection interface circuit of the memory device so as to be electrically connected to a host system. Wherein the processor is configured to obtain mapping table data to be stored, determine a size of an array storage group according to a total number N of a plurality of chip enable pins, wherein the array storage group comprises a plurality of physical pages corresponding to M chip enable pins, wherein M is less than N and greater than 1, and M is equal to N minus a predetermined value, set a plurality of array storage groups arranged in succession based on a word line order, a chip enable pin order, and a plane order, wherein the plurality of physical pages of each array storage group respectively correspond to different planes of the M chip enable pins, and store the mapping table data into the plurality of array storage groups, wherein the plurality of physical pages of each array storage group comprises a plurality of data pages and one check page, wherein the plurality of data pages are used to store partial mapping table data corresponding to the array storage group, and the check page is used to store check data corresponding to the partial mapping table data, wherein the respective check pages of two adjacent array storage groups correspond to different chip enable pins.

Based on the above, the memory management method and the controller thereof provided by the present disclosure enable mapping table data and check pages thereof to be uniformly distributed in different chip enable pins by optimizing the size setting and distribution mode of the array storage group, thereby effectively avoiding the problem of data centralized storage. Meanwhile, the method can ensure the parallel reading efficiency of the mapping table data even under the condition of power failure on the premise of keeping the data protection intensity, thereby improving the overall performance of the storage device.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention;

FIG. 2 is a flow chart of a memory management method shown according to one embodiment of the present disclosure;

FIG. 3 is a schematic diagram of setting array memory banks by a conventional method;

Fig. 4 is a schematic diagram illustrating setting array storage groups via a provided memory management method according to one embodiment of the present disclosure.

Description of the reference numerals

10 Host System

20 Storage device

110 Processor (second processor)

120 Host memory

130 Data transmission interface circuit

210 Memory controller

211 Processor (first processor)

212 Data management circuit

213 Memory interface control circuit

214 Buffer memory

220 Rewritable non-volatile memory module

230 Connection interface circuit

S210-S240 step

CE0-CE3 chip enable pins

PL0, PL1 plane

PG000-PG231 physical pages

SG0-SG2 word string line

REG01-REG03, REG11-REG14 array memory set

Detailed Description

Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the invention. Referring to fig. 1, a host system 10 is, for example, a personal computer, a notebook computer, or a server. The Host System (Host System) 10 includes a Processor (Processor) 110 (also referred to as a second Processor), a Host Memory (Host Memory) 120, and a data transfer interface Circuit (DATA TRANSFER INTERFACE Circuit) 130. In the present embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transmission interface circuit 130. In another embodiment, the Processor 110, the host memory 120 and the data transmission interface circuit 130 are electrically connected to each other by a System Bus (System Bus). In the present embodiment, the processor 110, the host memory 120 and the data transmission interface circuit 130 may be disposed on a motherboard of the host system 10.

The memory device 20 includes a memory controller (Memory Controller) 210, a Rewritable nonvolatile memory module (Rewritable Non-Volatile Memory Module) 220, a connection interface circuit (Connection Interface Circuit) 230, and a random access memory 240. The memory controller 210 includes a processor 211 (also called a first processor), a data management Circuit (DATA MANAGEMENT Circuit) 212, and a memory interface control Circuit (Memory Interface Control Circuit) 213.

In the present embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operation. For example, the host system 10 may store data to the storage device 20 or read data from the storage device 20 via the data transfer interface circuit 130.

In this embodiment, the number of the data transmission interface circuits 130 may be one or more. The motherboard can be electrically connected to the memory device 20 through a wired or wireless manner via the data transmission interface circuit 130. The storage device 20 may be, for example, a usb disk, a memory card, a Solid state disk (Solid STATE DRIVE, SSD), or a wireless memory storage device. The wireless memory storage device may be, for example, a Near Field Communication (NFC) memory storage device, a wireless facsimile (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a Bluetooth low energy memory storage device (e.g., iBeacon) or the like based on various wireless Communication technologies. In addition, the motherboard may also be electrically connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, and a speaker through a system bus.

In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component connection interface (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCI Express) standard. And, the data transmission interface circuit 130 and the connection interface circuit 230 use the rapid nonvolatile memory interface standard (Non-Volatile Memory express, NVMe) protocol to transmit data.

In addition, in another embodiment, the connection interface circuit 230 may be packaged with the memory controller 210 in a chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210.

In the present embodiment, the host memory 120 is used for temporarily storing instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 and the random access memory 240 may be dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random Access Memory, SRAM), and the like. However, it should be understood that the present invention is not limited thereto, and the host memory 120 and the random access memory 240 may be other suitable memories.

The memory controller 210 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware and perform operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 220 according to the instructions of the host system 10.

In more detail, the processor 211 in the memory controller 210 is hardware with operation capability, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with a plurality of control commands/program codes, and these control commands/program codes are executed to perform data writing, reading and erasing operations while the memory device 20 is operating. In addition, in this embodiment, the control instructions/program codes may be further executed to perform a specific garbage collection operation, so as to implement the memory management method for different working states of the memory device according to the present invention. The control instructions/program codes corresponding to the memory management method may be implemented as hardware-form circuit units to implement the memory management method provided by the present invention.

It should be noted that, in the present embodiment, the Processor 110 and the Processor 211 are, for example, a central processing unit (Central Processing Unit, CPU), a Microprocessor (micro-Processor), or other programmable processing units (micro Processor), a digital signal Processor (DIGITAL SIGNAL Processor, DSP), a programmable controller, an Application SPECIFIC INTEGRATED Circuits (ASIC), a programmable logic device (Programmable Logic Device, PLD), or other similar circuit components, which are not limited to this embodiment.

In the present embodiment, as described above, the memory controller 210 further includes the data management circuit 212 and the memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 may also be considered operations performed by the memory controller 210.

The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is configured to receive the instruction from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., host memory 120) via the connection interface circuit 230, and the read data is written into the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (e.g., write operations are performed according to write instructions from the host system 10). For another example, data is read from one or more physical units of the rewritable nonvolatile memory module 220 via the memory interface control circuit 213 (data may be read from one or more memory units in the one or more physical units), and the read data is written into the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., a read operation is performed according to a read instruction from the host system 10). In another embodiment, the data management circuit 212 may also be integrated into the processor 211.

The memory interface control circuit 213 is used for receiving the instruction of the processor 211, and performs a write (also called Programming) operation, a read operation or an erase operation on the rewritable nonvolatile memory module 220 in cooperation with the data management circuit 212.

In one embodiment, the memory interface control circuit 213 includes a plurality of chip enable pin control circuits. The Chip Enable pin control circuits respectively correspond to Chip Enable pins (also referred to as CEs) of a plurality of chips in the rewritable nonvolatile memory module 220, and are used for controlling enabling and disabling of the corresponding chips. In this way, the memory interface control circuit 213 may enable selective access to different chips.

In addition, the data to be written into the rewritable nonvolatile memory module 220 is converted into a format acceptable to the rewritable nonvolatile memory module 220 by the memory interface control circuit 213. Specifically, if the processor 211 is to access the rewritable nonvolatile memory module 220, the processor 211 transmits a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code, a memory address, and a physical address.

In addition, the memory controller 210 establishes a Logical To PHYSICAL ADDRESS MAPPING table and a physical To Logical address mapping table (Physical To Logical ADDRESS MAPPING table) To record the mapping relationship between the Logical addresses of the Logical units (e.g., logical blocks, logical pages) and the physical addresses (physical addresses) of the physical units (e.g., physical erase units/physical blocks, physical pages) allocated To the rewritable nonvolatile memory module 220. In other words, the memory controller 210 may search for an entity unit mapped by a logical unit (e.g., search for an entity page mapped by a logical page; search for an entity address mapped by a logical address) through a logical-to-entity address mapping table (also referred to as a logical-to-entity mapping table), and the memory controller 210 may search for a logical unit mapped by a physical unit (e.g., search for a logical page mapped by a physical page; search for a logical address mapped by a physical address) through a physical-to-logical address mapping table (also referred to as a physical-to-logical mapping table).

In one embodiment, memory controller 210 also includes a buffer memory 214. The buffer memory 214 is electrically connected to the processor 211 for temporarily storing data and instructions from the host system 10, data from the rewritable nonvolatile memory module 220, or other system data for managing the memory device 20. In addition, the buffer memory 214 may be used to store various mapping tables (e.g., a logical-to-physical address mapping table and a physical-to-logical address mapping table) to allow the processor 211 to quickly access the data, instructions, or system data from the buffer memory 214.

In one embodiment, to ensure the reliability of the mapping table data, the memory controller 210 performs an Error correction Code (RAID ECC) protection mechanism of the redundant array of independent disks (RAID ECC) on the mapping table data before the memory controller 210 writes the mapping table data to the rewritable nonvolatile memory module 220. Specifically, the memory controller 210 generates corresponding check pages based on the mapping table data and stores the mapping table data and the check page distribution in different chips of the rewritable nonvolatile memory module 220. In this way, even if a chip fails, the memory controller 210 can reconstruct the mapping table data stored in the failed chip from the mapping table data stored in other chips and the corresponding check pages.

In one embodiment, the buffer memory 214 is divided into a plurality of buffer areas, including a mapping table buffer area dedicated to temporarily storing mapping table data to be encoded and a check data buffer area dedicated to temporarily storing encoded check data. Such region division contributes to improvement of processing efficiency of the map data.

The rewritable nonvolatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213) and is used for storing user data sent by the host system 10.

In the present embodiment, each memory die (chip) of the plurality of memory dies of the rewritable nonvolatile memory module 220 has a plurality of planes (e.g., P planes for each chip enable pin), and each Plane has a plurality of physical blocks. Each entity block includes a plurality of entity programming units (also referred to as entity pages). Each physical page has a plurality of memory locations (also referred to as physical bytes or bytes), each memory location corresponding to a physical address. The physical address is used to record the physical location of the data stored in the memory location. It should be noted that the present invention is not limited to the size of each physical page and logical page.

FIG. 2 is a flow chart of a memory management method shown according to one embodiment of the present disclosure.

Referring to fig. 2, in step S210, the memory controller 210 acquires map data to be stored. Specifically, the memory controller 210 may retrieve mapping table data to be stored from the buffer memory 214. The mapping table data comprises a logical-to-physical address mapping table and a physical-to-logical address mapping table. However, the present memory management method can be applied to other kinds of mapping tables or various system data that need to be properly protected.

Next, in step S220, the memory controller 210 determines the size of the array memory group according to the total number N of the plurality of chip enable pins (CEs). The array memory set includes a plurality of physical pages corresponding to M chip enable pins, where M is less than N and greater than 1, and M is equal to N minus a predetermined value. In an embodiment, the predetermined value may be formulated according to requirements, for example, 1. The predetermined value is set so that a plurality of array memory groups arranged in succession can be staggered, so that the check pages of the adjacent array memory groups do not belong to the same chip enable pin.

It should be noted that, in order to make the plurality of array storage groups arranged in succession staggered, when the total number N of the chip enable pins (CEs) is even, the number of the array storage groups corresponding to the M chip enable pins is a divisor of N, and there is a remainder, i.e., N cannot be divided by M, so that the array storage groups are staggered as much as possible.

In step S230, the memory controller 210 sets a plurality of array memory groups sequentially arranged based on the word line order, the chip enable pin order, and the plane order. The memory controller 210 causes the plurality of physical pages of each array memory set to correspond to different planes of the M chip enable pins, respectively. The plane sequence is from the 0 th plane to the P-1 st plane in the same chip enable pin.

For example, in one embodiment, the memory controller 210 sets a plurality of array memory banks arranged one after the other based on the word line order, the chip enable pin order, and the plane order. Specifically, the memory controller 210 first selects a first array memory group to be set in order of sequence numbers of the plurality of array memory groups. Such sequence number order may ensure that the array memory set setting process proceeds in order.

In another embodiment, the memory controller 210 selects the available first word line from the rewritable nonvolatile memory module 220 based on the word line order. Then, the memory controller 210 selects one or more first chip enable pins from the plurality of chip enable pins corresponding to the first word line based on the chip enable pin order. The chip enable pin sequence may be from smaller number to larger number.

In another embodiment, when the memory controller 210 detects that the number of the selected one or more first chip enable pins is equal to M, the memory controller 210 performs the operation of first, the memory controller 210 obtains a plurality of first physical pages corresponding to the plurality of planes in each first chip enable pin. The memory controller 210 then sets the plurality of first physical pages to the plurality of physical pages of the first array storage group. In this way, the memory controller 210 can complete the setting of the array memory group within a single word line.

In another embodiment, if the memory controller 210 detects that the number of one or more first chip enable pins selected in the first string is less than M (e.g., the corresponding remaining space of the current first string cannot be set to a complete array memory group), the memory controller 210 performs the steps of first selecting the available second string lines ordered after the first string (taking additional space from the next string to make up the first string-insufficient space). Next, the memory controller 210 selects one or more second chip enable pins from the plurality of chip enable pins corresponding to the second word line based on the chip enable pin order. Wherein the memory controller 210 ensures that the total number of the one or more first chip enable pins and the one or more second chip enable pins is M.

Then, the memory controller 210 obtains a plurality of first physical pages corresponding to the planes in each of the first chip enable pins, and obtains a plurality of second physical pages corresponding to the planes in each of the second chip enable pins. Finally, the memory controller 210 sets the plurality of first physical pages and the plurality of second physical pages as the plurality of physical pages of the first array storage set. In this way, the memory controller 210 can complete the setting of the array memory group in a range spanning adjacent word lines.

Through the above embodiments, the memory management method provided by the present disclosure may flexibly set the array memory group in a single word line or in a range crossing adjacent word lines according to practical situations.

In step S240, the memory controller 210 stores the mapping table data into the plurality of array storage groups. Specifically, the plurality of physical pages of each array storage group includes a plurality of data pages to store partial mapping table data corresponding to the array storage group and a check page to store check data corresponding to the partial mapping table data. It is noted that the check pages of two adjacent array memory banks each correspond to a different chip enable pin.

By the memory management method, the data of the mapping table can be uniformly distributed and stored, and the problem that the reading efficiency is reduced possibly caused by concentrated storage of the check pages in a traditional mode is effectively avoided.

In one embodiment, the process by which the memory controller 210 generates the check data for the mapping table data is as follows.

Specifically, the memory controller 210 first divides the partial mapping table data to be stored into a plurality of data units. The memory controller 210 then performs an exclusive or (XOR) operation on the data units based on an error correction code algorithm of the redundant array of independent disks, thereby generating corresponding check data. Wherein the check data has the same size as the single data unit, and the check data contains redundant information for recovering the partial mapping table data.

In another embodiment, the memory controller 210 encodes the generated parity data before writing the parity data to the parity page. Specifically, the memory controller 210 encodes the check data using an error correction code encoding technique, such as a Low density parity check code (Low DENSITY PARITY CHECK, LDPC), to improve the reliability of the check data itself. With this double protection mechanism, even if the check data itself is partially erroneous, the memory controller 210 can recover the correct check data through the error correction code, thereby ensuring the reliability of the mapping table data.

FIG. 3 is a schematic diagram of setting array memory banks by conventional method. In one embodiment, referring to fig. 3, a conventional array storage set arrangement is shown.

In this embodiment, the configuration of the memory controller 210 for the array memory banks has the feature that the total number of chip enable pins is 4 (n=4), with 4 chip enable pins (m=4=n) for each array memory bank.

Specifically, each wordline (e.g., SG0, SG1, SG 2) includes 4 chip enable pins (CE 0, CE1, CE2, CE 3), and each chip enable pin corresponds to 2 planes (PL 0, PL 1). The memory controller 210 fixedly sets the check page of each array memory group (e.g., REG01, REG02, REG 03) in the physical page of the last chip enable pin CE 3. For example, in the string line SG0, the check page of the array memory group REG01 is set in the physical page PG031 of the chip enable pin CE 3.

In another embodiment, when this conventional approach is adopted, the memory controller 210 sets the array memory group in such a manner that, first, the memory controller 210 sets the physical pages (from the physical pages PG000 to PG021, also referred to as data pages) corresponding to the chip enable pins CE0 to CE2 as the data pages of the array memory group REG01 and sets the physical page PG031 corresponding to the chip enable pin CE3 as the check page of the array memory group REG01 in the word string line SG 0. Next, the memory controller 210 sets the array memory group REG02 in the same manner in the word string line SG1, and so on.

However, this conventional arrangement has the following technical drawbacks:

In one embodiment, since the check page is always fixed in the last chip enable pin CE3, when an abnormal condition such as power down occurs, the memory controller 210 needs to supplement the virtual page at a position before the chip enable pin CE 3. This results in valid mapping table data being centrally stored in the front chip enable pins (e.g., CE0, CE 1) and the rear chip enable pins (e.g., CE2, CE 3) then storing mainly virtual pages or check pages.

In another embodiment, such an uneven data distribution may cause a significant decrease in read efficiency. Because the parallel read capability of multiple chip enable pins is not fully utilized when the memory controller 210 needs to read the mapping table data, a large number of read operations are forced to be concentrated on the few chip enable pins in front, resulting in a read performance bottleneck.

These technical drawbacks highlight the limitations of conventional array storage group arrangements in practical applications and also illustrate the necessity of developing new storage management methods.

Fig. 4 is a schematic diagram illustrating setting array storage groups via a provided memory management method according to one embodiment of the present disclosure. In an embodiment, please refer to fig. 4, which illustrates an improved array storage group configuration provided in the present disclosure.

In this embodiment, the memory controller 210 employs an innovative configuration strategy in which the total number of chip enable pins is 4 (n=4), but each array memory bank corresponds to only 3 chip enable pins (N minus a predetermined value of 1))。

For example, the memory controller 210 configures the array memory groups REG11 to REG14 as follows:

The array memory group REG11 is configured in such a manner that the memory controller 210 sets the physical pages (from PG000 to PG 021) corresponding to the chip enable pins CE0, CE1, CE2 in the word string line SG0 as the constituent parts of the array memory group REG11, wherein the physical page PG021 is set as the check page.

In one embodiment, the memory controller 210 may employ two ways in configuring the physical page distribution of the array memory group, the first way being to all correspond the physical pages of the array memory group to the chip enable pins of the same word line, and the second way to allocate the physical pages of the array memory group to the chip enable pins of adjacent word lines. The memory controller 210 may select an appropriate manner to configure the array memory banks based on the actual memory conditions.

Specifically, the memory controller 210 considers the memory capacity of each word line. Since each chip enable pin corresponds to P planes and there are N chip enable pins on the word line, each word line includes NP physical pages. For example, when N is 4 and P is 2, each wordline may include 8 physical pages. The memory controller 210 will program the distribution of the array memory banks based on this fixed memory capacity, ensuring that the physical page allocation does not exceed the capacity limit of the word lines.

Returning to the configuration of the array memory group REG12, the array memory group REG12 is configured in such a way that the memory controller 210 spans the word string lines SG0 and SG1, and sets the physical pages (from PG030 to PG 111) corresponding to the chip enable pins CE3 in the word string line SG0 and the chip enable pins CE0 and CE1 in the word string line SG1 as the constituent parts of the array memory group REG12, wherein the physical pages PG111 are set as the check pages.

In more detail, the memory controller 210 performs the following detailed steps when setting the array memory group REG 12:

first, the memory controller 210 selects the array memory group REG12 as the array memory group to be set after the setting of REG11 is completed in the order of the sequence numbers of the array memory groups. Next, the memory controller 210 selects the available string line SG0 as the first string line based on the string line order.

Then, the memory controller 210 selects from among the plurality of chip enable pins corresponding to the string line SG0 based on the chip enable pin order. Since the chip enable pins CE0, CE1, CE2 are already occupied by the array memory group REG11, the memory controller 210 can select only the chip enable pin CE3 as the first chip enable pin. At this time, the memory controller 210 detects that the number (1) of first chip enable pins selected in the string line SG0 is smaller than M (m=3).

Accordingly, the memory controller 210 selects the string line SG1, which is ordered after the string line SG0, as the second string line. The memory controller 210 continues to select an available second chip enable pin from the plurality of chip enable pins corresponding to the wordline SG1 based on the chip enable pin order. Specifically, the memory controller 210 selects the chip enable pins CE0 and CE1 as the second chip enable pins, such that the total number of the first chip enable pins (CE 3) and the second chip enable pins (CE 0, CE 1) is M (m=3).

Next, the memory controller 210 obtains a plurality of first physical pages (i.e., PG030, PG 031) corresponding to the plurality of planes in the first chip enable pin CE3, and obtains a plurality of second physical pages (i.e., PG100, PG101, PG110, PG 111) corresponding to the plurality of planes in the second chip enable pins CE0 and CE 1. Finally, the memory controller 210 sets these first and second physical pages collectively as a plurality of physical pages of the array memory group REG12, and sets the physical page PG111 therein as a check page.

By analogy, the array memory group REG13 is configured in such a way that the memory controller 210 spans the word lines SG1 and SG2, and sets the physical pages (from the physical pages PG120 to PG 201) corresponding to the chip enable pins CE2, CE3 and CE0 in the word line SG1 as the constituent parts of the array memory group REG13, wherein the physical page PG201 is set as the check page.

The array memory group REG14 is configured in such a way that the memory controller 210 sets the physical pages (using the remaining available physical pages PG210-PG 231) corresponding to the chip enable pins CE1, CE2, CE3 in the string line SG2 as the constituent parts of the array memory group REG14, wherein the physical page PG231 is set as the check page.

It is worth mentioning that the innovative configuration has the advantage that firstly, since the check page position of each array memory group is different, the valid mapping table data can be stored in different chip enable pins in a scattered manner even if the virtual page needs to be supplemented in the case of power failure. For example, the check page of array memory group REG11 is located at chip enable pin CE2, the check page of REG12 is located at chip enable pin CE1, the check page of array memory group REG13 is located at chip enable pin CE0, and the check page of array memory group REG14 is located at chip enable pin CE3.

Second, the memory controller 210 can prevent data in the same array memory group from being stored in the same chip enable pins corresponding to different word lines by limiting the range of the array memory group to M (m=3) chip enable pins, thereby ensuring that data in the same array memory group is not lost too much even if a chip fails, and improving the reliability of the data. If the range of the array storage group is assumed to be 5, the entity pages in SG0 and SG1 corresponding to CE0 will store data belonging to the same array storage group, and when the chip corresponding to CE0 is abnormal, more data will be lost, so that the data cannot be corrected again.

Finally, the cross-word string configuration mode enables the memory controller 210 to fully utilize the parallel reading capability of a plurality of chip enable pins, thereby significantly improving the reading efficiency of the mapping table data.

In one embodiment, the memory controller 210 employs a serial configuration across the word lines in managing the order of the chip enable pins. Specifically, after the memory controller 210 completes accessing the last chip enable pin of the ith wordline, it automatically switches to the first chip enable pin of the (i+1) th wordline, thereby realizing continuous access of the chip enable pins.

Through the configuration mode, the memory management method provided by the disclosure can ensure the effective utilization of the memory space and realize the flexible distributed storage of the mapping table data. The memory controller 210 is able to efficiently manage and allocate physical page resources, whether within a single wordline or across adjacent wordlines.

In one embodiment, the memory controller 210 employs a particular check page layout policy in configuring each array storage group. Specifically, the memory controller 210 sets the check page of each array storage group to the last physical page of the plurality of physical pages of the array storage group.

In another embodiment, the memory controller 210, when setting the check page position of the array memory set, performs the following operation steps, firstly, the memory controller 210 confirms the total number of physical pages contained in the array memory set, wherein the physical pages include data pages for storing mapping table data and check pages for storing check data. The memory controller 210 then designates the physical page with the largest sequence number as the check page for the array memory bank. For example, if an array memory set contains M physical pages, then the Mth physical page will be designated as a check page, and the 1 st through (M-1) th physical pages will be used as data pages.

With this fixed parity page layout strategy, the memory controller 210 can quickly locate where parity data is stored when data recovery is performed. This arrangement not only simplifies the data management operation of the memory controller 210, but also improves the access efficiency of the parity data. In addition, the memory controller 210 may perform the writing and restoring operations of the mapping table data more efficiently due to the certainty of checking the page position.

In another embodiment, the memory controller 210 may employ a round robin check page allocation policy. Specifically, the memory controller 210 loops based on the numbered order of the chip enable pins, sequentially designating the physical pages in different chip enable pins as check pages.

For example, the memory controller 210 may perform a check page allocation step in which, for a first array memory group, the memory controller 210 selects a last physical page in its corresponding last chip enable pin as a check page, for a second array memory group, the memory controller 210 selects a last physical page in its corresponding first chip enable pin as a check page, and for a third array memory group, the memory controller 210 selects a last physical page in its corresponding second chip enable pin as a check page.

With this round-robin parity page allocation policy, the memory controller 210 not only ensures that parity pages of adjacent array memory groups are not located on the same chip enable pin, but also achieves a balanced distribution of parity pages among the chip enable pins. In addition, the regularity of this allocation policy also facilitates quick positioning and access of check page locations by memory controller 210.

In one embodiment, the memory controller 210 has a mapping table data reconstruction function. Specifically, when the memory controller 210 detects that the target chip fails, a mechanism for rebuilding the mapping table data is triggered.

In another embodiment, the memory controller 210 performs the specific steps of mapping table data reconstruction by first, the memory controller 210 identifies an array memory set containing the target chip. Since the plurality of physical pages of each array memory bank correspond to M different chip enable pins, respectively, the memory controller 210 can determine which array memory banks are affected by the target chip failure.

The memory controller 210 then performs a data reconstruction operation separately for each affected array storage group. Specifically, the memory controller 210 first reads the complete mapping table data from the non-failed chip in the array memory set. Meanwhile, the memory controller 210 reads the check data from the corresponding check page.

In another embodiment, the memory controller 210 performs an exclusive or (XOR) operation with the parity data based on an error correction code algorithm of the redundant array of independent disks, thereby reconstructing the target portion map data stored in the target chip. For example, if the array memory set includes three data pages (D1, D2, D3) and one check page (P), and D2 is stored in the failed target chip, the memory controller 210 may calculateTo reconstruct D2.

In another embodiment, the memory controller 210 performs a data verification step after the data reconstruction is completed. Specifically, the memory controller 210 calculates the check code of the reconstructed data again and compares the check code with the original check data to ensure the accuracy of the reconstructed mapping table data. If the verification is passed, the memory controller 210 will store the reconstructed mapping table data in the buffer memory 214 for subsequent use.

Through the mapping table data reconstruction mechanism, the memory management method provided by the disclosure not only realizes reliable storage of data, but also ensures the data recovery capability under the condition of chip faults, thereby improving the reliability and stability of a memory system. Even if one chip fails, the memory controller 210 can reconstruct and recover critical mapping table data from the data and verification information in the other chips.

The present embodiment also provides a computer program product comprising computer readable code, or a non-transitory computer readable storage medium carrying computer readable code, which when executed in a processor, performs the steps of the above memory management method. The computer program product may be embodied in hardware, firmware, software, or a combination thereof. In an alternative embodiment, the computer program product is embodied as a computer storage medium, and in another alternative embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), or the like.

Based on the above, the memory management method and the memory controller provided by the present disclosure have the following advantages:

the size of the array storage group is determined according to the total number of the plurality of chip enabling pins, wherein the array storage group comprises a plurality of entity pages corresponding to the chip enabling pins with the number smaller than the total number, and the check pages can be effectively prevented from being stored in the last chip enabling pin in a concentrated mode, so that the storage distribution uniformity of mapping table data is improved.

By setting a plurality of array memory groups which are sequentially arranged based on the word line sequence, the chip enable pin sequence and the plane sequence, a plurality of entity pages of each array memory group respectively correspond to different planes of different chip enable pins, even distribution of mapping table data in a physical memory space can be ensured, and reading bottlenecks caused by centralized data storage are avoided.

By corresponding the respective check pages of the two array storage groups which are adjacently arranged to different chip enable pins, even if virtual pages are required to be supplemented under the condition of power failure, effective data can be ensured to be stored in different chips in a scattered manner, so that higher parallel reading efficiency is maintained, and meanwhile, the protection intensity of mapping table data is not influenced.

It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.

Claims (16)

1. A memory management method adapted for a memory device configured with a rewritable nonvolatile memory module including a plurality of chips each corresponding to a chip enable pin, each chip including P planes, the method comprising:

Acquiring mapping table data to be stored;

Determining a fixed size of each array storage group according to a total number N of the plurality of chip enable pins, wherein the array storage group comprises a plurality of physical pages corresponding to M chip enable pins, wherein M is less than N and greater than 1, and M is equal to N minus a predetermined value;

Setting a plurality of array memory groups sequentially arranged based on the word line sequence, the chip enable pin sequence and the plane sequence, wherein the plurality of physical pages of each array memory group respectively correspond to different planes of the M chip enable pins, and

Storing the mapping table data into the plurality of array storage groups, wherein the plurality of physical pages of each array storage group comprises a plurality of data pages and a check page, wherein the plurality of data pages are used for storing partial mapping table data corresponding to the array storage groups, and the check page is used for storing check data corresponding to the partial mapping table data, wherein the check page of each array storage group has a predetermined fixed position within the array storage group,

Wherein the check pages of two adjacent array memory groups correspond to different chip enable pins.

2. The memory management method according to claim 1, wherein the step of setting the plurality of array memory groups arranged successively based on the word line order, the chip enable pin order, and the plane order includes:

Selecting a first array storage group to be set according to the sequence numbers of the plurality of array storage groups;

selecting an available first wordline based on the wordline sequence;

selecting one or more available first chip enable pins from a plurality of chip enable pins corresponding to the first word line based on the chip enable pin order;

if the number of the one or more first chip enable pins is equal to M:

acquiring a plurality of first entity pages corresponding to the P planes in each first chip enable pin, and

The plurality of first physical pages is set as the plurality of physical pages of the first array storage set.

3. The memory management method according to claim 2, wherein the step of setting the plurality of array memory groups arranged successively based on the word line order, the chip enable pin order, and the plane order further comprises:

If the number of the one or more first chip enable pins selected in the first wordline is less than M:

selecting an available second wordline ordered after the first wordline;

selecting one or more available second chip enable pins from the plurality of chip enable pins corresponding to the second word line based on the chip enable pin order, wherein a total number of the one or more first chip enable pins and the one or more second chip enable pins is M;

acquiring a plurality of first entity pages corresponding to the P planes in each first chip enable pin, and acquiring a plurality of second entity pages corresponding to the P planes in each second chip enable pin, and

The plurality of first physical pages and the plurality of second physical pages are set as the plurality of physical pages of the first array storage set.

4. The memory management method of claim 1, wherein the check page of each array storage group is a last one of the plurality of physical pages of the array storage group.

5. The memory management method according to claim 1, wherein if N is an even number, there is a remainder when M is a divisor of N.

6. The memory management method according to claim 1, wherein the predetermined value is 1.

7. The memory management method according to claim 1, wherein the chip enable pin following the last chip enable pin of the ith word line is the first chip enable pin of the (i+1) th word line, wherein the plurality of physical pages of each array memory group corresponds to the plurality of chip enable pins of the same word line or to the plurality of chip enable pins of adjacent word lines,

Wherein each word line includes NP physical pages.

8. The memory management method according to claim 1, characterized in that the method further comprises:

if the target chip fails, reconstructing target part mapping table data stored in the target chip according to the part mapping table data stored in other chips except the target chip and the corresponding verification data.

9. A memory controller for controlling a memory device configured with a rewritable non-volatile memory module, the memory controller comprising:

A memory interface control circuit for electrically connecting to the rewritable nonvolatile memory module, the rewritable nonvolatile memory module including a plurality of chips each corresponding to a chip enable pin, each chip including P planes, and

A processor electrically connected to the memory interface control circuit, wherein the processor is further electrically connected to the connection interface circuit of the memory device to be electrically connected to a host system,

Wherein the processor is configured to:

Acquiring mapping table data to be stored;

Determining a fixed size of each array storage group according to a total number N of the plurality of chip enable pins, wherein the array storage group comprises a plurality of physical pages corresponding to M chip enable pins, wherein M is less than N and greater than 1, and M is equal to N minus a predetermined value;

Setting a plurality of array memory groups sequentially arranged based on the word line sequence, the chip enable pin sequence and the plane sequence, wherein the plurality of physical pages of each array memory group respectively correspond to different planes of the M chip enable pins, and

Storing the mapping table data into the plurality of array storage groups, wherein the plurality of physical pages of each array storage group comprises a plurality of data pages and a check page, wherein the plurality of data pages are used for storing partial mapping table data corresponding to the array storage groups, and the check page is used for storing check data corresponding to the partial mapping table data, wherein the check page of each array storage group has a predetermined fixed position within the array storage group,

Wherein the check pages of two adjacent array memory groups correspond to different chip enable pins.

10. The memory controller of claim 9, wherein the step of setting the plurality of array memory banks in successive arrangement based on the word line order, the chip enable pin order, and the plane order comprises:

Selecting a first array storage group to be set according to the sequence numbers of the plurality of array storage groups;

selecting an available first wordline based on the wordline sequence;

selecting one or more available first chip enable pins from a plurality of chip enable pins corresponding to the first word line based on the chip enable pin order;

if the number of the one or more first chip enable pins is equal to M:

acquiring a plurality of first entity pages corresponding to the P planes in each first chip enable pin, and

The plurality of first physical pages is set as the plurality of physical pages of the first array storage set.

11. The memory controller of claim 10, wherein the step of setting the plurality of array memory banks in successive arrangement based on the word line order, the chip enable pin order, and the plane order further comprises:

If the number of the one or more first chip enable pins selected in the first wordline is less than M:

selecting an available second wordline ordered after the first wordline;

selecting one or more available second chip enable pins from the plurality of chip enable pins corresponding to the second word line based on the chip enable pin order, wherein a total number of the one or more first chip enable pins and the one or more second chip enable pins is M;

acquiring a plurality of first entity pages corresponding to the P planes in each first chip enable pin, and acquiring a plurality of second entity pages corresponding to the P planes in each second chip enable pin, and

The plurality of first physical pages and the plurality of second physical pages are set as the plurality of physical pages of the first array storage set.

12. The memory controller of claim 9, wherein the check page of each array storage group is the last of the plurality of physical pages of the array storage group.

13. The memory controller of claim 9, wherein if N is even, then M is a divisor of N with a remainder.

14. The memory controller of claim 9, wherein the predetermined value is 1.

15. The memory controller of claim 9, wherein the chip enable pin following the last chip enable pin of the ith wordline is the first chip enable pin of the (i+1) th wordline, wherein the plurality of physical pages of each array memory group corresponds to the plurality of chip enable pins of the same wordline or to the plurality of chip enable pins of adjacent wordlines,

Wherein each word line includes NP physical pages.

16. The memory controller of claim 9, wherein the processor is further configured to:

if the target chip fails, reconstructing target part mapping table data stored in the target chip according to the part mapping table data stored in other chips except the target chip and the corresponding verification data.