CN119903008B

CN119903008B - Bus expansion device and data processing method

Info

Publication number: CN119903008B
Application number: CN202510081198.9A
Authority: CN
Inventors: 苏振宇
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2025-01-17
Filing date: 2025-01-17
Publication date: 2025-11-25
Anticipated expiration: 2045-01-17
Also published as: CN119903008A

Abstract

The application relates to the technical field of electronic information, in particular to a bus expansion device and a data processing method, wherein the bus expansion device comprises a bus expansion module, a bus processing module and a data processing module, wherein the bus expansion module is configured to be connected with a target bus; the bus expansion module is configured to interact with a target bus with a data signal with a first width, and generate a first target data signal based on the data signal with the first width, or generate a data signal with the first width based on an acquired second target data signal, wherein the data width of the first target data signal is the first target width, the data width of the second target data signal is the second target width, and the first target width is equal to or greater than the first width, and the second target width is greater than or equal to the first width. Based on the bus expansion module, the width of the target bus can be expanded, the control of the module of the data bus with the data width larger than the first width is realized, the problem of application limitation is solved, and the technical effect of flexible application is achieved.

Description

Bus expansion device and data processing method

Technical Field

The application relates to the technical field of electronic information, in particular to a bus expansion device and a data processing method.

Background

The Low Pin Count (LPC) bus is a parallel bus with Low Pin number, and is composed of 13 signal wires, wherein 7 necessary signals and 6 optional signals, and LPC communication can be realized only by 7 necessary signals, so that the implementation mode is flexible. However, the limitation of data width based on the LPC bus or other similar buses can only realize the operation of the device corresponding to the data width, resulting in application limitation.

Disclosure of Invention

The application provides a bus expansion device and a data processing method, which at least solve the problem of bus application limitation caused by data width in the related art.

According to a first aspect, the present application provides a bus extension apparatus configured in a server, the bus extension apparatus comprising:

The bus extension module is configured to interact with the target bus to generate a first target data signal based on the data signal with the first width or generate the data signal with the first width based on an acquired second target data signal;

the data width of the first target data signal is a first target width, the data width of the second target data signal is a second target width, the first target width is equal to or greater than the first width, and the second target width is greater than or equal to the first width.

According to a second aspect, the present application provides a data processing method, executed based on the bus extension apparatus provided in the first aspect, the data processing method comprising:

acquiring a data signal with a first width transmitted by the target bus;

Generating a first target data signal based on the data signal having a first width, the first target data signal having a data width that is a first target width, the first target width being equal to or greater than the first width;

Or alternatively

Acquiring a second target data signal;

A data signal having a first width is generated based on the second target data signal, the data width of the second target data signal being a second target width, the second target width being greater than or equal to the first width.

According to the application, the bus expansion module connected with the target bus is arranged in the bus expansion device, the bus expansion module interacts with the target bus to form a data signal with a first width, the first target data signal can be generated based on the data signal with the first width, the data width of the first target data signal is larger than or equal to the first width, or the data signal with the first width is generated based on the acquired second target data signal, and the data width of the second target data signal is larger than or equal to the first width, so that the width of the target bus can be expanded based on the bus expansion module, the control of the data bus module with the data width larger than the first width is realized, the problem of application limitation is solved, and the technical effect of flexible application is achieved.

Drawings

FIG. 1 is a LPC interface scheme in the related art;

FIG. 2 is a schematic diagram of an application architecture of a bus extension device according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a bus extension device according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a second bus expansion device according to an embodiment of the present application;

FIG. 5 is a schematic diagram III of a bus extension device according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a bus extension device according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a bus extension device according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a bus extension device according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a bus extension device according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a bus extension device according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a bus extension device according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a state transition flow of an algorithm state machine of a bus extension device according to an embodiment of the present application;

FIG. 13 is a schematic diagram showing a bus extension apparatus according to an embodiment of the present application;

FIG. 14 is a schematic diagram of a bus extension device according to an embodiment of the present application;

FIG. 15 is a schematic diagram showing a bus extension device according to an embodiment of the present application;

FIG. 16 is a second schematic diagram of an application architecture of a bus extension device according to an embodiment of the present application;

FIG. 17 is a flowchart of a data processing method according to an embodiment of the present application;

FIG. 18 is a second flow chart of a data processing method according to an embodiment of the application;

Fig. 19 is a flowchart of a data processing method according to an embodiment of the application.

Detailed Description

The application provides a bus expansion device and a data processing method, which are used for expanding the data width of a data signal of a target bus and realizing the control of a module of the data bus with the data signal width larger than the data width of the target bus so as to improve the application flexibility.

In some implementations, the module with the high-speed clock signal can also be controlled by clock multiplication by using a low-speed target bus to increase the speed of data processing.

In some implementations, a cryptographic control module may also be provided to promote security during data communications.

In some implementations, the bus expansion device can be set based on a programmable logic device, so that the deployment is flexible and the implementation is convenient.

The technical solutions provided by the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

Fig. 1 is a LPC interface scheme in the related art. As shown in FIG. 1, the LPC bus is located under a south bridge chip (PCH) of a server/a Computer (CPU), and a module with an LPC interface such as a TPM (Trusted Platform Module )/TCM (Trusted Cryptography Module, trusted cryptography module) can be used as an LPC device and inserted into an LPC slot on a motherboard to communicate with the south bridge chip (PCH). Since the LPC bus has only 4bit data bus, the server/computer can only control the LPC device with 4bit data width (such as TPM/TCM) through the LPC bus, but cannot control the IO (Input Output) device/module with data width exceeding 4bit, such as 16bit, 32bit, 64bit IO device/module, etc., thus resulting in application limitation.

In view of the above, the embodiment of the application provides a bus expansion device and a data processing method, which break application limitation based on expansion of data width. The application limitation caused by the data width is described only by taking the LPC bus as an example, and the application limitation caused by the data width of other buses can be improved by adopting the technical scheme provided by the embodiment of the application, which is not limited herein.

Fig. 2 is a schematic diagram of an application architecture of a bus extension device according to an embodiment of the present application. As shown in fig. 2, the bus extension device 100 provided in the embodiment of the present application is configured in the server 10. The bus extension device 100 may be connected between the target bus 01 and the server 10, or the bus extension device 100 may be disposed within the server 10 (as in fig. 2), for example, without limitation. One end of the bus extension device 100 is connected to the host computer 20 via the target bus 01, and the other end is connectable to the cryptographic module 30. The upper computer 20 may include upper application software operated by a user, and the user may set a key, a register, data to be operated, etc. based on the operation of the upper computer 20, and send the data to the bus extension device 100 through the target bus 01, and may receive data returned by the bus extension device 100 after the operation is completed. The bus extension device 100 extends the data transmitted from the target bus 01 to data of a width corresponding to the cryptographic module 30, and transmits the data to the cryptographic module 30. The cryptographic module 30 performs an operation on the received data and returns the operation-completed data to the bus extension device 100, the bus extension device 100 performs data conversion on the received operation-completed data, outputs data having a data width that satisfies the transmission data width of the target bus 01, and returns the operation-completed data to the host computer 20 via the target bus 01.

Fig. 3 is a schematic structural diagram of a bus extension device according to an embodiment of the present application. As shown in fig. 3, the bus extension device 100 provided by the embodiment of the application may include a bus extension module 110 configured to be connected to a target bus 01, where the bus extension module 110 is configured to interact with the target bus 01 and generate a first target data signal based on the data signal having a first width, or generate a data signal having a first width based on an acquired second target data signal, where the data width of the first target data signal is a first target width and the data width of the second target data signal is a second target width, and the first target width is equal to or greater than the first width and the second target width is greater than or equal to the first width.

The target bus 01 may be a bidirectional data/address bus having a data width, which may be represented as a first width. It will be appreciated that the first width is smaller, and the control of the module/device having a larger number of bits of data width can be achieved by performing data width expansion on the data signal transmitted by the target bus 01 based on the bus expansion device 100. By way of example, target bus 01 may be an LPC bus or other low-bit data width bus, not limited herein.

The bus extension module 110 is connected to the target bus 01, and is capable of receiving a data signal having a first width transmitted by the target bus 01 or outputting a data signal having the first width to the target bus 01. Further, the bus extension module 110 can perform data extension based on the received data signal having the first width, and generate a first target data signal having the first target width, so as to implement control of the module/device having the first target width. Or the bus extension module 110 can acquire a second target data signal having a second target width transmitted by a module/device having the second target width, and convert the second target data signal into at least one data signal having the first width and transmit the data signal through the target bus 01, thereby implementing control of the module/device having the second target width through the target bus 01.

The first target width and the second target width may be the same or different, and are not limited herein. When the second target width is the same as the first target width, the modules/devices controlled based on the target bus may be the same module/device, which is not limited herein.

In some implementations, when the first target width and the second target width are both equal to the first width, control of the module/device having the first width may be implemented based on the target bus such that the setting of the bus extension apparatus 100 does not affect control of the module/device having the first width.

In some implementations, when the first target width is greater than the first width and the second target width is greater than the first width, control of the module/device having the larger data width may be implemented based on the target bus and the bus extension apparatus 100, thereby breaking the application limitations of the target bus.

The bus extension device 100 provided by the embodiment of the application comprises a bus extension module 110, wherein the bus extension module 110 can receive a data signal with a first width transmitted by a target bus 01 and generate a first target data signal with a first target width, or acquire a second target data signal and generate a data signal with the first width and transmit the data signal through the target bus 01, wherein the first target width is greater than or equal to the first width, and the second target width is greater than or equal to the first width, so that the extension of the data width transmitted by the target bus 01 can be realized, the application limitation of the target bus 01 caused by the limitation of the data width is broken, and the application flexibility of the target bus 01 is improved.

In some implementations, fig. 4 is a schematic diagram of a second structure of a bus extension device according to an embodiment of the present application, where a specific structure of the bus extension module 110 is shown. As shown in fig. 4, in the bus extension device 100 provided by the embodiment of the application, the bus extension module 110 may include a control module 111, a counting module 112, and a first data buffer 113, where the counting module 112 and the first data buffer 113 are respectively connected to the control module 111, the counting module 112 is configured to count data periods of a target bus and transmit the count value to the control module 111, the first data buffer 113 is configured to store data signals of at least one data period transmitted by the target bus, the control module 111 is configured to generate a first target data signal based on the data signals of at least one data period stored in the first data buffer 113, and output a period valid signal of the first target data signal based on the count value reaching the target count value.

The input end of the counting module 112 is connected to the bus cycle signal LFRAME of the target bus 01, and the output end of the counting module 112 is connected to the control module 111. The bus cycle signal LFRAME is a start signal of a data cycle of the 01 target bus, and is active low. Based on this, the bus cycle signal LFRAME is switched to a low level, which indicates that one data cycle is started, and the period during which the bus cycle signal LFRAME is at a low level corresponds to one data cycle. The counting module 112 is capable of counting data cycles of the target bus, each of which transmits a valid data signal LAD 3.0 on the target bus.

Illustratively, the count value may be N (n=1, 2, n.), i.e. N is a positive integer. The target count value may be set by the user based on the data width requirement of the target data signal, i.e., based on the data expansion requirement, and the specific value thereof is not limited herein. When the count value reaches the target count value, the control module 111 outputs a cycle valid signal of the first target data signal, i.e. generates an expanded bus cycle signal, which is shown as FRAME in fig. 4.

Illustratively, when the first width is 4 bits and the first target width is 16 bits, the target count value is 16 bits/4 bits, i.e., the target count value is 4. Based on this, when the count value reaches from 1 accumulation, the target bus transmits 4 data signals LAD [3..0] having the first width, that is, after satisfying 4×4 bit=16 bit, the control module 111 generates an extended bus cycle signal FRAME. Illustratively, the extended bus cycle signal FRAME is active low.

The first data buffer 113 is configured to temporarily store a number of data signals corresponding to a target count value transmitted on the target bus. By way of example, the first data buffer 113 may be a volatile memory unit, such as a random access memory (Random Access Memory, RAM) or other component having a memory function, which is not limited herein.

The capacity of the first data buffer 113 may be set according to the data width expansion requirement, and in different application scenarios, the capacity of the first data buffer 113 may be changed. Illustratively, the capacity of the first data buffer 113 may be set to an integer multiple of the first width to store the data signal LAD [3..0] transmitted by the target bus. For example, the first width is 4 bits, the capacity of the first data buffer 113 may be 4nbit, and n represents the target count value.

The control module 111 is capable of receiving the count value of the count module 112, and outputting an expanded bus cycle signal FRAME based on the count value reaching a target count value; and based on the DATA stored in the first DATA buffer 113, after the DATA splicing, a first target DATA signal DATA [4N-1..0] (n=1, 2, once again, n.). Illustratively, when the first target width is 16 bits, then the target count value n=4, at which time the first target DATA signal may be DATA [15..0].

In the bus extension device 100 provided by the embodiment of the application, the bus extension module 110 comprises the control module 111, the counting module 112 and the first data buffer area 113, the counting module 112 can count the data period of the target bus and transmit the count value to the control module 111, the first data buffer area 113 can store the data signal of at least one data period transmitted by the target bus, the control module 111 can generate the first target data signal based on the data signal of at least one data period stored in the first data buffer area 113 and output the period effective signal of the first target data signal based on the count value reaching the target count value, and therefore data width extension is achieved.

In some implementations, fig. 5 is a schematic diagram of a bus extension device according to an embodiment of the present application, in which a specific structure of the counter is shown. As shown in fig. 5, in the bus extension device provided by the embodiment of the application, the counting module 112 may include an accumulator ADD, and the accumulator ADD counts the data cycles based on the cycle start signal (i.e. the bus cycle signal LFRAME) of the target bus transmission.

When the bus cycle signal LFRAME is at low level, 1 is added to the output terminal Q of the D flip-flop dr_ff_1 with reset to generate a periodic count value cnt [5..0], and when the count value cnt=32, 0 is returned to be effective, the accumulator ADD count is added by 1. Illustratively, when the bus cycle signal is low, the accumulator ADD counts up by 1, producing a periodic count value cnt [5..0] at the output Q of D flip-flop dr_ff_1 with reset. For example, if the target count value is 32, the count range is 1-32, and when the count value reaches 32, the accumulator ADD returns 0 to recount.

In the bus extension device 100 provided by the embodiment of the application, the counting module 112 comprises the accumulator ADD, so that the counting function can be realized based on a simple hardware circuit structure, and the hardware structure is simple.

It should be noted that, in other implementations, the counting module 112 may be implemented based on other structural components with counting functions, which are not described herein again.

In some implementations, fig. 6 is a schematic diagram of a bus extension device according to an embodiment of the present application, where a specific structure of the first data buffer 113 is shown. As shown in fig. 6, in the bus extension device provided by the embodiment of the application, the first data buffer 113 includes at least one first storage unit 1131, and the capacity of the first storage unit 1131 is matched with the first width and is configured to store the data signal of at least one data cycle.

The first data buffer 113 may include a first storage unit 1131, where the first storage unit 1131 may store a data signal having a first width transmitted by the target bus, so that the bus extension apparatus 100 may implement control over the module/device having the first width. Alternatively, the first data buffer 113 may include two or more first memory units 1131, and each memory unit 1131 may store one data signal having a first width transmitted by the target bus, so as to implement splice extension of the data signal. The capacity of the first memory unit 1131 may be equal to the first width to store the data signal having the first width.

Illustratively, the first width is 4 bits, and the capacity of the first memory cell may be 4 bits. The number of first memory units 1131 may be N if the target count value is N, and the data stored in each first memory unit 1131 may be D [4N-1,4N-4] (n=1, 2..times.n) in order to achieve N-fold expansion of the data signal transmitted by the target bus.

In the bus extension device 100 provided in the embodiment of the present application, the first data buffer area 113 may include a number of first storage units 1131 matching the number of the target count values, where each first storage unit 1131 may store the data signals in one data cycle transmitted by the target bus, so as to splice and output the data signals in at least one data cycle stored in the first data buffer area 113, thereby implementing data extension and further improving flexibility of bus application.

In some implementations, with continued reference to fig. 5, in the bus extension apparatus provided by the embodiment of the present application, the control module 111 includes an RS flip-flop rs_ff and a first inverter, where the first inverter is illustrated by a first NOT gate not_14, the data input terminal D of the RS flip-flop rs_f is connected to a first level, the carry terminal C of the RS flip-flop rs_f is connected to a second level, the set terminal S and the clear terminal R of the RS flip-flop rs_f are connected to the counting module 112, the output terminal of the RS flip-flop rs_f is connected to the output terminal of the control module 111 through the first inverter, and the RS flip-flop rs_f outputs a cycle valid signal of the first target data signal, that is, an extended bus cycle signal, based on the count value reaching the target count value.

The first level is a high level, and the second level is a low level. The set terminal S of the RS flip-flop rs_ff is connected to the output terminal of the AND gate and_2, the clear terminal R is connected to the output terminal of the OR gate OR, AND specifically, as shown in fig. 5, the output terminal Q of the rs_ff is connected to the output terminal of the control module through the NOT gate not_14. The data input terminal D of the RS flip-flop rs_ff is connected to a high level, so that the value output by the output terminal Q outputs '0' or '1' according to the values of the set terminal S and the clear terminal R, specifically, q= '0' when r= '1', and q= '1' when s= '1', r= '0'. The carry terminal C of the RS trigger RS_FF is connected with a low level, so that the value of the output terminal Q is not influenced by the carry signal of the carry terminal C. The setting end S of the RS trigger RS_FF is connected to the output end of the AND gate AND_2, AND the zero clearing end R is connected to the output end of the OR gate OR; when the system is reset (lreset= '0 '), the reset signal LRESET transmitted by the target bus is changed into '1' through an NOT_7 AND is input into an OR gate OR to enable the OR gate OR to output '1', at this time, the zero clearing end R of the RS trigger RS_FF is '1', AND the value output by the output end Q is '0'; when the system is in a non-reset state (lreset= '1 '), AND the output of the D flip-flop dr_ff_1 with reset is cnt [5..0] = "100000" (100000 is a binary number, AND the corresponding decimal number is 32), the lower 5 bits cnt [4..0] = "00000" of the cnt are changed to "11111" after passing through the NOT_9 to NOT12, AND then pass through the AND gate and_2, AND then output a high level '1', so that the set terminal s= '1' of the RS flip-flop rs_ff, the highest bits cnt [5] = '1' of the cnt are changed to '0' after passing through the NOT_8, AND are input to the OR gate, AND when in the non-reset state, lreset= '1' is changed to '0' AND then input to the OR gate, at this time, the value of the reset terminal R of the RS flip-flop rs_ff is '0', AND when the output terminal q= '1' of the RS flip-flop rs_ff is changed to '1', AND when the highest bits cnt [5] = '1' is changed to '0', AND when the reset terminal is changed to '1' AND the reset terminal is changed to '1', ' is output to the gate OR, therefore, each time the count value cnt reaches 32, the extended bus cycle signal FRAME generates a low level, and otherwise, the extended bus cycle signal FRAME is high level.

Thus, when the count value reaches the target count value, for example, 32, the output terminal of the control module outputs the extended bus cycle signal FRAME as an active signal, for example, generates a low level, and otherwise outputs the extended bus cycle signal FRAME as an inactive signal, for example, outputs a high level signal.

In the bus extension device 100 provided by the embodiment of the application, the control module 111 is configured to include the RS flip-flop rs_ff and the first inverter, so that the function of outputting the extended bus cycle signal based on the count value reaching the target count value can be realized based on a simple hardware circuit structure, and the hardware structure is simple.

It should be noted that, in other implementations, the control module 111 may be implemented based on other structural components, which are not described herein again.

In some implementations, fig. 7 is a schematic diagram of a bus extension device according to an embodiment of the present application, in which another specific structure of the control module 111 is shown. As shown in fig. 7, in the bus extension device provided by the embodiment of the application, the control module 111 further includes a second inverter and a first D flip-flop d_ff_2, the second inverter is shown as a second NOT gate not_15, the clock end of the first D flip-flop d_ff_2 is connected to the cycle start signal of the target bus through the second inverter, the input end of the first D flip-flop d_ff_2 is connected to the data signal of the target bus, the output end Q of the first D flip-flop d_ff_2 is connected to the first data buffer 113, the first D flip-flop d_ff_2 is an active signal based on the cycle start signal, the data signal of the target bus is stored in the first data buffer 113, and based on the difference of the count values, the data in the first data buffer 113 corresponding to the first storage unit 1131 is transmitted to the position corresponding to the first target data signal.

Wherein the control module 111 is capable of reading DATA transmitted on the target bus, storing the DATA in the first DATA buffer 113, and outputting the DATA in the first DATA buffer 113 to the DATA port DATA 127.

In fig. 7, the bus cycle signal LFRAME is connected to the clock terminal of the first D flip-flop d_ff_2 through the second NOT gate not_15, and when the bus cycle signal LFRAME is an active signal (low level), the data signals LAD [3..0] having the first width are sequentially stored in the first memory unit 1131 of the first data buffer 113 through the output terminal Q of the first D flip-flop d_ff_2, and the data corresponding to the different first memory units 1131 are transferred to the positions corresponding to the first target data signals according to the difference of the count values. Illustratively, the first target DATA signal is shown as DATA [127..0], when the count value is 1, DATA of a first memory cell 1131 in the first DATA buffer 113 is transferred to the lower 4 bits DATA [3..0] of the first target DATA signal DATA [127..0], and so on.

In the bus extension device 100 provided in the embodiment of the present application, by setting the control module 111 to further include the second inverter and the first D flip-flop d_ff_2, data splicing between different first storage units 1131 in the first data buffer 113 can be implemented based on the counting sequence, so that data width extension is implemented, and application flexibility of the target bus is improved.

In some implementations, fig. 8 is a schematic diagram of a bus extension device according to an embodiment of the present application, where another specific structure of the bus extension module 110 is shown. As shown in fig. 8, in the bus extension device provided by the embodiment of the present application, the bus extension module 110 further includes a clock module 114, where the clock module 114 is connected to the control module 111, and the clock module 114 is configured to multiply the clock signal LCLK transmitted by the target bus under the control of the control module 111, so as to generate the target clock signal CLK. Specifically, the control module 111 can control the clock module 114 to perform clock coefficient adjustment, and output the target clock signal after frequency multiplication.

Wherein the input of the clock module 114 is connected to the clock signal LCLK transmitted by the target bus. Taking the target bus as an LPC bus as an example, the frequency of the clock signal is 33MHz.

In the bus extension device 100 provided in the embodiment of the present application, the bus extension module 110 further includes a clock module 114, where the clock module 114 can multiply the frequency of the clock signal LCLK transmitted by the target bus under the control of the control module 111, so that the module/device of the high-speed clock signal can be controlled by using the low-speed target bus while realizing data width extension.

In some implementations, with continued reference to fig. 5, in the bus extension apparatus provided by the embodiment of the application, the clock module 114 may include a phase-locked loop PLL, where an input of the phase-locked loop PLL is connected to the clock signal LCLK of the target bus, and the phase-locked loop PLL is configured to multiply the clock signal LCLK transmitted by the target bus to generate the target clock signal.

A phase locked loop PLL may be employed as the clock module 114 to increase the clock frequency.

For example, the multiplication factor of the phase-locked loop PLL may be 2, and the 33MHz frequency of the clock signal LCLK transmitted by the target bus is increased to the 66MHz frequency of the target clock signal, and is output to the clock terminal CLK as the clock signal of the slave module, for example, the cryptographic module. Alternatively, as shown in fig. 5, the multiplication factor of the phase-locked loop PLL may be 4, and the input 33MHz clock signal is multiplied by 4 to output 132MHz target clock signal.

In other implementations, the multiplication coefficient of the PLL may be set to other values, which may be set according to the frequency multiplication requirement, and is not limited herein. Specifically, the control module 111 can control the PLL to perform multiplication factor adjustment, and output a target clock signal meeting the frequency requirement.

In some implementations, parameters of the PLL may also be adjusted according to a clock frequency of a controlled module, such as a cryptographic module, to achieve synchronization of the clock signal LCLK transmitted by the target bus with the clock of the cryptographic module.

In some implementations, the multiplication factor of the PLL may be set to 1, so that the clock frequency remains unchanged, i.e., the CLK end of the PLL still outputs the target clock signal of 33MHz.

In the bus extension device 100 provided by the embodiment of the application, the clock module 114 can comprise a phase-locked loop PLL, and the multiplication coefficient of the phase-locked loop PLL is set, so that the matching requirements of different clock frequencies can be met, and the hardware circuit has a simple structure and is easy to realize.

In some implementations, with continued reference to fig. 5, in the bus extension device provided by the embodiment of the present application, the control module 111 further includes a second D flip-flop d_ff_1, a clock signal of the second D flip-flop d_ff_1 is accessed to a clock signal of the target bus, a data input of the second D flip-flop d_ff_1 is accessed to a RESET signal of the target bus, and the second D flip-flop d_ff_1 is configured to output a new RESET signal RESET corresponding to the first target data signal after controlling the effective time of the RESET based on the RESET signal LRESET of the target bus. The reset signal may be an active low signal, for example.

Specifically, after the RESET signal LRESET of the target bus is delayed by 1 clock cycle through the second D flip-flop d_ff_1, a new RESET signal RESET is formed and output to the RESET terminal of the bus extension module 110.

In the bus extension device 100 provided by the embodiment of the present application, the control module 111 can also receive the RESET signal LRESET transmitted by the target bus, control, for example, adjust or not change the effective time of the RESET, and then output a new RESET signal RESET to meet the RESET requirement of the controlled device.

It should be noted that, fig. 5 shows a related circuit structure of a bus expansion module based on a clock signal (shown by LCLK in fig. 5), a RESET signal (shown by LRESET in fig. 5) AND a data cycle signal (shown by LFRAME in fig. 5) transmitted by a target bus, generating an expanded clock signal (shown by CLK in fig. 5), a RESET signal (shown by RESET in fig. 5) AND a data cycle signal (shown by FRAME in fig. 5), the circuit structure may include 1 phase-locked loop (shown by PLL in fig. 5), 1D flip-flop (shown by d_ff_1 in fig. 5), 1D flip-flop with a RESET terminal (shown by dr_ff_1 in fig. 5), 1 RS flip-flop (shown by rs_ff in fig. 5), 2 alternative data selectors (shown by mux_1 mux_2 in fig. 5), 16 bit accumulator (shown by ADD in fig. 5), 2 AND gate (shown by and_1 AND 1 in fig. 5) AND 1 to 14 OR gate structures (shown by NOT gate structures in fig. 5 to 14. In other implementations, the bus extension module may also be implemented with other circuit structures that implement the extension function described above, and is not limited thereto.

In some implementations, fig. 9 is a schematic structural diagram seven of a bus extension apparatus according to an embodiment of the present application, where another specific structure of the bus extension apparatus is shown. As shown in fig. 9, the bus extension device 100 provided in the embodiment of the present application may further include a password control module 120, where the password control module 120 is connected to the bus extension module 110, the password control module 120 is further configured to be connected to the target password module 300, and the password control module 120 is configured to generate a password control signal based on the first target data signal, and the password control signal is configured to control the target password module 300.

The first target data signal is an extension signal based on a data signal transmitted by the target bus 01, and the cryptographic control module 120 is connected to the bus extension module 110, and is capable of receiving the first target data signal and generating a cryptographic control signal to control the target cryptographic module 300 connected to the cryptographic control module 120. The cipher control signal may also be understood as a cipher algorithm control signal, and may be used to control the target cipher module 300. Wherein the data width of the first target data signal is matched with the data width of the target cryptographic module 300 to realize control over the target cryptographic module 300.

The bus extension device 100 provided by the embodiment of the application comprises a bus extension module 110 and a password control module 120, and can realize the width extension of the data signal transmitted by the target bus based on the bus extension module 110, thereby improving the application flexibility of the target bus, and can control the target password module 300 based on the password control module 120, thereby improving the safety of data.

In some embodiments, the target cryptographic module 300 may be a TCM or a TPM when the bus expansion module 110 expands the width of the data signal by a factor of 1, i.e., the first target data signal is the same as the data width of the data signal transmitted by the target bus. In other embodiments, when the width extension of the bus extension module 110 is greater than 1, that is, the data width of the first target data signal is greater than the data width of the data signal transmitted by the target bus, the target cryptographic module 300 may be a cryptographic module having a corresponding data width, such as an SM4 cryptographic module, which is not limited herein.

In some implementations, fig. 10 is a schematic diagram eight of a bus extension device according to an embodiment of the present application, in which a specific structure of the cryptographic control module 120 is shown. As shown in fig. 10, in the bus extension device provided by the embodiment of the application, the cryptographic control module 120 includes an algorithm state machine 121 and a second data buffer 122, the second data buffer 122 is connected to the algorithm state machine 121, the algorithm state machine 121 is configured to transmit a first target data signal to the second data buffer 122 based on a periodic valid signal of the first target data signal, and the second data buffer 122 is configured to store at least one first target data signal to the second data buffer 122 based on control of the algorithm state machine 121 and interact with the target cryptographic module 300. By way of example, the second data buffer 122 may be a volatile memory unit, such as, but not limited to, a random access memory (Random Access Memory, RAM) or other memory-enabled component.

The algorithm state machine 121 is capable of performing data transmission control between the first data buffer 113 and the second data buffer 122, and controlling the target cryptographic module 300. Specifically, when the extended bus cycle signal FRAME is valid, the algorithm state machine 121 transmits the first target data signal to the second data buffer 122 corresponding to the cycle valid signal of the first target data signal. The second data buffer 122 may temporarily store at least one first target data signal therein, and may generate a control signal for the target cryptographic module 300 based on the stored at least one first target data signal, thereby implementing control of the target cryptographic module 300.

In the bus extension device 100 provided in the embodiment of the present application, by setting that the crypto control module 120 includes the algorithm state machine 121 and the second data buffer 122 connected to the bus extension module 110, the first target data signal formed by splicing and extending the data stored in the first data buffer 113 can be transmitted to the second data buffer 122 based on the valid period signal of the first target data signal, and further transmitted to the target crypto module 300, thereby implementing control of the target crypto module 300.

In some implementations, fig. 11 is a schematic diagram of a bus extension device according to an embodiment of the present application, where another specific structure of the cryptographic control module 120 is shown. As shown in fig. 11, in the bus extension device provided by the embodiment of the application, the cryptographic control module 120 further includes a function register 123, an input end of the function register 123 is connected to the algorithm state machine 121, an output end of the function register 123 is connected to the target cryptographic module 300, and the function register 123 is configured to output a target operation instruction to the target cryptographic module 300 based on control of the algorithm state machine 121, where the target operation instruction includes at least one of an operation instruction to write a key to the target cryptographic module 300, an operation instruction to write a data packet length to the target cryptographic module 300, and an operation instruction to encrypt and decrypt data.

Illustratively, the function register 123 may be a 3-bit register for representing different operation commands of the algorithm state machine 121 to the target cryptographic module 300, and the different operation commands may be output to the target cryptographic module 300 through the command port OP [2..0 ]. Wherein each bit has the effect of being set by the algorithm state machine 121 to an initial value of '0', being set to '1' to represent an operation instruction for writing a KEY to the target cryptographic module, illustratively the KEY may be represented as KEY 4n-1..0], being set by the algorithm state machine 121 to an initial value of '0', being set to '1' to represent an operation instruction for writing a data packet length to the target cryptographic module, illustratively the data packet length may be represented as LEN 4n-1..0], being set by the user in the host software to a value of '1' to represent an operation instruction for data encryption, and being set to '0' to represent an operation instruction for data decryption.

In the bus extension device 100 provided by the embodiment of the application, by setting the password control module 120 to include the function register 123, different operations on the target password module 300 can be realized based on the control of the operation instruction, and the control mode is simple while ensuring the data security.

In some implementations, fig. 12 is a schematic diagram of a state transition flow of an algorithm state machine of a bus extension device according to an embodiment of the present application, which shows the flow steps of a state transition of the algorithm state machine 121. As shown in fig. 12, the algorithm state machine 121 includes the states of IDLE, START, write KEY wr_key, write length wr_len, write DATA wr_data, WAIT, read DATA rd_data, end fish. Illustratively, when bus extension apparatus 100 is implemented based on a programmable device, such as a field programmable gate array (Field Programmable GATE ARRAY, FPGA), algorithm state machine 121 may be implemented by VHDL programming of an FPGA, which is not limited in this regard.

As shown in fig. 12, the transition/transfer relationship between the different states may include the following steps:

Entering an IDLE state after a system RESET (e.g., reset= "0"), the algorithm state machine 121 enters a START state when the RESET is ended and the target bus transmits a cycle START signal (e.g., frame= '0');

at the START state, the algorithm state machine 121 sets the function register 123 to be located at the writing KEY to the target cryptographic module 300, i.e., the algorithm state machine 121 sets OP [0] = '1' of the function register 123, and then enters the writing KEY wr_key state;

In the write KEY wr_key state, the algorithm state machine 121 sends KEY data in the second data buffer 122, e.g., KEY [127..0] to the target cryptographic module 300, and sets the function register 123 to be located at the write length to the target cryptographic module 300, i.e., sets OP [1] = '1' of the function register 123, and then enters the write length wr_len state;

in the write length wr_len state, algorithm state machine 121 sends length DATA, e.g., LEN [127..0], in second DATA buffer 122 to target cryptographic module 300, before entering the write DATA wr_data state;

in the write DATA wr_data state, the algorithm state machine 121 transmits the cryptographic DATA stored in the at least one second storage unit 1221 in the second DATA buffer 122 to the target cryptographic module 300 according to the cryptographic length value LEN in the length DATA, and then enters the WAIT state;

In the WAIT state, the algorithm state machine 121 WAITs for the target cryptographic module 300 to complete the operation and enters the read DATA rd_data state based on the completion of the operation (e.g., done= '1');

In the read DATA RD_DATA state, the algorithm state machine 121 reads the DATA ciphertext or DATA plaintext after the target cryptographic module 300 has been operated, and stores the DATA ciphertext or DATA plaintext in at least one second storage unit 1221 in the second DATA cache 122;

At the end of the FINISH state, the algorithm state machine 121 clears the flag bit of the function register 123, that is, clears the OP [0] bit and OP [1] bit of the function register 123, and returns to the IDLE state.

Thus, the data processing process of the control target cryptographic module 300 is completed once, and the next data processing will repeat the above steps.

In some implementations, fig. 13 is a schematic diagram of a bus extension device according to an embodiment of the present application, in which a specific structure of the second data buffer 122 is shown. As shown in fig. 13, in the bus extension device according to the embodiment of the present application, the second data buffer 122 includes a key data storage unit 1222, a length data storage unit 1223, and at least one second storage unit 1221, where the key data storage unit 1222 is configured to store key data, the length data storage unit 1223 is configured to store length data, the second storage unit 1221 is configured to store cipher data of different data packets, and a set of cipher data includes a first target data signal.

Illustratively, when the first data width is 4 bits, the first target width of the first target data signal is 4 nbits, and the capacity size of each second memory cell 1221 may be 4n bits. Similar to the first data buffer, the storage capacity of the entire second data buffer 122 may be set by a user according to data storage requirements or may be dynamically changed based on differences in reference scenarios, which are not limited herein.

Illustratively, taking the orientation of the second DATA buffer 122 shown in fig. 13 as an example, the 1 st storage unit may be a KEY DATA storage unit 1222 for storing KEY DATA KEY [4n-1..0], the 2 nd storage unit may be a length DATA storage unit 1223 for storing length DATA LEN [4n-1..0], which indicates the number of DATA packets to be encrypted/decrypted, i.e., len=m (m+.1), which indicates that there are M DATA packets to be encrypted/decrypted, in order from bottom to top, the 3 rd to m+2 th storage units may be second storage units 1221 each for storing a first target DATA signal, and the first target DATA signals DATA [4n-1..0] may be sequentially stored in the 3 rd to m+2 th second storage units 1221.

In the bus extension device 100 provided by the embodiment of the application, the algorithm state machine 121 also controls the KEY DATA KEY [4n-1..0] in the second DATA buffer 122 to be transmitted to the KEY port of the target cryptographic module 300 through the KEY output end KEY, the length DATA LEN [4n-1..0] is transmitted to the length port of the target cryptographic module 300 through the length output end LEN, the DATA packets data_1-data_m are sequentially transmitted to the DATA input port of the target cryptographic module 300 through the DATA output end data_out [4n-1..0], and the command port OP [2..0] is connected to the command control port of the target cryptographic module 300 so as to realize the transmission of operation instructions and realize the control of the target cryptographic module 300 based on the operation instructions.

In some implementations, fig. 14 is a schematic diagram eleven of a structure of a bus extension apparatus according to an embodiment of the present application, where another specific structure of the bus extension apparatus is shown. As shown in fig. 14, in the bus extension device provided by the embodiment of the application, the algorithm state machine 121 and the second data buffer area 122 are further respectively connected to the control module 111 in the bus extension module 110, the algorithm state machine 121 is further configured to transmit a preparation completion signal to the control module 111 based on receiving the data packet completed by the operation of the target cryptographic module 300 and transmitting the data packet to a different second storage unit 1221 in the second data buffer area 122, and the control module 111 is further configured to read the second target data signal in the target second storage unit 1221 in the second data buffer area 122 and store the second target data signal in the first storage unit 1131 in the first data buffer area 113 in the bus extension module 110 according to the format of the first width based on the preparation completion signal.

Specifically, the algorithm state machine 121 is further capable of receiving an operation completion signal DONE of the target cryptographic module 300, receiving a DATA packet, i.e., encrypted DATA ciphertext or decrypted DATA plaintext, of the target cryptographic module 300 through the DATA input port data_in [4n-1..0] when done= '1', and sequentially transmitting the DATA packet to the second DATA buffer 122, and making the output READY to be high level '1' after the DATA transmission is completed. Correspondingly, the control module 111 receives a READY signal of the algorithm state machine 121, and when ready= '1', reads DATA in the second DATA buffer 122 through the DATA interaction port DATA, where the DATA is the second target DATA signal, and sequentially stores the read DATA in the first DATA buffer 113 according to a format with a first width, for example, 4 bits, so that the DATA can be transmitted through the target bus.

In some implementations, fig. 15 is a schematic diagram twelve of a bus expansion device according to an embodiment of the present application, which shows a related circuit structure that the bus expansion module 110 reads DATA [127..0], stores it in the first DATA buffer 113, and transmits it to the target bus. Taking the first width as 4 bits and the second target width as 128 bits as an example. In the figure, the control module 111 includes 1 Tri-state buffer Tri, 1 multiplexer SEL and 32 comparators cmp_1 to cmp_32. The control end of the Tri-state buffer Tri is connected with a READY signal, when ready= '1', the Tri-state buffer Tri is conducted, DATA [127..0] can be output through a Tri-state gate, after being split by 4 bits, the Tri-state buffer Tri is connected to an input end d corresponding to a multi-way DATA selector SEL, 1 input end of each of the comparators cmp_1-cmp_32 is connected with a count value cnt, the other 1 input end is a comparison value, the comparison values are respectively set to 1-32, the output ends of the cmp_1-cmp_32 are respectively connected to a selection control end e of the multi-way DATA selector SEL, the output end of the multi-way DATA selector SEL is connected to a first DATA buffer area 113, the multi-way DATA selector SEL can gate corresponding DATA according to the output result of each comparator, for example, when the count value cnt=1, the first cmp_1 outputs a high level, the rest comparators output a low level, and at the moment, the DATA [3..0] are output to the first DATA buffer area 113 through the multi-way DATA selector SEL, and the like. After the data is transferred to the first data buffer 113, it is transferred to the target bus.

In some implementations, the target bus includes an LPC bus, and the bus extension device is implemented based on a programmable logic device, the first target width and the second target width each being an integer multiple of the first width.

The bus extension device 100 provided by the embodiment of the application can extend the LPC bus based on a programmable logic device, such as an FPGA, and realize the control of a module/device having a data bus with a data bus width greater than 4 bits, specifically, an integer multiple of 4 bits. Meanwhile, the frequency multiplication can be performed based on the clock module, so that the control of the module/equipment with high-speed clock signals (for example, integer multiple of 33 MHz) by using the low-speed LPC bus is realized, and the data processing speed is improved. Meanwhile, a password control module can be adopted, so that the safety in the data communication process is improved. In addition, the function of the existing system is not affected by the adoption of the scheme, namely, when the multiple is 1, the data width of the LPC bus is kept unchanged, the function of the existing system is maintained, and the system is flexible to deploy and convenient to implement.

Specifically, the bus expansion device 100 provided by the embodiment of the application can realize expansion of the LPC bus based on the FPGA, and can be applied to the fields of electronic information and data security. Specifically, the bus expansion module comprises a control module based on the FPGA, so that the processing of LPC bus data signals and control signals can be realized, the equipment with an LPC interface can control the width to be 4nbit (n=1, 2, the number of the equipment is equal to N), namely, the equipment is a multiple of 4bit, such as a module/equipment/data bus with 16bit, 32bit, 64bit and the like, and the expansion of the data bus is realized, and the application flexibility is improved. On the basis, the clock module is utilized to multiply the frequency of the clock signal of the LPC bus, and the target cipher module is controlled by the algorithm state machine of the cipher control module, so that the transmission speed and the safety of data can be improved. Therefore, the embodiment of the application can control the module/equipment of the data bus with high-speed clock signals and 4bit multiple by utilizing the limited data width and clock signals of the LPC bus, has expandability and safety, does not influence the functions of the existing system, and has flexible deployment and convenient implementation. In addition, the target password module is controlled, so that the overall safety of the system can be improved, and the requirement of the information safety field on data safety processing is met.

In some implementations, fig. 16 is a schematic diagram of an application architecture of a bus extension device according to an embodiment of the present application, taking an SM4 cryptographic algorithm module as an example, and showing an application manner of the bus extension device. The target cryptographic module for controlling other data widths based on the bus extension device is similar and not described in detail herein. The SM4 cryptographic algorithm is a cryptographic algorithm module with a cryptographic key width of 128 bits and a data width of 128 bits, and the SM4 cryptographic algorithm processes 1 data packet each time by taking the 128 bits as 1 data packet until all data packets are processed, and generates ciphertext after data encryption or plaintext after decryption.

The signals of the SM4 cryptographic algorithm module shown in the figure and their corresponding actions will be described. The specific value of clk can be input by an external clock source, the higher the frequency is, the faster the operation speed of the SM4 cryptographic algorithm module is, and the clock signal can adopt 132MHz clock frequency in the embodiment;

len 127.0 represents a length signal representing the number of Data packets, op 2.0 represents a command control signal, done represents an output signal after completion of Data operation, and data_out 127.0 represents a Data output signal having a Data width of 128 bits.

As shown in fig. 16, the bus extension device 100 may be connected to the host software 200 through an LPC bus, and to the SM4 cryptographic algorithm module 3 through another bus.

The upper computer software 200 is upper application software operated by a user side, and may include a driver, an application software interface, etc., where a user sets a key, a register, data to be operated, etc. through the upper computer software, and sends the data to the bus expansion module 110 through an LPC bus, and receives data returned by the bus expansion module 110 and operated by the SM4 cryptographic algorithm module 3 through the LPC bus.

The bus extension module 110 may employ any of the bus extension modules provided in the above embodiments. Illustratively, in the bus extension module 110, by setting the PLL multiplication coefficient of the clock module 114 to 4, the control module 111 multiplies the clock signal LCLK input to the LPC bus by 4, and outputs the target clock signal clk=33×4=132 (MHz) as the clock signal of the SM4 crypto algorithm module. Since the DATA width of the SM4 cipher algorithm module is 128 bits, the count value n=128 bits/4 bits=32 of the count module 112, and the DATA signal output by the bus expansion module is DATA [127..0].

The cryptographic control module 120 may employ any of the cryptographic control modules provided in the above embodiments. IN the cryptographic control module 120, the capacity of the memory cells of the second DATA buffer 122 is 128 bits, and the corresponding interactive ports, including the KEY output KEY, the length output LEN, the DATA output data_out, and the DATA input data_in, are 128 bits.

In some implementations, a power module and JTAG/AS interface may also be provided on the bus extension device 100, e.g., an FPGA. The power module can provide working voltages for each module of the FPGA, such as 1.5V, 3.3V, etc., which is not limited herein. The JTAG/AS interface is a debugging/downloading interface of the FPGA and is used for debugging and downloading programs of the FPGA.

In the embodiment of the application, the expansion of the LPC bus and the frequency multiplication of the clock frequency are realized based on the FPGA, so that the SM4 cryptographic algorithm module with the data bus width of 32 times of 4 bits can be controlled, and in addition, the SM4 cryptographic algorithm module is controlled in the FPGA through an algorithm state machine, so that the speed and the safety of data processing are improved.

Based on the same inventive concept, the embodiments of the present application further provide a data processing method, where the data processing method is executed based on any one of the bus extension devices provided in the embodiments of the present application, and the same or similar parts can be understood by referring to the above, and are not repeated herein.

Fig. 17 is a schematic flow chart of a data processing method according to an embodiment of the application. As shown in fig. 17, the data processing method may include:

S510, acquiring a data signal with a first width transmitted by a target bus.

For example, the bus extension device may acquire a data signal having a first width transmitted by the target bus.

S520, generating a first target data signal based on the data signal having the first width, the first target data signal having a data width that is the first target width, the first target width being equal to or greater than the first width.

The bus expansion means may, for example, perform data expansion for a data signal having a first width, generate a first target data signal having a first target width, wherein the first target width may be equal to the first width so as not to affect the control of the module/device having the data signal of the first width, or the first target width may be greater than the first width so as to enable the control of the module/device having the data signal greater than the first width.

In the data processing method provided by the embodiment of the application, the width of the data signal transmitted by the target bus is expanded, so that the module/device with the data width equal to or larger than the first width can be controlled, and the application flexibility of the target bus is improved.

Fig. 18 is a schematic flow chart of a data processing method according to an embodiment of the application. As shown in fig. 18, the data processing method may include:

S610, acquiring a second target data signal.

For example, a control module in the bus extension device may acquire a second target data signal having a second target width.

S620, generating a data signal with a first width based on a second target data signal, wherein the data width of the second target data signal is a second target width, and the second target width is larger than or equal to the first width.

For example, the control module in the bus extension device may split the second target data signal having the second target width in the format of the first width and further store the second target data signal to the first storage unit in the first data buffer for transmission based on the target bus having the first width.

In the data processing method provided by the embodiment of the application, the data signal with the first width, which can be transmitted by the target bus, is generated by performing data width conversion on the second target data signal, so that the control of modules/devices with other data widths can be realized based on the target bus, and the application flexibility of the target bus is improved.

In some implementations, the bus extension module may include a control module, a count module, and a first data cache.

Based on this, generating the first target data signal based on the data signal having the first width may include:

The counting module counts the data period of the target bus and transmits the counted value to the control module;

the first data buffer area stores data signals of at least one data period transmitted by the target bus;

The control module generates a first target data signal based on the data signal of at least one data period stored in the first data buffer based on the count value reaching a target count value, and outputs a period valid signal of the first target data signal.

In the data processing method provided by the embodiment of the application, the bus expansion module comprises a control module, a counting module and a first data buffer area, wherein the counting module can count the data period of the target bus and transmit the count value to the control module, the first data buffer area can store the data signal of at least one data period transmitted by the target bus, the control module can generate a first target data signal based on the data signal of at least one data period stored in the first data buffer area and output a period effective signal of the first target data signal based on the data signal of at least one data period when the count value reaches the target count value, and therefore data width expansion is achieved.

In some implementations, the bus extension module further includes a clock module.

Based on the above, the data processing method may further include the clock module multiplying the clock signal transmitted by the target bus under the control of the control module to generate the target clock signal.

In the data processing method provided by the embodiment of the application, the bus expansion module is arranged to further comprise a clock module, and the clock module can multiply the frequency of the clock signal transmitted by the target bus under the control of the control module, so that the module/equipment of the high-speed clock signal can be controlled by utilizing the low-speed target bus while the data width expansion is realized.

In some implementations, the bus extension device further includes a cryptographic control module.

Based on this, the data processing method may further comprise the cryptographic control module generating a cryptographic control signal based on the first target data signal, the cryptographic control signal being configured to control the target cryptographic module.

According to the data processing method provided by the embodiment of the application, the width expansion of the data signal transmitted by the target bus can be realized based on the bus expansion module, so that the application flexibility of the target bus is improved, the target password module can be controlled based on the password control module, and the safety of data is improved.

In some implementations, the cryptographic control module includes an algorithm state machine and a second data cache.

Based on this, generating the cryptographic control signal based on the first target data signal may specifically include:

the algorithm state machine transmits the first target data signal to the second data buffer area based on the period effective signal of the first target data signal;

the second data buffer stores at least one first target data signal to the second data buffer based on control of an algorithm state machine, and interacts with the target cryptographic module.

In the data processing method provided by the embodiment of the application, by setting the password control module to comprise the algorithm state machine and the second data buffer area which are connected with the bus expansion module, the first target data signal formed by splicing and expanding the data stored in the first data buffer area can be transmitted to the second data buffer area based on the effective periodic signal of the first target data signal and further transmitted to the target password module, so that the control of the target password module is realized.

In some implementations, interacting with the target cryptographic module may include:

the algorithm state machine sends the key data, the length data and the password data of different data blocks in the second data cache area to the target password module;

And the algorithm state machine reads the data processed by the target password module based on the completion of the processing of the password data by the target password module and stores the data into a second storage unit in the second data cache area.

The method and the device realize the transmission of data to the target cryptographic module and the reading of the data from the target cryptographic module, thereby realizing the interaction between the algorithm state machine and the target cryptographic module and further realizing the control of the target cryptographic module.

In some implementations, generating a data signal having a first width based on a second target data signal may include:

The control module reads a second target data signal in a target second storage unit in the second data cache region, stores the second target data signal in a first storage unit in the first data cache region according to a format of a first width, and reads data in the first data cache region by an upper computer connected with a target bus.

Therefore, conversion of the data width is realized based on the control module, the second data buffer area and the first data buffer area, so that a second target data signal with a second target width is conveniently converted into a data signal with a first width, transmission of a data signal with a larger data width is conveniently performed based on the target bus, and application flexibility of the target bus is improved.

In some implementations, fig. 19 is a third flowchart of a data processing method according to an embodiment of the present application, which illustrates an overall process of one data processing. As shown in fig. 19, the data processing method may include:

S710, a user sets a key, a packet length, data to be operated and a value of a function register OP [2] bit through upper computer software, OP [2] = '1' represents data encryption operation, and '0' represents decryption operation.

S720, the data is transmitted to the first data buffer area through the target bus.

And S730, after the data is converted by the bus expansion module, storing the data in the second data cache area in a format of a first target width.

And S740, the algorithm state machine sends the data in the second data buffer area to the target password module.

S750, the target cipher module obtains the key, the group length and the data to be operated, and encrypts or decrypts the data according to the OP 2 value.

S760, the algorithm state machine is in a waiting state.

During this step, all data packet processing is waited for to complete. It may be determined whether all data packet processing is completed, for example, whether done= '1', if not, indicating that the processing is not completed, returning to S750, and if yes, indicating that the processing is completed, executing the subsequent S770.

S770, when done= '1', the algorithm state machine reads the ciphertext data or plaintext data after the operation is completed, and stores the ciphertext data or plaintext data in the second data buffer, and after all the data after the operation is completed, the algorithm state machine reads the signal ready= '1'.

In this step, whether the reading is completed or not is determined, for example, whether ready= '1' is determined, when the determination result is no, it indicates that the reading is not completed, the reading operation is performed, when the determination result is yes, it indicates that the reading is completed, and the subsequent S780 is performed.

S780, the bus expansion module reads the data in the second data cache area and sequentially stores the data in the first data cache area according to the format of the first width.

S790, the upper computer reads the data in the first data buffer area through the target bus.

Thus, the data processing process is completed once.

In other embodiments, if the key change, the data change, the packet length, etc. are required, the above steps may be repeated.

According to the data processing method provided by the embodiment of the application, the control of the target password module with the first target width can be realized based on the target bus through data width expansion, so that the application flexibility of the target bus is improved, and the data processing safety is ensured.

It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bus expansion device, characterized in that it is configured in a server; the bus expansion device comprises:

A bus expansion module is configured to connect to a target bus; the bus expansion module is configured to interact with the target bus to generate a data signal with a first width, and generate a first target data signal based on the data signal with the first width, or generate the data signal with the first width based on an acquired second target data signal;

Wherein, the data width of the first target data signal is the first target width, and the data width of the second target data signal is the second target width; the first target width is equal to or greater than the first width, and the second target width is greater than or equal to the first width;

The bus expansion device further includes a cryptographic control module, which is connected to the bus expansion module; the cryptographic control module is configured to connect to a target cryptographic module.

The cryptographic control module includes an algorithm state machine and a function register. The input of the function register is connected to the algorithm state machine, and the output of the function register is connected to the target cryptographic module.

The function register is configured to control the algorithm state machine and output target operation instructions to the target cryptographic module. The target operation instructions include at least one of the following: an operation instruction to write a key to the target cryptographic module, an operation instruction to write a data block length to the target cryptographic module, and a data encryption/decryption operation instruction.

2. The bus expansion device according to claim 1, wherein the bus expansion module includes a control module, a counting module, and a first data buffer, wherein the counting module and the first data buffer are respectively connected to the control module;

The counting module is configured to count the data cycles of the target bus and transmit the count value to the control module;

The first data buffer is configured to store the data signal of at least one data cycle transmitted by the target bus;

The control module is configured to generate the first target data signal based on the data signal of the at least one data period stored in the first data buffer when the target count value is reached, and to output the periodic valid signal of the first target data signal.

3. The bus expansion device according to claim 2, wherein the counting module includes an accumulator;

The accumulator counts the data cycles based on the cycle start signal transmitted on the target bus.

4. The bus expansion device according to claim 2, wherein the first data buffer includes at least one first storage unit;

The capacity of the first storage unit matches the first width and is configured to store the data signal for at least one data cycle.

5. The bus expansion device according to claim 2, characterized in that the control module includes an RS flip-flop and a first inverter; the data input terminal of the RS flip-flop is connected to a first level, the carry terminal of the RS flip-flop is connected to a second level, the set terminal and the clear terminal of the RS flip-flop are connected to the counting module, and the output terminal of the RS flip-flop is connected to the output terminal of the control module through the first inverter; the RS flip-flop outputs a periodic valid signal of the first target data signal based on the count value reaching the target count value;

The control module further includes a second inverter and a first D flip-flop; the clock terminal of the first D flip-flop is connected to the period start signal of the target bus through the second inverter, the input terminal of the first D flip-flop is connected to the data signal of the target bus, and the output terminal of the first D flip-flop is connected to the first data buffer; the first D flip-flop stores the data signal of the target bus in the first data buffer based on the period start signal being valid, and transmits the data in the first storage unit corresponding to the first data buffer to the position corresponding to the first target data signal based on the different count values.

6. The bus expansion device according to claim 2, wherein the bus expansion module further includes a clock module, the clock module being connected to the control module;

The clock module is configured to multiply the clock signal transmitted on the target bus under the control of the control module to generate a target clock signal.

7. The bus expansion device according to claim 6, wherein the clock module includes a phase-locked loop;

The input terminal of the phase-locked loop is connected to the clock signal of the target bus, and the phase-locked loop is configured to multiply the clock signal transmitted by the target bus to generate a target clock signal.

8. The bus expansion device according to claim 6, wherein the control module further comprises a second D flip-flop; the clock terminal of the second D flip-flop is connected to the clock signal of the target bus, and the data input terminal of the second D flip-flop is connected to the reset signal of the target bus; the second D flip-flop is configured to output a new reset signal corresponding to the first target data signal after controlling the effective time of the reset based on the reset signal of the target bus.

9. The bus expansion device according to any one of claims 1-8, wherein the cryptographic control module is configured to generate a cryptographic control signal based on the first target data signal, and the cryptographic control signal is configured to control the target cryptographic module.

10. The bus expansion device according to claim 9, wherein the cryptographic control module further includes a second data buffer, the second data buffer being connected to the algorithm state machine;

The algorithm state machine is configured to transmit the first target data signal to the second data buffer based on a periodic valid signal of the first target data signal;

The second data buffer is configured to store at least one of the first target data signals into the second data buffer based on the control of the algorithm state machine, and to interact with the target cryptographic module.

11. The bus expansion device according to claim 10, wherein the second data buffer area comprises a key data storage unit, a length data storage unit, and at least one second storage unit;

The key data storage unit is configured to store key data, the length data storage unit is configured to store length data, the second storage unit is configured to store cryptographic data of different data groups, and a group of cryptographic data includes a first target data signal.

12. The bus expansion device according to claim 11, wherein the algorithm state machine includes the following states: idle, start, write key, write length, write data, wait, read data, and end;

The transitions between the different states include the following steps:

After the system is reset, it enters an idle state. When the reset ends and the target bus transmission cycle starts, the algorithm state machine enters the start state.

In the initial state, the algorithm state machine sets the function register to write the key to the target cryptographic module, and then enters the key writing state;

In the key writing state, the algorithm state machine sends the key data in the second data buffer to the target cryptographic module; and sets the function register to write the length to the target cryptographic module, and then enters the length writing state;

In the write length state, the algorithm state machine sends the length data in the second data buffer to the target cryptographic module, and then enters the write data state;

In the data writing state, the algorithm state machine sends the password data stored in at least one of the second storage units in the second data buffer to the target password module according to the password length value in the length data, and then enters the waiting state;

In the waiting state, the algorithm state machine waits for the target cryptographic module to complete its operation, and then enters the data reading state based on the completion of the operation.

In the data reading state, the algorithm state machine reads the ciphertext or plaintext data after the target cryptographic module has completed its operation and stores it in at least one of the second storage units in the second data buffer; then it enters the end state.

In the final state, the algorithm state machine clears the flag bit of the function register and then returns to the idle state.

13. The bus expansion device according to claim 12, wherein the algorithm state machine and the second data buffer are further connected to the control module in the bus expansion module;

The algorithm state machine is further configured to receive data packets completed by the target cryptographic module, transmit the data packets to different second storage units in the second data buffer, and send a preparation completion signal to the control module.

The control module is further configured to read the second target data signal from the target second storage unit in the second data buffer based on the preparation completion signal, and store the second target data signal in the first storage unit in the first data buffer of the bus expansion module in the format of the first width.

14. The bus expansion device according to claim 1, wherein the target bus includes an LPC bus; the bus expansion device is implemented based on a programmable logic device, and the first target width and the second target width are both integer multiples of the first width.

15. A data processing method, characterized in that it is executed based on the bus expansion device according to any one of claims 1-14; the data processing method includes:

Acquire the data signal with a first width transmitted by the target bus;

A first target data signal is generated based on the data signal having a first width, wherein the data width of the first target data signal is the first target width, and the first target width is equal to or greater than the first width;

or,

Acquire the second target data signal;

A data signal with a first width is generated based on the second target data signal, wherein the data width of the second target data signal is a second target width, and the second target width is greater than or equal to the first width.

16. The data processing method according to claim 15, wherein the bus expansion module includes a control module, a counting module, and a first data buffer; the step of generating a first target data signal based on the data signal having a first width includes:

The counting module counts the data cycles of the target bus and transmits the count value to the control module;

The first data buffer stores the data signal of at least one data cycle transmitted by the target bus;

The control module reaches a target count value based on the count value, generates a first target data signal based on the data signal of at least one data period stored in the first data buffer, and outputs a periodic valid signal of the first target data signal.

17. The data processing method according to claim 16, wherein the bus expansion module further includes a clock module; the data processing method further includes:

Under the control of the control module, the clock module multiplies the clock signal transmitted on the target bus to generate a target clock signal.

18. The data processing method according to claim 16, wherein the bus expansion device further includes a password control module; the data processing method further includes:

The cryptographic control module generates a cryptographic control signal based on the first target data signal, and the cryptographic control signal is configured to control the target cryptographic module.

19. The data processing method according to claim 18, wherein the cryptographic control module comprises an algorithm state machine and a second data buffer; the step of generating a cryptographic control signal based on the first target data signal comprises:

The algorithm state machine transmits the first target data signal to the second data buffer based on the periodic valid signal of the first target data signal;

The second data buffer, based on the control of the algorithm state machine, stores at least one of the first target data signals into the second data buffer and interacts with the target cryptographic module;

The interaction with the target cryptographic module includes:

The algorithm state machine sends the key data, length data, and cipher data of different data blocks in the second data buffer to the target cryptographic module;

The algorithm state machine reads the data processed by the target cryptographic module after the target cryptographic module has finished processing the cryptographic data, and stores it in the second storage unit in the second data cache area.

The step of generating a data signal with a first width based on the second target data signal includes:

The control module reads the second target data signal from the target second storage unit in the second data buffer, and stores the second target data signal in the first storage unit in the first data buffer according to the first width format; the data in the first data buffer is available for reading by the host computer connected to the target bus.