CN119906402A - High-precision multi-power supply detection power-on reset circuit - Google Patents
High-precision multi-power supply detection power-on reset circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature
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Abstract
The invention discloses a power-on reset circuit for high-precision multi-power detection, which mainly solves the problem that the existing power-on reset circuit cannot reset a plurality of power supplies. It includes power detection unit, buffer unit. The power supply detection unit is used for detecting the power supply up and down and giving out a reset signal with accurate threshold value, and comprises two power supply voltage division modules, two power supply threshold value modules and a high-to-low module, wherein the buffer unit is used for outputting a final reset signal and generating a feedback output signal to the power supply detection unit. The feedback outputs are respectively transmitted to the first power voltage division module and the high-to-low module for voltage division and conversion, converted voltages are output through the high-to-low module and converted again through the second power voltage division module, and then are respectively output to the two power threshold modules for comparison and combination, and finally reset signals are output to the buffer unit. The invention can improve the accuracy and temperature characteristics of the power-on and power-off threshold values, reduce the power consumption, and can be used for detecting a plurality of power supplies of the chip.
Description
Technical Field
The invention belongs to the technical field of analog integrated circuits, and particularly relates to a power-on reset circuit which can be used for detecting a plurality of power supplies of a chip and ensuring that the chip works in a power supply range with accurate threshold value.
Background
In the power-on process of the chip, all modules in the circuit are in an undetermined state, and some modules have the minimum power supply voltage requirement, so that a power-on reset circuit is needed, and a power-on reset signal is output after the power supply voltage reaches a threshold value and is used for resetting the modules, so that all the modules in the circuit output expected default signals, and the power supply voltage is ensured to meet the minimum power supply voltage requirement of all the modules. In some application scenarios, the power supply of the chip needs multiple power supplies such as digital power supplies and analog power supplies, and power-on and power-off thresholds of the multiple power supplies are required, so that a power-on reset circuit capable of detecting multiple power supplies and having thresholds for each power supply is required.
The existing power-on reset circuit is usually realized by a cascade resistor string, a band-gap reference and a comparator circuit, wherein the band-gap reference circuit provides a reference voltage, the cascade resistor string is used for dividing the power supply voltage, and the comparator is used for judging whether the divided voltage of the cascade resistor string is larger than the reference voltage given by the band-gap reference circuit. When the power supply is powered on, the band-gap reference circuit can quickly output stable reference voltage and is larger than the voltage division of the cascade resistor string, and the comparator outputs low level. When the power supply voltage continues to increase, and the voltage division of the cascade resistor string is larger than the reference voltage given by the band gap reference circuit, the comparator outputs high level, and the reset is completed. The power-on reset circuit is simple in structure and principle, and can provide power-on and power-off thresholds with higher precision, but the band-gap reference circuit and the comparator circuit are needed, and the power-on threshold and the power-off threshold are the same voltage, so that no hysteresis interval exists. Therefore, the power consumption is high, only the voltage of a single power supply can be detected, and the requirements of power-on reset detection of a plurality of power supplies cannot be met.
In order to meet the requirements of multiple power supply detection, multiple PMOS (P-channel metal oxide semiconductor) tubes and units with resistors connected in series can be used for detecting power supply voltage, and finally, the output of a power-on reset signal is realized through an OR gate. The implementation mode is simple, and the power-on reset circuit can be configured into a plurality of power supply detection circuits, but the accuracy of the power-on threshold voltage and the power-off threshold voltage is not high, and a hysteresis interval of the power-on threshold and the power-off threshold cannot be configured. The power-on reset circuit for detecting the multiple power supplies with high threshold precision can be realized by a plurality of cascade resistor strings, comparators and a band-gap reference circuit, wherein the cascade resistor strings divide the multiple power supplies respectively, the band-gap reference circuit provides reference voltages with different magnitudes, the comparators compare the divided voltage of the cascade resistor strings with the reference voltage of the band-gap reference circuit, and finally, the comparison result is output by an AND gate, so that the power-on reset result for detecting the multiple power supplies is obtained. This approach, while capable of power-on-reset detection of multiple power supplies, requires multiple comparators and multiple reference voltages, consumes significant power consumption and area, and requires a band gap reference circuit to power up faster, which is difficult to achieve in some chips.
Patent document CN201811440767.0 proposes a power-on reset circuit, which adopts a mode of combining a comparator and a schmitt trigger, divides a power supply through a cascade resistor string, compares the divided signal with a reference voltage through the comparator, and outputs the result of low level comparison received by the schmitt trigger to complete the power-on reset of the circuit. The circuit feeds back and gates different voltage division signals according to the result of power-on reset, so that different power-on thresholds and power-off thresholds are obtained. However, the circuit can only detect the voltage of a single power supply, cannot meet the requirements of power-on reset detection of a plurality of power supplies, has a complex comparator structure, requires additional reference voltage, and is not beneficial to the reduction of power consumption.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides a high-precision multi-power-supply detection power-on reset circuit which is used for improving the precision and temperature characteristics of power-on and power-off threshold values, reducing power consumption and realizing the detection of the power-on reset circuits of a plurality of power supplies.
The technical scheme for realizing the aim of the invention is that a plurality of power supply voltages are detected by utilizing the voltage division of a cascade resistor string, wherein a main power supply obtains an accurate threshold value through a band-gap reference-like structure, and the rest power supplies lower than the main power supply voltage utilize the threshold value of a transistor as the voltage division threshold value of the cascade resistor string, and the detection results are input into a buffer module to finally output a power-on reset signal.
According to the above thought, the invention provides a power-on reset circuit for high-precision multi-power detection, and a scheme for carrying out power-on reset and power-off protection by using the power-on reset circuit, wherein the scheme comprises the following steps:
1. the utility model provides a power on reset circuit of many power of high accuracy detection, includes power detecting element and buffer unit, its characterized in that:
The power supply detection unit is used for detecting the power supply up and down and giving out a reset signal with accurate threshold value, and comprises two power supply voltage division modules, two power supply threshold value modules and a high-to-low module, wherein the output fed back by the buffer unit is respectively transmitted to the first power supply voltage division module and the high-to-low module for voltage division and conversion, and the converted voltage output by the high-to-low module is respectively output to the first power supply threshold value module and the second power supply threshold value module for comparison and combination after being converted again by the second power supply voltage division module and is transmitted to the buffer unit for outputting a final reset signal.
Further, the input end of the first power voltage division module is connected with the feedback output end of the buffer unit, the output end of the first power voltage division module is connected with the input end of the first power threshold module, and the output end of the first power threshold module is connected with the input end of the buffer unit;
The input end of the high-to-low conversion module is connected with the feedback output of the buffer unit, and the output end of the high-to-low conversion module is connected with the input end of the second power voltage division module;
the output end of the second power supply voltage division module is connected with the input end of the second power supply threshold module, and the output end of the second power supply threshold module is connected with the input end of the buffer unit;
the working voltages of the modules are supplied by an external power supply, and the power supply comprises a first power supply VDD1 and a second power supply VDD2.
2. A method of power-on reset using the power-on reset circuit of claim 1, comprising:
setting a first power supply VDD1 and a second power supply VDD2 to enter a power-on state, so that the power supply voltage is gradually increased, and at the moment, the power supply detection unit receives a high-level feedback signal ENB of the buffer unit and transmits the high-level feedback signal ENB to the high-to-low module to convert the high-level feedback signal ENB into a low-voltage signal;
the low-voltage signal and the high-level feedback signal ENB are respectively transmitted to a second power supply voltage division module and a first power supply voltage division module to generate respective power-on voltage division, and are respectively transmitted to a second power supply threshold module and a first power supply threshold module to be compared, when the power-on voltage division is greater than the power-on threshold of the two threshold modules, the threshold module outputs a comparison result as a high level, and then the comparison result is transmitted to a buffer unit;
the buffer unit receives and outputs the high level of the comparison result, and the power-on reset of the circuit is completed.
3. A method for power-down protection using the power-on reset circuit of claim 1, comprising the steps of:
After the power-on reset is completed, the first power supply VDD1 and the second power supply VDD2 are set to enter a power-off state, so that the power supply voltage is gradually reduced, at the moment, the power supply detection unit receives a low-level feedback signal ENB of the buffer unit and transmits the low-level feedback signal ENB to the high-to-low module to convert the low-level feedback signal ENB into a low-voltage signal;
the low voltage signal and the low level feedback signal ENB are respectively transmitted to a second power supply voltage division module and a first power supply voltage division module to generate respective power-down voltage division, and are respectively transmitted to a second power supply threshold module and a first power supply threshold module to be compared, when the power-down voltage division is lower than the power-down threshold of the two threshold modules, the threshold module outputs a comparison result as a low level, and then the comparison result is transmitted to a buffer unit;
the buffer unit receives and outputs the low level of the comparison result, and the power-down protection of the circuit is completed.
Compared with the prior art, the invention has the following advantages:
firstly, the invention designs the power-on reset circuit comprising the power detection unit, and utilizes the band-gap-like reference structure of the first power threshold module and the threshold value of the device in the second power threshold module, thereby improving the precision of the power-on and power-off threshold values of the power-on reset circuit, ensuring the stability of the threshold value of the first power threshold module in the whole temperature range and reducing the difficulty of realizing the threshold value of the second power threshold module.
According to the invention, the power voltage is divided by the first power voltage dividing module and the second power voltage dividing module, and cascading resistors with different proportions are connected in series with the power voltage according to the existing output result of the power-on reset circuit, so that an adjustable hysteresis interval between the power-on threshold and the power-off threshold is obtained, and the stability of the power-on reset circuit in outputting a reset signal is improved.
Thirdly, the common node in the buffer unit is charged and discharged through the multipath output of the power supply detection unit, so that a plurality of power supply voltages with different power-on and power-off sequences can obtain required reset signals, the configuration difficulty of the multi-power-supply power-on reset circuit is reduced, an additional band-gap reference circuit is not needed, and the power consumption is reduced.
Drawings
FIG. 1 is an overall circuit block diagram of the present invention;
FIG. 2 is a circuit diagram of a power detection unit according to the present invention;
FIG. 3 is a circuit diagram of a buffer unit according to the present invention;
FIG. 4 is a waveform diagram of a node in the present invention, wherein the first power source is powered up before the second power source, and the second power source is powered down later;
FIG. 5 is a waveform diagram of a node in the present invention, wherein the first power supply is powered up later than the second power supply, and the second power supply is powered down earlier.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without making any creative effort shall fall within the protection scope of the present invention.
Referring to fig. 1, the power-on reset circuit for high-precision multi-power detection in the embodiment comprises a power detection unit 1 and a buffer unit 2, wherein the input end of the power detection unit 1 is connected with a feedback output end ENB of the buffer unit 2, the input end of the buffer unit 2 is connected with two output ends of the power detection unit 1, and a final output end EN of the buffer unit outputs a power-on reset signal. Wherein:
The power supply detection unit 1 comprises two power supply voltage division modules 11 and 14, two power supply threshold modules 12 and 15 and a high-to-low module 13. The first power supply voltage division module 11 is powered by a first power supply VDD1, the input end of the first power supply voltage division module is connected with a feedback output ENB of the buffer unit 2, the output end of the first power supply voltage division module is connected with the input end of a first power supply threshold module 12, the first power supply threshold module 12 is powered by the first power supply VDD1 and receives the output of the first power supply voltage division module 11, the output end of the first power supply voltage division module is connected with the input end of the buffer unit 2, the high-speed switching-low module 13 is simultaneously powered by the first power supply VDD1 and a second power supply VDD2, the input end of the high-speed switching-low module 13 is connected with the input end of the second power supply threshold module 14, the output end of the second power supply voltage division module 14 is connected with the input end of the buffer unit 2, and the output end of the second power supply threshold module 15 is simultaneously powered by the first power supply VDD1 and the second power supply VDD2 and receives the voltage division of the second power supply voltage division module 14;
The buffer unit 2 comprises two inverters, wherein the first inverter receives two paths of output of the power supply detection unit 1, outputs a feedback output signal ENB, and transmits the feedback output signal to the second inverter, and the second inverter finally outputs a power-on reset signal EN of the whole circuit.
Examples of the structure of each unit in the power-on reset circuit are given below:
Embodiment 1 construction of the power supply detection unit 1.
Referring to fig. 2, the two power voltage dividing modules 11 and 14, the two power threshold modules 12 and 15, and the high-to-low module 13 in the power detection unit 1 of this example are respectively configured as follows:
The first power voltage dividing module 11 comprises a first resistor R1, a second resistor R2, a third resistor R3 and a hysteresis transistor M1, wherein the head end of the first resistor R1 is connected with a first power supply VDD1, the tail end of the first resistor R1 is connected with the head end of the second resistor R2, the tail end of the second resistor R2 is connected with the head end of the third resistor R3, the tail end of the third resistor R3 is connected with a power supply ground, the hysteresis transistor M1 is a PMOS tube, the source electrode of the hysteresis transistor M is connected with the first power supply VDD1, the drain electrode of the hysteresis transistor M is connected with the tail end of the first resistor R1, and the grid electrode of the hysteresis transistor M is connected with a feedback output ENB of the buffer unit 2.
The first power supply threshold module 12 comprises threshold bipolar transistors Q0 and Q1, load transistors M2 and M3, a driving transistor M4, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a load capacitor C0, wherein bases of the threshold bipolar transistors Q0 and Q1 are respectively connected with output ends of the first power supply voltage dividing module 11, emitters of the threshold bipolar transistors are respectively connected with head ends of the fifth resistor R5 and the fourth resistor R4, collectors of the load transistors M2 and M3 are respectively connected with drains of the load transistors M2 and M3, gates of the load transistors M2 and M3 are PMOS transistors, collectors of the bipolar transistors Q0 are respectively connected with a first power supply VDD1, drains of the load transistors M4 are respectively connected with collectors of the bipolar transistors Q0 and Q1, sources of the drive transistors M4 are PMOS transistors, gates of the load transistors are connected with the first power supply VDD1, gates of the load transistors are connected with the heads of the sixth resistor R6 and the load capacitor C0, tails of the fourth resistor R4 and the fifth resistor R5 are respectively connected with the heads of the power supply voltage dividing module 11, drains of the load transistors are respectively connected with the heads of the fourth resistor R4 and the load transistors M3, drains of the load transistors are respectively connected with the heads of the power supply transistors of the fourth resistor transistors, the load transistors are connected with the power supply transistors, the power supply transistors are respectively.
The high-to-low module 13 comprises conversion pull-up transistors M13 and M15 and conversion pull-down transistors M14 and M16, wherein sources of the conversion pull-up transistors M13 and the conversion pull-down transistors M14 are respectively connected with a power supply VDD1 and a power supply ground, gates of the conversion pull-up transistors M13 and the conversion pull-down transistors M14 are respectively connected with an output ENB of the buffer unit 2, drains of the conversion pull-up transistors M15 and the conversion pull-down transistors M16 are respectively connected with a source of the conversion pull-up transistors M16, sources of the conversion pull-up transistors M15 and the conversion pull-down transistors M16 are respectively connected with a power supply VDD2 and a power supply ground, and drains of the conversion pull-up transistors M13 are used as output ends of the high-to-low module 13.
The second power voltage dividing module 14 includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a hysteresis transistor M9, where the head end of the seventh resistor R7 is connected to the second power supply VDD2, the tail end of the seventh resistor R7 is connected to the head end of the eighth resistor R8, the tail end of the eighth resistor R8 is connected to the head end of the ninth resistor R9, the tail end of the ninth resistor R9 is connected to the power supply ground, the hysteresis transistor M9 is a PMOS tube, the source of the hysteresis transistor M is connected to the second power supply VDD2, the drain of the hysteresis transistor M is connected to the tail end of the seventh resistor R7, and the gate of the hysteresis transistor M is connected to the output of the high-to-low module 13.
The second power threshold module 15 includes a weak pull-up transistor M10, a threshold transistor M11, and a pull-down transistor M12, where the weak pull-up transistor M10 is a PMOS transistor, its source is connected to the first power supply VDD1, its gate is connected to the power ground, and its drain is connected to the drain of the threshold transistor M11, the threshold transistor M11 is an NMOS transistor, its source is connected to the power ground, its gate is connected to the output of the second power voltage divider module 14, and the pull-down transistor M12 is an NMOS transistor, its source is connected to the power ground, its gate is connected to the drain of the threshold transistor M11, and its drain is used as the output of the module.
Embodiment 2 structure of the buffer unit 2.
Referring to fig. 3, the first inverter and the second inverter in the buffer unit 1 of the present example are respectively configured as follows:
The first inverter comprises a first buffer pull-up transistor M5 and a first buffer pull-down transistor M6, wherein the source electrode of the first buffer pull-up transistor M5 is connected with a first power supply VDD1, the grid electrode of the first buffer pull-up transistor M5 is connected with the grid electrode of the first buffer pull-down transistor M6, the grid electrode is used as an input end of the buffer unit 2, the drain electrode of the first buffer pull-down transistor M6 is connected with the drain electrode of the first buffer pull-down transistor M6, the source electrode of the first buffer pull-down transistor M6 is connected with the power supply ground, the grid electrode of the first buffer pull-up transistor M5 is connected with the grid electrode, and the drain electrode of the first buffer pull-down transistor M6 is used as an ENB output end of the buffer unit 2;
The second inverter comprises a second buffer pull-up transistor M7 and a second buffer pull-down transistor M8, wherein the source electrode of the second buffer pull-up transistor M7 is connected with the first power supply VDD1, the grid electrode of the second buffer pull-up transistor M8 is connected with the grid electrode of the second buffer pull-down transistor M8, the drain electrode of the second buffer pull-down transistor M8 is connected with the drain electrode of the second buffer pull-down transistor M8, the source electrode of the second buffer pull-down transistor M8 is connected with the power supply ground, the grid electrode of the second buffer pull-up transistor M7 is connected with the grid electrode, and the drain electrode of the second buffer pull-down transistor M8 is used as an EN output end of the buffer unit 2.
Embodiment 3 Power-on reset based on the above-described circuitry.
The power-on reset is performed in the power-on process of the first power supply VDD1 and the second power supply VDD2, and at this time, the rest circuits on the chip are all in an initial reset state, so that in order to make the chip enter a working state, the power-on reset circuit is required to change the output EN signal from low level to high level and output the EN signal to the circuits when the two power supply voltages are both greater than the power-on threshold value of the respective power supply domain, and the power-on reset is completed.
The method for performing power-on reset by using the circuit in the embodiment comprises the following steps:
Setting the first power supply VDD1 and the second power supply VDD2 to enter a power-on state, so that the power supply voltage is gradually increased, and at the moment, the power supply detection unit 1 receives a high-level feedback signal ENB of the buffer unit 2 and transmits the high-level feedback signal ENB to the high-to-low module 13 to convert the high-level feedback signal ENB into a low-voltage signal;
the low voltage signal is transmitted to a transistor M9 in the second power supply voltage division module 14 and is turned off so as to obtain the power-on voltage division of the second power supply voltage division module 14, the power-on voltage division is transmitted to a threshold transistor M11 in the second power supply threshold module 15 so that the transistor M11 generates a current, and when the current is larger than a pull-up current generated by a weak pull-up transistor M10, a pull-down transistor M12 is turned off so that the second power supply threshold module 15 does not output the pull-down current;
The high-level feedback signal ENB is transmitted to a transistor M1 in the first power supply voltage division module 11 and is turned off, so that the power-on voltage division of the first power supply voltage division module 11 is obtained, the power-on voltage division is transmitted to threshold bipolar transistors Q0 and Q1 in the first power supply threshold module 12 and generates two paths of branch currents, the first branch current generated by the transistor Q0 is copied through load transistors M2 and M3, and if the copied first branch current is smaller than the second branch current generated by the transistor Q1, the gate voltage of a driving transistor M4 is reduced, so that the first power supply threshold module 12 outputs a high level;
The buffer unit 2 receives the high level output of the first power threshold module 12, and outputs a high level EN signal to complete the power-on reset of the circuit since the second power threshold module 15 does not output the pull-down current.
Example 4 power down protection based on the above described circuitry.
The power-down protection occurs in the power-down process of the first power supply VDD1 and the second power supply VDD2, and other circuits on the chip are all in a working state at this time, so that the circuits are required to be in a reset state for protection in order to avoid abnormal working of the circuits during power-down. When any one of the two power supply voltages of the power-on reset circuit is smaller than the power-off threshold value, the output EN signal is changed from a high level to a low level and is output to the circuits, and the power-off protection of the circuits is completed.
The method for power-down protection by using the circuit in the embodiment comprises the following steps:
Setting the first power supply VDD1 and the second power supply VDD2 to enter a power-down state, so that the power supply voltage is gradually reduced, and at the moment, the power supply detection unit 1 receives a low-level feedback signal ENB of the buffer unit 2 and transmits the low-level feedback signal ENB to the high-to-low module 13 to convert the low-level feedback signal ENB into a low-voltage signal;
The low voltage signal is transmitted to a transistor M9 in the second power supply voltage division module 14 and is conducted so as to obtain the power-down voltage division of the second power supply voltage division module 14, the power-down voltage division is transmitted to a threshold transistor M11 in the second power supply threshold module 15, the generated pull-down current is smaller than the pull-up current generated by a weak pull-up transistor M10, so that the pull-down transistor M12 is conducted so as to enable the second power supply threshold module 15 to output the pull-down current;
The high-level feedback signal ENB is transmitted to a transistor M1 in the first power supply voltage division module 11 and is conducted, so that the power-down voltage division of the first power supply voltage division module 11 is obtained, the power-down voltage division is transmitted to threshold bipolar transistors Q0 and Q1 in the first power supply threshold module 12 and generates two paths of branch currents, the first branch current generated by the transistor Q0 is copied through load transistors M2 and M3, and the copied first branch current is larger than the second branch current generated by the transistor Q1, so that the grid voltage of a driving transistor M4 is increased, and the first power supply threshold module 12 outputs a low level;
The buffer unit 2 receives the low level output of the first power threshold module 12, and outputs a low level EN signal due to the output of the pull-down current by the second power threshold module 15, thereby completing the power-down protection of the circuit.
The effect of the present invention can be further illustrated by the following simulation experiment.
Simulation conditions
Using cadance virtuoso software, the temperature was set at 27 ℃, the first supply voltage at 2.5V, and the second supply voltage at 1.2V.
Second, simulation content
Simulation 1, according to the above simulation conditions, for the power-on reset circuits of embodiments 1 and 2 of the present invention, a time sequence simulation is performed that the first power supply is powered on before the second power supply and is powered off later than the second power supply, and the result is shown in fig. 4, where the power-on threshold and the power-off threshold of the first power supply are respectively 2.3V and 1.53V, the voltage of the node C changes along with the change of the second power supply, and after the voltage of the node C is greater than the threshold voltage, the voltage of the node B is increased, so as to output a high level EN signal, and the voltage of the output node D of the feedback output ENB signal passing through the high-to-low module is pulled down.
Simulation 2, according to the above simulation conditions, for the power-on reset circuits of embodiments 1 and 2 of the present invention, a time sequence simulation is performed that the first power supply is powered on later than the second power supply and the second power supply is powered off earlier, and the result is shown in fig. 5, where the power-on threshold and the power-off threshold of the second power supply are respectively 0.92V and 0.73V, the voltage of the node a changes along with the change of the first power supply, and after the voltage of the node a is greater than the threshold voltage, the voltage of the node B is raised, so as to output a high level EN signal, and the voltage of the output node D of the feedback output ENB signal passing through the high-to-low module is pulled down.
As can be seen from fig. 4 and fig. 5, the power-on reset circuits of the embodiments 1 and 2 of the present invention output the high-level EN signal only when the first power supply and the second power supply are both greater than the power-on threshold value, so as to complete the power-on reset of the circuits. And outputting a low-level EN signal when any one of the first power supply and the second power supply is smaller than a power-down threshold value, so as to complete power-down protection of the circuit.
The simulation result shows that the power-on reset circuit can perform power-on reset and power-off protection on multiple power supplies, has a power-on threshold and a power-off threshold with higher precision, and has an adjustable hysteresis interval between the two thresholds.
The above description is only a few specific examples of the present invention and does not constitute any limitation of the present invention, it will be apparent to those skilled in the art that various modifications and changes in form and details may be made without departing from the principles and structure of the present invention, for example, the number of the modules may be increased or decreased by the power detection unit in addition to a second power voltage dividing module and a second power threshold module given in this example, the ratio and size may be modified by the two power voltage dividing modules in addition to the ratio and size of the cascade resistor string unit given in this example, the size and ratio may be modified by the first power threshold module in addition to the two bipolar transistors and the two resistors given in this example, the size and ratio may be increased or decreased by the second power threshold module in addition to a weak pull transistor and a threshold transistor given in this example, the number of the transistors may be increased or decreased by the number of the transistors in addition to the connection relationship of the elements in each example, and the connection may be changed based on the invention as claimed herein.
Claims (10)
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| CN202411992740.8A CN119906402A (en) | 2024-12-31 | 2024-12-31 | High-precision multi-power supply detection power-on reset circuit |
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| CN202411992740.8A CN119906402A (en) | 2024-12-31 | 2024-12-31 | High-precision multi-power supply detection power-on reset circuit |
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