CN119892103A - Data compression chip and data compression method - Google Patents

Abstract

The data compression chip comprises a data conversion circuit, a data coding circuit, an AXI interface and a buffer unit, wherein the data conversion circuit is used for receiving input data from the AXI interface, carrying out data conversion on the input data to obtain deformed data, the data conversion comprises symbol bit rotation, comparison increment operation, bit plane conversion and bit exclusive OR operation, and the data coding circuit is used for carrying out bit plane data coding and structural rearrangement on the deformed data when receiving a data output request to obtain compressed data and outputting the compressed data through the AXI interface. The compression algorithm is converted into a hardware circuit, a special chip for data compression is provided for data transmission, the data transmission rate of data between the chips can be improved, and the data bandwidth pressure is reduced.

Description

Data compression chip and data compression method

Technical Field

The disclosure relates to the technical field of data processing, and in particular relates to a data compression chip and a data compression method.

Background

With the advent of the big data age, the generation and processing of data has become an integral part of daily life and work. However, due to the huge amount of data, its storage and transmission becomes a big challenge. In order to alleviate the data read speed gap between the computing unit and the storage unit, a multi-level SRAM cache is provided in the processor. The closer the cache is to the computing unit, the smaller its space and the faster the read speed. But still requires a bus connection between the processor and the memory, and a connection between each level of cache. International semiconductor blueprints (International Technology Roadmap for Semiconductors, ITRS) indicate that the annual increase in pin speed is less than 10%, while the increase in bandwidth per pin also results in the need to configure additional circuitry for the high-speed interface, which consumes additional static and dynamic power. Therefore, research on data compression algorithms can more effectively cope with increasing challenges than increasing physical bandwidth, and is one of the effective methods for solving the problem of bandwidth wall caused by von neumann architecture.

If the data compression algorithm is applied in the data transmission process to accelerate the transmission rate between the chips, the conventional algorithm has the defects that, for example, the conventional data compression algorithm uses software in a computer to compress data, the most important index is the data compression rate, so that the algorithm is often complex, and the data compression algorithm commonly used at present is compressed by means of front-back data association or large-scale dictionary establishment, the process is usually performed in a software mode, the implementation by hardware is difficult, and the compression and decompression processes consume a great amount of time, so that the requirement for data transmission is difficult to meet.

Disclosure of Invention

In order to solve the technical problems, the present disclosure provides a data compression chip and a data compression method.

According to an aspect of the present disclosure, there is provided a data compression chip comprising a data conversion circuit, a data encoding circuit and an AXI interface, wherein,

The data conversion circuit is used for receiving input data from the AXI interface, and carrying out data conversion on the input data to obtain deformed data, wherein the data conversion comprises symbol bit rotation, comparison increment operation, bit plane conversion and bitwise exclusive OR operation;

The data coding circuit is used for carrying out bit plane data coding and structural rearrangement on the deformed data when receiving a data output request to obtain compressed data, and outputting the compressed data through the AXI interface.

According to another aspect of the present disclosure, there is also provided a data compression method, which is applied to the data compression chip as described above, the method including:

Receiving input data, and performing data transformation on the input data to obtain deformed data, wherein the data transformation comprises symbol bit rotation, comparison increment operation, bit plane transformation and bitwise exclusive OR operation;

and when a data output request is received, carrying out bit plane data coding and structural rearrangement on the deformed data to obtain compressed data.

The present disclosure also provides an electronic device including:

A processor;

A memory for storing the processor-executable instructions;

the processor is configured to read the executable instructions from the memory and execute the instructions to implement the data compression method described above.

The present disclosure also provides a computer-readable storage medium storing a computer program for executing the above-described data compression method.

Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:

The data compression chip comprises a data conversion circuit, a data coding circuit, an AXI interface and a buffer unit, wherein the data conversion circuit is used for receiving input data from the AXI interface, carrying out data conversion on the input data to obtain deformed data, the data conversion comprises symbol bit rotation, comparison increment operation, bit plane conversion and bitwise exclusive OR operation, and the data coding circuit is used for carrying out bit plane data coding and structural rearrangement on the deformed data when a data output request is received to obtain compressed data and outputting the compressed data through the AXI interface. The data compression chip is formed by taking a data conversion comprising symbol bit rotation, comparison increment operation, bit plane conversion and bitwise exclusive OR operation as an improved bit plane compression algorithm, taking a data conversion circuit and a data coding circuit as a main body framework based on the improved bit plane compression algorithm, and further comprising a buffer unit and an AXI interface structure, and the compression algorithm is converted into a hardware circuit based on the buffer unit and the AXI interface structure, so that a special chip for data compression is provided for data transmission, the data transmission rate between chips is improved, and the data bandwidth pressure is reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

FIG. 1 is a block diagram of a data compression chip according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a workflow of a data compression chip according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a bit-plane conversion unit according to an embodiment of the disclosure;

FIG. 4 is a schematic diagram of a bit-plane transformation process according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a full cache array according to an embodiment of the disclosure;

FIG. 6 is a schematic diagram of a process for encoding bit-plane data according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a ping-pong buffer according to an embodiment of the present disclosure;

FIG. 8 is a flow chart of a data compression method according to an embodiment of the disclosure;

Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein, and it is apparent that the embodiments in the specification are only some, rather than all, of the embodiments of the present disclosure.

Aiming at the problems of complex algorithm, lack of hardware realization and the like in the traditional data compression algorithm, the present disclosure provides a data compression chip and a data compression method. The data compression chip in the scheme is a data lossless compression algorithm chip, uses an improved bit plane compression algorithm, takes a data conversion circuit and a data coding circuit as the framework main body of the chip, and also comprises a buffer unit, an AXI interface and other structures. For ease of understanding, embodiments of the present disclosure are described below.

Referring to fig. 1, a data compression chip according to an embodiment of the present disclosure includes at least a data conversion circuit 110, a data encoding circuit 120, and an AXI (Advanced eXtensible Interface, bus protocol) interface 140.

In another embodiment, the data compression chip may further include a buffer unit 130 connected between the data conversion circuit 110 and the data encoding circuit 120, the buffer unit 130 including a plurality of buffer arrays. Based on this, the data compression chip may use the data conversion circuit 110 and the data encoding circuit 120 as architecture bodies, and further includes the buffer unit 130 and the AXI interface 140.

In the above embodiment, the data conversion circuit 110 is configured to receive input data from the AXI interface 140, and perform data conversion on the input data to obtain deformed data, where the data conversion includes symbol bit rotation, comparison increment operation, bit plane conversion, and bitwise exclusive or operation. The deformed data obtained by the data conversion circuit 110 may be temporarily stored in the buffer unit 130 or directly output to the data encoding circuit 120.

The buffer unit 130 is configured to buffer the deformed data of the data conversion circuit 110.

The data encoding circuit 120 is configured to, when receiving a data output request, perform bit-plane data encoding and structural rearrangement on the deformed data to obtain compressed data, and output the compressed data through the AXI interface 140.

Specifically, after the data conversion circuit 110 performs data conversion on the input data, the buffer unit 130 may temporarily store the deformed data, and wait for a data output request from the outside. When the buffer unit 130 is not empty, the data encoding circuit 120 obtains the temporarily stored deformed data from the buffer unit 130 when receiving the data output request, performs bit plane data encoding on the deformed data, rearranges the data encoding structure, and splices the rearranged data encoding structure into 32 bits for output.

Based on the above data compression chip, the workflow thereof may be shown with reference to fig. 2, including the following steps S202 to S212.

Step S202, receiving input data to be processed, wherein the input data comprises, but is not limited to, data in FP32, FP16, INT32 and INT8 formats.

And step S204, carrying out data transformation on the input data based on the improved bit plane compression algorithm to obtain deformed data, wherein the data transformation carried out by the improved bit plane compression algorithm comprises symbol bit rotation, comparison increment operation, bit plane transformation and bitwise exclusive OR operation.

When the step is realized by the data conversion circuit, the data conversion circuit controls the execution of data conversion by a state machine and temporarily stores the data in conversion by the data conversion array. The data conversion circuit comprises a plurality of bit plane conversion units, and the bit plane conversion unit can comprise a data conversion array and a first register (namely data_in_reg1), a second register (namely data_in_reg2), a third register (namely dbx_reg1) and a fourth register (namely dbx_reg2) which are connected with the data conversion array, wherein the first register and the second register are arranged at a data input end, and the third register and the fourth register are arranged at a data output end, as shown in a schematic diagram of a circuit structure of a single bit plane data conversion unit in fig. 3. In fig. 3, the state machine is composed of the above-described plurality of registers and combinational logic circuits.

Based on the circuit structure of the above bit plane conversion unit, the present embodiment provides a method for performing data conversion on input data to obtain deformed data, which includes the following matters.

(1) The sign bit rotating process comprises the steps of carrying out sign bit rotation on input data of a current clock cycle to obtain first data, storing the first data into a first register, and transmitting second data of a previous clock cycle in the first register to a second register.

In this embodiment, when the data transmission start signal is received, the state machine of the bit plane data conversion unit will switch from the idle state to the compare delta operation state, receiving the input data at the current clock cycle.

In one example, where the input data for the current clock cycle is valid 32-bit data, the input data is sign bit rotated. The sign bit rotation can be understood as circularly shifting the input data to the left, namely shifting the sign bit of the floating point number from the highest bit to the lowest bit, shifting the rest bit data to the left by one bit, and completing the operation of sign bit rotation to obtain the first data. Then, the first data is assigned to a first register, and the first register is a first-stage register data_in_reg1; and transferring second data existing in the first register at the last clock cycle to a second register, wherein the second register is a second-stage register data_in_reg2.

It will be appreciated that the current clock cycle is a relative concept for characterizing a time period for receiving input data and performing symbol bit rotation, and similarly, the first data and the second data are opposite, and are data after symbol bit rotation corresponding to the upper clock cycle and the lower clock cycle, that is, the first data in the first register in the last clock cycle becomes the second data to be transferred to the second register by the current clock cycle, and so on, the first data in the first register in the current clock cycle becomes the second data to be transferred to the second register by the next clock cycle.

In another example, in the case where the input data of the current clock cycle is data with a bit width smaller than 32 bits (such as 16-bit data or 8-bit data), the data to be input is first subjected to sign bit rotation, and then the high bits of the data after the sign bit rotation are supplemented by 0 until the bit width reaches 32 bits, that is, the data after the sign bit rotation is placed at the low bits of the 32-bits, and the high bits of the 32-bits are filled with 0, thereby obtaining the first data. And transferring second data present in the first register for a last clock cycle to the second register.

(2) The comparison increment operation process comprises the steps of comparing the first data with the second data to obtain third data, writing the third data into a data conversion array, and storing the third data with a plurality of clock cycles in the data conversion array according to the column direction.

After storing the first data of the current clock cycle in the first register and transferring the second data of the previous clock cycle in the first register to the second register, the embodiment performs a comparison increment operation on the first data of the first register and the second data of the second register. The specific implementation process can comprise the following steps:

The method comprises the steps of comparing the value of first data with the value of second data, subtracting the value of data with a small value from the value of data with a large value according to a comparison result to obtain a difference value with an increment operation of 32-bits which is low, adding a high-order expansion bit on the basis of the difference value to obtain third data, wherein the high-order expansion bit is a first value of 0 if the value of the first data is larger than or equal to the value of the second data, and is a second value of 1 if the value of the first data is smaller than the value of the second data.

And comparing the increment operation with the high-order expansion bit to obtain 33-bit data as third data, and writing the third data into the data conversion array.

The above embodiment can obtain the third data of the plurality of clock cycles, and then, in the data conversion array, the third data of the plurality of clock cycles is stored in the column direction.

(3) The bit plane transformation process comprises the step of carrying out bit plane transformation on the data in the data transformation array to obtain bit plane transformation data.

In a data conversion array in which data is stored in the column direction, the first column is said to be the base number. In the process of carrying out bit plane transformation on each column of data in the data transformation array, splitting the data except the basic data, and recombining the same weight bits of the original data. Referring to fig. 4, when receiving the bit plane conversion start signal, the data conversion circuit sequentially reads data while keeping the data in the data conversion array unchanged, records the base_data of the base number in the first column and keeps unchanged, and then changes the column-by-column reading from row-by-row reading when reading the data except the base number, that is, the data of the highest order of each column forms the first new data arranged in the row direction, the data of the next highest order forms the second new data arranged in the row direction, and so on until the data of the lowest order forms the last new data arranged in the row direction, and the new data is recorded as data dbp_flag.

When data except the basic number are read, the row with the full '0' value can be recorded, and if the new data dbp_flag is read to be the full '0' value, the subscript register corresponding to the new data dbp_flag is assigned to be '1'.

And forming bit plane conversion data by a column of basic numbers and new data of each line after conversion through the bit plane conversion.

(4) The bit exclusive OR operation process comprises the steps of sequentially reading one row of bit plane conversion data in the data conversion array from the second clock period, storing the read bit plane conversion data in the third register, transmitting the data in the third register in the last clock period to the fourth register, and carrying out bit exclusive OR operation on the data in the third register and the data in the fourth register to obtain deformed data.

In this embodiment, when the bitwise exclusive or operation start signal is received, the first clock cycle outputs a base number of 32 bits, and from the second clock cycle, the upper 31 bits of one line of data in the data conversion array are read every clock cycle, stored in the third register (i.e., the first-stage register dbx_reg1), and the data read in the last clock cycle is stored in the fourth register (i.e., the second-stage register dbx_reg2).

And then, carrying out bit exclusive OR operation on the data in the third register and the data in the fourth register, and sequentially reading the last data to obtain deformed data. The exclusive-or operation is characterized by an output of "0" when the input is two identical values, and for an input in which a mutation occurs in the data, it is possible to generate "1" of consecutive bits after the increment calculation (of course, the present embodiment reduces the generation of the "1" value by comparing the increment operation), and becomes "1" of the same weight bits of the plurality of data after the bit plane conversion, which are converted to "0" by the exclusive-or operation. Therefore, the embodiment can further extract the characteristics of the data for compression through bitwise exclusive OR operation, and improves the data compression capability.

In this embodiment, after the last bit plane conversion data in the data conversion array is sequentially read, the end signal corresponding to the bitwise exclusive or operation is set to high, and the state machine of the bit plane conversion unit is switched to the idle state to wait for the arrival of the next data transmission start signal.

At the level of the data conversion circuit, in three main stages of the bit plane data conversion process, the comparison increment operation writes data into the data conversion array, the bit plane conversion and the exclusive OR operation read data from the data conversion array, and in the process of reading the data, the data conversion array cannot write new data, and before the data conversion is completed, the data conversion array cannot output a result. Based on this, in order to maintain continuous data transmission and improve throughput efficiency, both the input and output of the data conversion array in the present embodiment use a pipeline structure.

For the pipeline of the input of the data transformation array, when the writing of the first-stage array is completed and the data transformation is carried out, if new data enters, the new data is written into the second-stage array, when the writing of the second-stage array is completed and the new data is written into the third-stage array, when the writing of the third-stage array is completed, the first-stage array finishes the data transformation, and the result is transferred to the buffer unit and can be written into the new data. If the signal that the buffer is full is received, the data input is suspended, the state of the input state machine is kept, and the data in the data conversion array is temporarily stored in the array and is not output. The output pipeline structure of the data conversion array is the same, the first-stage array enters the writing state again after finishing the data output of the buffer unit, the second-stage array starts to output data to the buffer unit, and the third-stage array continues to output data after finishing the output of the second-stage array.

According to the embodiment, the pipeline structure is used for the input and the output of the data transformation array, the pipeline structure is tightly combined with the data transformation process of the data compression algorithm, continuous input data can be processed, and the deformation can be integrated according to the data block mode.

Step S206, judging whether the data does not need to be cached, namely judging whether the deformed data is directly output to the data coding circuit.

Step S208, if the buffer is needed, the deformed data is stored in the buffer unit.

In the above embodiment, the data transformation of the input data is the most dominant and time-consuming process, and since the transformed deformed data is still stored in the form of a block, if the deformed data does not need to be directly encoded and output, the deformed data after the data transformation needs to be buffered. The cache unit includes a plurality of cache arrays, for example, 8 cache arrays in total. The structure of the buffer unit is similar to that of the data conversion array, but the function of the buffer unit only comprises reading and writing, and logic operation is not involved. The multiple cache arrays meet the following requirements that 1) the writing and the reading of data blocks in the cache arrays are required to be completed according to the same sequence, namely, the data blocks written first are required to be read first, 2) when one cache array is writing, the other cache array can be read, 3) the address management of the cache arrays is simple enough, and whether the cache arrays are fully written or fully empty can be judged according to the addresses. FIG. 5 shows a case where the buffer array is full, the buffer unit generates a buffer full signal, back-pressures the input data, and pauses the storage of new data before there is data output and an empty buffer array is generated.

Step S210, if no buffer is needed, outputting the deformed data to the data encoding circuit.

In step S212, the data encoding circuit performs bit plane data encoding and structural rearrangement on the deformed data to obtain compressed data.

When the data encoding circuit receives the data output request, the data encoding circuit can read the deformed data from the buffer unit, or can directly receive the deformed data from the data conversion circuit. The data coding circuit comprises a data coding unit and a structure rearrangement unit, wherein the data coding unit is used for carrying out bit plane data coding on deformed data to obtain coded data, the bit plane data coding comprises basic number coding, zero value run coding and frequent mode coding, and the structure rearrangement unit is used for carrying out structure rearrangement on the coded data by using a ping-pong buffer to obtain compressed data.

In this embodiment, the data encoding unit may include three encoding modes, namely, base number encoding, zero-value run length encoding and frequent mode encoding, and one specific mode of bit-plane data encoding of the deformed data by the data encoding unit may be shown in fig. 6.

And if the deformation data is the basic number, performing basic number coding on the basic number to obtain coded data. The base number encoding is used only for the base number.

If the number is not the basic number, judging whether the deformation data is the total 0 number, if the number is the total 0 number, carrying out zero value run-length coding on the deformation data to obtain coded data, and if the number is not the total 0 number, carrying out frequent mode coding on the deformation data to obtain the coded data.

In one implementation, zero-value run-length encoding is preferentially used for the morphed data, and if the morphed data is all "0" values, the zero-value counter is incremented by one, and no encoded data is generated. If the deformation data is a value other than 0, the state of a zero value counter is judged, if the previous deformation data is a value other than 0, zero value run-length coding is finished, the run-length coding is generated, and meanwhile, frequent mode coding is carried out, and then the two codes are spliced, and if the previous deformation data is a value other than 0, only frequent mode coding is carried out.

In addition, the frequent pattern coding has a priority order, whether the deformed data is a full '1' value is judged firstly, if not, whether the deformed data is a full '0' value before bitwise exclusive OR operation is judged according to the carried dbx_flag, and if not, pattern matching is attempted with the data type with only single '1', only two continuous '1' or other types, and corresponding coded data is generated.

The encoded data corresponding to the deformed data is obtained through the above embodiment, and the encoded data is output after being rearranged into compressed data in a 32-bit form through a structure.

The structure rearrangement unit in this embodiment uses Ping-pong buffer (Ping-pong buffer) structure to perform structure rearrangement and output, so as to avoid that code overflow cannot be temporarily stored, and influence data output efficiency. As shown in FIG. 7, a ping-pong buffer pp_buf [63:0] is established, and whether the ping-pong buffer is used for writing data or reading data is the upper 32 bits or the lower 32 bits is controlled by a strobe signal. When the high-32 bit buffer pp_buf [63:32] writes coded data, the data is read from the low-32 bit buffer pp_buf [31:0], the high-32 bit buffer is alternated after the writing is finished, the data is read from the high-32 bit buffer, the low-32 bit buffer is written, and the continuous output of the data is ensured by twice the storage space. FIG. 7 illustrates that when the upper 32-bit buffer is full, the remaining data bits of the current data are written to the lower 32-bit buffer and then the upper 32-bit buffer is output.

The above embodiment sets the data coding unit with coding priority and the structure rearrangement unit with ping-pong buffer, transforms the data of types including, but not limited to, FP32, INT8, etc. into the data block formed after the bit plane data transformation, applies the coding method to transform the data block into the coded data, rearranges the coded data into the 32-bit form for output, and can realize higher compression rate.

In summary, the data compression chip provided by the embodiment of the disclosure includes a data conversion circuit, a data encoding circuit, an AXI interface, and a buffer unit, where the data conversion circuit is configured to receive input data from the AXI interface, perform data conversion on the input data to obtain deformed data, where the data conversion includes symbol bit rotation, comparison increment operation, bit plane conversion, and bitwise exclusive or operation, and the data encoding circuit is configured to perform bit plane data encoding and structural rearrangement on the deformed data when receiving a data output request, to obtain compressed data, and output the compressed data through the AXI interface. The data compression chip is formed by taking a data conversion comprising symbol bit rotation, comparison increment operation, bit plane conversion and bitwise exclusive OR operation as an improved bit plane compression algorithm, taking a data conversion circuit and a data coding circuit as a main body framework based on the improved bit plane compression algorithm, and further comprising a buffer unit and an AXI interface structure, and the compression algorithm is converted into a hardware circuit based on the buffer unit and the AXI interface structure, so that a special chip for data compression is provided for data transmission, the data transmission rate between chips is improved, and the data bandwidth pressure is reduced.

As shown in a flowchart of a data compression method in fig. 8, an embodiment of the present disclosure provides a data compression method, which is applied to the data compression chip described in the foregoing embodiment, where the data compression method in the present embodiment may include:

step S302, receiving input data, and carrying out data transformation on the input data to obtain deformed data, wherein the data transformation comprises symbol bit rotation, comparison increment operation, bit plane transformation and bitwise exclusive OR operation;

And step S304, when a data output request is received, bit plane data coding and structural rearrangement are carried out on the deformed data, so as to obtain compressed data.

The method provided in this embodiment has the same implementation principle and technical effects as those of the foregoing data compression chip embodiment, and for brevity, reference may be made to the corresponding content in the foregoing data compression chip embodiment where no mention is made in the method embodiment section.

Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the disclosure. As shown in fig. 4, electronic device 400 includes one or more processors 401 and memory 402.

The processor 401 may be a Central Processing Unit (CPU) or other form of processing unit having data processing capabilities and/or instruction execution capabilities and may control other components in the electronic device 400 to perform desired functions.

Memory 402 may include one or more computer program products that may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. The volatile memory may include, for example, random Access Memory (RAM) and/or cache memory (cache), and the like. The non-volatile memory may include, for example, read Only Memory (ROM), hard disk, flash memory, and the like. One or more computer program instructions may be stored on the computer readable storage medium that can be executed by the processor 401 to implement the data compression method and/or other desired functions of the embodiments of the present disclosure described above. Various contents such as an input signal, a signal component, a noise component, and the like may also be stored in the computer-readable storage medium.

In one example, electronic device 400 may also include input device 403 and output device 404, which are interconnected by a bus system and/or other form of connection mechanism (not shown).

In addition, the input device 403 may also include, for example, a keyboard, a mouse, and the like.

The output device 404 may output various information to the outside, including the determined distance information, direction information, and the like. The output device 404 may include, for example, a display, speakers, a printer, and a communication network and remote output devices connected thereto, etc.

Of course, only some of the components of the electronic device 400 that are relevant to the present disclosure are shown in fig. 9 for simplicity, components such as buses, input/output interfaces, and the like are omitted. In addition, electronic device 400 may include any other suitable components depending on the particular application.

Further, the present embodiment also provides a computer-readable storage medium storing a computer program for executing the above-described data compression method.

The embodiment of the disclosure provides a data compression method, apparatus, electronic device, and computer program product of a medium, including a computer readable storage medium storing program codes, where the instructions included in the program codes may be used to execute the method described in the foregoing method embodiment, and specific implementation may refer to the method embodiment and will not be repeated herein.

It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.

The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A data compression chip is characterized by comprising a data conversion circuit, a data coding circuit and an AXI interface, wherein the data conversion circuit is connected with the data coding circuit,

The data conversion circuit is used for receiving input data from the AXI interface, and carrying out data conversion on the input data to obtain deformed data, wherein the data conversion comprises symbol bit rotation, comparison increment operation, bit plane conversion and bitwise exclusive OR operation;

The data coding circuit is used for carrying out bit plane data coding and structural rearrangement on the deformed data when receiving a data output request to obtain compressed data, and outputting the compressed data through the AXI interface.

2. The data compression chip of claim 1, wherein the data conversion circuit comprises a plurality of bit plane conversion units;

the bit plane conversion unit comprises a data conversion array, and a first register, a second register, a third register and a fourth register which are connected with the data conversion array, wherein the first register and the second register are arranged at a data input end, and the third register and the fourth register are arranged at a data output end.

3. The data compression chip of claim 2, wherein the performing data transformation on the input data to obtain deformed data comprises:

the input data of the current clock period is subjected to sign bit rotation through the state machine to obtain first data, the first data are stored in the first register, and second data existing in the first register in the last clock period are transmitted to the second register;

Comparing the first data with the second data for incremental operation to obtain third data;

writing the third data into the data transformation array;

Storing the third data of a plurality of clock cycles in a column direction in the data conversion array;

Performing bit plane transformation on the data in the data transformation array to obtain bit plane transformation data;

sequentially reading one row of the bit plane conversion data in the data conversion array from the second clock period, storing the read bit plane conversion data into a third register, and transmitting the data in the third register in the last clock period to the fourth register;

And performing bit exclusive OR operation on the data in the third register and the data in the fourth register to obtain deformed data.

4. The data compression chip of claim 2, wherein the state machine switches to an idle state after sequentially reading the last bit-plane transformed data in the data transformation array, and setting an end signal corresponding to a bitwise exclusive or operation high.

5. The data compression chip of claim 2, wherein the input and output of the data transformation array each use a pipeline structure.

6. The data compression chip of claim 1, further comprising a buffer unit coupled between the data transformation circuit and the data encoding circuit, the buffer unit comprising a plurality of buffer arrays for buffering the deformed data of the data transformation circuit.

7. The data compression chip of claim 1, wherein the data encoding circuit comprises a data encoding unit and a structural rearrangement unit, wherein,

The data coding unit is used for carrying out bit plane data coding on the deformed data to obtain coded data, wherein the bit plane data coding comprises basic number coding, zero value run coding and frequent mode coding;

The structure rearrangement unit is used for carrying out structure rearrangement on the coded data by using a ping-pong buffer memory to obtain compressed data.

8. The data compression chip of claim 7, wherein the data encoding unit is further configured to:

judging whether the deformation data is a basic number or not;

if the basic number is the basic number, performing basic number coding on the basic number to obtain coded data;

if the deformation data is not the basic number, judging whether the deformation data is the total 0 number or not;

if the number is all 0, carrying out zero value run-length coding on the deformed data to obtain coded data;

And if the number is not all 0, carrying out frequent mode coding on the deformed data to obtain coded data.

9. The data compression chip of claim 7, wherein the structural rearrangement unit is further configured to:

whether the ping-pong buffer is used for writing data or reading data is the upper 32 bits or the lower 32 bits is controlled by a strobe signal.

10. A data compression method, characterized in that the method is applied to the data compression chip of any one of claims 1 to 9, the method comprising:

Receiving input data, and performing data transformation on the input data to obtain deformed data, wherein the data transformation comprises symbol bit rotation, comparison increment operation, bit plane transformation and bitwise exclusive OR operation;

and when a data output request is received, carrying out bit plane data coding and structural rearrangement on the deformed data to obtain compressed data.