CN119889414B - Personalized repair method of memory chip based on test equipment - Google Patents
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Abstract
The invention relates to the technical field of chip testing, in particular to a personalized repair method of a memory chip based on test equipment, which comprises the steps of respectively acquiring a failure unit circuit set of each memory chip in a CP front-stage test stage and a FT back-stage test stage; the method comprises the steps of respectively constructing adjacent matrixes corresponding to failure unit circuit sets, calculating union sets, dividing to obtain data feature sets, carrying out cluster analysis on the data feature sets, extracting failure unit distribution derivatization rules, constructing a derivatization rule base, calculating pearson correlation analysis between failure unit distribution in a sliding window and a derivatization rule element matrix to obtain failure units of derivatization analysis, adding the failure units into the sparse failure unit sets for normal solution analysis, and judging whether a chip is good or not according to whether chip redundancy resources meet preset solution conditions. The invention can solve the problem of unstable sparse units to a certain extent and increase the yield of the memory chip.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a personalized memory chip repairing method based on testing equipment.
Background
The testing of the memory chip mainly comprises a functional test, a performance test and a reliability test. The test machine verifies whether the memory chip can correctly store and restore data by writing data into each memory cell of the memory and then reading the data and comparing the data with the written data. These failed unit circuits are then grasped by the machine. In order to ensure the normal working function of the chip, a standby circuit is arranged in the memory chip to repair the failure unit circuit. The standby circuits are mainly divided into two types, namely a row standby circuit and a column standby circuit, as shown in figure 1, and comprise two groups of row standby circuits and two groups of column standby circuits, and a repair circuit flow, if a failure unit circuit exists in a normal circuit, a group of rows or columns need to be allocated to repair the area.
In the prior art, the failure unit circuit is divided into a row or column specific repair type failure unit circuit, and a sparse failure unit circuit area, and a repair standby circuit allocation scheme for the row or column specific repair type failure unit area is generally a fixed solution due to the standby circuit design. The sparse failure unit circuit can be repaired by using a row standby circuit or a column standby circuit, so that the repairing scheme is flexible and changeable. The sparse failure unit circuit has certain instability due to factors such as a process procedure and the like. As shown in fig. 2, the chip after the repair process has new failure units in the subsequent test process, and has certain regularity for the distribution situation of the sparse failure units, for example, the failure units in the yellow area in the following figure, which appear later, are near the repaired area, are all obtained by testing functional related test items, and have been repaired by column type standby circuits, and for this situation, row type standby circuits are used for repairing most appropriately.
For the solutions of the unstable sparse failure unit circuit in the above description, there are generally solutions of increasing the number of test items, test flow, upper limit value of test conditions, etc., but these solutions have problems of increasing the cost of the whole test time and the cost of test economy.
Disclosure of Invention
The invention aims to provide a personalized repair method for a memory chip based on test equipment, which solves the technical problems.
The aim of the invention can be achieved by the following technical scheme:
The personalized memory chip repairing method based on the test equipment comprises the following steps:
And (3) failure unit extraction:
Acquiring failure unit circuit sets F CP and F FT of each memory chip in a CP front-stage testing stage and a FT back-stage testing stage respectively;
Respectively constructing adjacent matrixes corresponding to failure unit circuit sets F CP and F FT AndCalculation ofDividing the matrix epsilon according to the structural characteristics of the memory chip to obtain a data feature set;
Performing cluster analysis on the data feature set by adopting a sparse matrix-based spectral clustering method, extracting a failure unit distribution derivatization rule, and constructing a derivatization rule base, wherein the derivatization rule base comprises a derivatization rule element matrix and a derivatization direction matrix;
Failure unit analysis:
calculating the pearson correlation analysis between failure unit distribution in a sliding window and a derivatization rule element matrix by adopting a window sliding method, and executing the derivatization analysis if the correlation reaches a preset threshold;
obtaining failure units of derivatization analysis according to the derivatization rule element matrix and the distribution of all failure units in the window, and adding the failure units into a sparse failure unit set;
And performing normal solution analysis on all the sparse failure unit sets, and judging whether the chip is good or not according to whether the redundant resources of the chip meet preset solution conditions.
As a further aspect of the invention, constructing the adjacency matrixAndThe specific steps of (a) are as follows:
obtaining maximum value MAX_X of X axis direction and maximum value MAX_Y of Y axis direction of each block of each memory chip, and creating MAX_X Two-dimensional matrix of MAX_YAndInitializing all values to 0;
Traversing the information of all failure units under different blocks of the chip, and updating the two-dimensional matrix And。
As a further scheme of the invention, the specific steps of dividing the matrix according to the structural characteristics of the memory chip are as follows:
for two-dimensional matrix 、And epsilon is segmented to obtain a plurality of submatrices, and a submatrix set is obtained、AndWherein l.ltoreq.L, L representing the total number of submatrices.
The invention further provides a further scheme of analyzing the correlation between the CP front-section test and the FT back-section test data, and eliminating the failure unit distribution without the correlation, which comprises the following specific steps:
Acquiring a set of sub-matrices 、AndTraversing according to the number of the submatrices;
Firstly, judging whether the values in the submatrix w l are all 0, if so, skipping the submatrix, and traversing to the next submatrix;
If the value in the submatrix w l is not 0, the corresponding submatrices v l and u l are obtained, and whether the submatrices v l and u l meet the following constraint conditions is judged:
;
r approaches 1;
Wherein a and b represent the values of each corresponding position in the two matrices respectively, 、Respectively representing the average value of two matrixes, wherein L represents the size of the matrix;
If the constraint condition is met, u l is taken as a sub-sample to be added into the data feature set to be mined.
As a further scheme of the invention, the specific steps of clustering analysis of the data set by adopting a sparse matrix-based spectral clustering method are as follows:
Inputting a data feature set C, and mapping the data feature set C to be segmented into a weighted undirected graph G (V, E);
Calculating a similarity matrix S, a weight matrix W and a diagonal matrix D among different data feature sets;
Constructing a symmetric normalized laplacian matrix L, wherein l=d-W;
Performing feature decomposition on the Laplace matrix, solving a feature value and a feature vector, performing feature decomposition, and taking the first k feature vectors;
and after the feature vectors are standardized, clustering by using K-means to obtain a result.
As a further scheme of the invention, the calculation method of the similarity matrix S, the weight matrix W and the diagonal matrix D is as follows:
;
;
;
wherein w ij∈S;ci、cj ε C; And W ij epsilon W, wherein n represents the total number of samples in the data characteristic set C.
The method has the advantages that firstly, the difference between two data sets is compared through the sparse failure unit circuit data and FT (rear-stage) sparse failure unit circuit data of a CP front-stage test, the failure unit circuit distribution feature set is extracted through data preprocessing, the feature data set is mined through a clustering method, the feature set with a similar rule is classified into one type, the derivatization rule of an unstable sparse failure unit is extracted through a induction method and is added into a sparse failure unit derivatization rule base, before the sparse failure unit circuit analysis is carried out, sparse failure units of the derivatization rule base are processed, the failure unit circuit obtained through derivatization is added into the sparse failure unit set detected by the existing test equipment, and then normal restoration scheme distribution is carried out. The invention has low cost and high speed, does not need to increase test items and test flows, can solve the problem of unstable sparse units to a certain extent, and increases the yield of the memory chip.
The invention has important application in the memory chip repairing process, especially under the condition of unstable result of sparse failure unit circuit in test, the quality of the repaired memory chip can be effectively improved without increasing other cost. The sparse failure unit derivatization rule extraction method is combined with the characteristics of a storage chip and a spectral clustering general method, compared with a feature extraction algorithm through deep learning, category characteristics are not required to be set, key features can be extracted explicitly, rule base establishment can be performed quickly, efficiently and interpretably, and a knowledge rule of the derivatization rule base, which is extracted through a chip data set, is introduced in the sparse failure unit restoration process. And guiding the test equipment to conduct derivatization analysis of the failure unit in the sparse analysis stage of the memory chip through the derivatization rule base, so that the unstable failure unit can be repaired in advance in an earlier stage. Furthermore, the quality of the chip at the later stage can be more stable, the yield can be improved, and the repair work of the sparse failure unit of the memory chip can be completed with high quality.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a circuit for allocating a set of rows or columns to repair failed cells;
FIG. 2 is a schematic diagram of repair of an unstable sparse failure cell circuit;
FIG. 3 is a schematic diagram of the distribution of primary failure units in the present invention;
FIG. 4 is a schematic representation of the distribution of a matrix of derivatized rule elements in the invention;
FIG. 5 is a schematic diagram of the distribution of the failure units after the derivatization operation in the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 2-5, the invention discloses a personalized repair method for a memory chip based on test equipment, which is mainly applied to chip tester equipment and mainly comprises two methods, namely 1) a diffraction rule extraction method based on failure unit distribution of different test stages of the memory chip, 2) a sparse failure unit analysis method based on the diffraction rule, and comprises the following specific steps:
And step1, in the CP front-stage test stage, the chip tester runs a test program so as to acquire the integral failure unit circuit information of each memory chip. A repair scheme is first assigned to a failed cell circuit for a particular region. At this point, the sparse failure cell circuit type has not yet been assigned a repair scheme. Storing the sparse failure unit information into a hash table data structure, wherein the sparse failure unit information is marked as F CP={f1,f2,...,fk},fk={xk,yk }, k is E (1, M), M represents the total number of sparse failure unit circuits tested by the CP front stage, and X k,yk represents the X address and the Y address of the failure unit circuits respectively;
Step 2, in the test stage of the FT back end, the same operation as that in the step 1 is executed, a failure unit circuit set of the FT back end test is obtained and is marked as F FT={f1,f2,...,fk},fk={xk,yk }, k epsilon (1, N), N represents the total number of sparse failure unit circuits of the FT back end test, and X k,yk represents an X address and a Y address of the failure unit circuits respectively;
Step 3, obtaining the failure unit circuit information of all the memory chips obtained in the step 1 and the step 2 to obtain a distribution diagram of the original failure unit, and constructing an adjacent matrix of the failure unit set corresponding to F CP,FFT through X and Y coordinate values of the failure unit circuit as shown in fig. 3 AndThe specific process is as follows:
obtaining maximum value MAX_X of X axis direction and maximum value MAX_Y of Y axis direction of each block of each memory chip, and creating MAX_X Two-dimensional matrix of MAX_YAndInitializing all values to 0;
Traversing the information of all failure units under different blocks of the chip to update the two-dimensional matrix M, if the X address of the failure unit A is X 1 and the Y address is Y 1, updating the two-dimensional matrix, updating the values of the positions represented by the nodes X 1 and Y 1 to 1, and finally obtaining the updated two-dimensional matrix And;
Step 4, obtaining the two-dimensional matrix obtained in the step 3AndTwo-dimensional matrix relevance analysis is needed, logic OR operation is firstly carried out to obtain a union epsilon between two data sets,;
Step 5, considering regular mining of failure unit distribution information of the whole block, wherein the matrix is too large in scale and complex in operation, and meanwhile, the matrix of each block is divided according to the following rule by combining the structural characteristics of the memory chip, and the size of the submatrix after cutting is 16 generally8 Or 1616, For two-dimensional matrix,And epsilon is segmented to obtain a submatrix set、AndWherein L is less than or equal to L, L represents the total number of the submatrices, and v l、wl and u l represent the submatrices at corresponding positions respectively;
the X address direction, the corresponding memory chip of this direction is word line, the maximum value of this address value of each block is 256 generally, cut 256 into 16 segments generally;
the Y address direction, the corresponding memory chip of this direction is the bit line, the maximum value of this address value of each block is 128 generally, cut 256 into 16 sections or 8 sections generally;
Specific examples are as follows:
;
Will 6 The 6 matrix M is split into 4 submatrices, and the following matrixes are obtained according to the splitting of the corresponding positions:
、、 And ;
Step 6, considering the derivatization characteristic of the failure unit circuit, analyzing the correlation between the CP front-stage test and the FT back-stage test data, and rejecting the failure unit distribution without correlation, wherein the specific steps are as follows:
acquiring a sub-matrix set in step 5 、And Traversing according to the number of the submatrices;
Firstly, judging w l, if the median value of the w l matrix is 0, indicating that no newly added failure unit exists in the area in the back-end test, and analyzing is not needed, so that the analysis of the submatrix is skipped;
If the median value of the w l matrix is not 0, corresponding v l submatrices and u l submatrices need to be analyzed, and if the two matrices have a derivatization relationship, the relevance of the two matrices is higher, and a statistical pearson correlation coefficient calculation formula is used:
;
Wherein a, b represent the corresponding values of each of matrix 1 and matrix 2, respectively, 、Respectively representing the average value of the matrix 1 and the matrix 2, and L represents the size of the matrix;
If the r value is closer to 1, the correlation of the two matrixes is high, and if the correlation of the data set exists, and the correlation relation exists between v l and u l, the sub-matrix u l is taken as a sub-sample to be added into the data feature set C to be mined.
Step 7, analyzing the data set C, wherein the matrix formed by the sparse failure unit information has certain sparsity, so that the internal characteristic information is better mined out, and the invention provides a sparse matrix-based spectral clustering method, which comprises the following specific steps:
inputting a data feature set C, and mapping the data set C to be segmented into a weighted undirected graph G (V, E);
calculating a similarity matrix S, a weight matrix W and a diagonal matrix D between feature sets;
The calculation formula is as follows: ,、 a set of formulas representing a Euclidean distance between two data;
;
;
wherein s ij∈S;ci、cj ε C; W ij epsilon W, n representing the total number of samples in the data feature set C;
Constructing a symmetric normalized laplacian matrix L, wherein l=d-W;
Performing feature decomposition on the Laplace matrix, solving a feature value and a feature vector, performing feature decomposition, and taking the first k feature vectors;
and after the feature vectors are standardized, clustering by using K-means to obtain a result.
Step 8, obtaining a data set after cluster analysis, wherein failure unit distribution with rules and similar characteristics is classified into one type, and failure unit distribution in the same group is extracted through a induction method, and a derivatization rule base is constructed by extracting failure unit distribution derivatization rules, wherein the derivatization rule base consists of a plurality of rules, and a complete derivatization rule comprises a derivatization rule element matrix and a derivatization direction matrix, wherein fig. 4 shows a distribution schematic diagram of the derivatization rule element matrix;
2) The sparse failure unit analysis method based on the derivatization rule comprises the following steps:
Step 1, constructing a sparse failure unit derivatization rule base through the existing data by the method, wherein the derivatization analysis step is in a sparse analysis stage of CP front-stage test repair analysis;
Step 2, in the sparse failure unit derivatization repair analysis, a window sliding method is adopted, and a standard window (generally 256 256 Sliding analysis is carried out on the failure unit distribution, the pearson correlation analysis between the failure unit distribution in the sliding window and the derivatization rule element matrix is calculated, and if the correlation is high, the derivatization analysis is carried out;
Step 3, if the result is met, performing logic OR operation on the element matrix and all failure distribution of the window to obtain a failure unit for derivatization analysis, wherein the failure unit is added into a sparse failure unit set to be analyzed as shown in fig. 5;
Step 4, performing normal solution analysis on all sparse failure unit sets, and if the redundant resources of the chip meet the solution conditions, judging the chip as a good product and eliminating the chip in an irregular manner;
the invention has important application in the memory chip repairing process, especially under the condition of unstable result of sparse failure unit circuit in test, the quality of the repaired memory chip can be effectively improved without increasing other cost. The sparse failure unit derivatization rule extraction method is combined with the characteristics of a storage chip and a spectral clustering general method, compared with a feature extraction algorithm through deep learning, category characteristics are not required to be set, key features can be extracted explicitly, rule base establishment can be performed quickly, efficiently and interpretably, and a knowledge rule of the derivatization rule base, which is extracted through a chip data set, is introduced in the sparse failure unit restoration process. And guiding the test equipment to conduct derivatization analysis of the failure unit in the sparse analysis stage of the memory chip through the derivatization rule base, so that the unstable failure unit can be repaired in advance in an earlier stage. Furthermore, the quality of the chip at the later stage can be more stable, the yield can be improved, and the repair work of the sparse failure unit of the memory chip can be completed with high quality.
The foregoing describes one embodiment of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by the present invention.
Claims (6)
1. The personalized memory chip repairing method based on the test equipment is characterized by comprising the following steps of:
And (3) failure unit extraction:
Acquiring failure unit circuit sets F CP and F FT of each memory chip in a CP front-stage testing stage and a FT back-stage testing stage respectively;
Respectively constructing adjacent matrixes corresponding to failure unit circuit sets F CP and F FT AndCalculation ofDividing the matrix epsilon according to the structural characteristics of the memory chip to obtain a data feature set;
Performing cluster analysis on the data feature set by adopting a sparse matrix-based spectral clustering method, extracting a failure unit distribution derivatization rule, and constructing a derivatization rule base, wherein the derivatization rule base comprises a derivatization rule element matrix and a derivatization direction matrix;
Failure unit analysis:
calculating the pearson correlation analysis between failure unit distribution in a sliding window and a derivatization rule element matrix by adopting a window sliding method, and executing the derivatization analysis if the correlation reaches a preset threshold;
obtaining failure units of derivatization analysis according to the derivatization rule element matrix and the distribution of all failure units in the window, and adding the failure units into a sparse failure unit set;
And performing normal solution analysis on all the sparse failure unit sets, and judging whether the chip is good or not according to whether the redundant resources of the chip meet preset solution conditions.
2. The method for individually repairing a memory chip based on a test device according to claim 1, wherein the adjacency matrix is constructedAndThe specific steps of (a) are as follows:
obtaining maximum value MAX_X of X axis direction and maximum value MAX_Y of Y axis direction of each block of each memory chip, and creating MAX_X Two-dimensional matrix of MAX_YAndInitializing all values to 0;
Traversing the information of all failure units under different blocks of the chip, and updating the two-dimensional matrix And。
3. The method for individually repairing the memory chip based on the test equipment according to claim 1, wherein the specific steps of dividing the matrix according to the structural characteristics of the memory chip are as follows:
for two-dimensional matrix 、And epsilon is segmented to obtain a plurality of submatrices, and a submatrix set is obtained 、AndWhere l.ltoreq.L, L represents the total number of submatrices, v l、wl and u l represent the submatrices at the corresponding positions, respectively.
4. The method for individually repairing a memory chip based on a test device according to claim 3, further comprising the steps of analyzing the correlation between the CP front test and the FT back test data, and rejecting the failure unit distribution without correlation, wherein the specific steps are as follows:
Acquiring a set of sub-matrices 、AndTraversing according to the number of the submatrices;
Firstly, judging whether the values in the submatrix w l are all 0, if so, skipping the submatrix, and traversing to the next submatrix;
If the value in the submatrix w l is not 0, the corresponding submatrices v l and u l are obtained, and whether the submatrices v l and u l meet the following constraint conditions is judged:
;
r approaches 1;
Wherein a and b represent the values of each corresponding position in the two matrices respectively, 、Respectively representing the average value of two matrixes, wherein L represents the size of the matrix;
If the constraint condition is met, u l is taken as a sub-sample to be added into the data feature set to be mined.
5. The personalized repair method for memory chips based on test equipment according to claim 1, wherein the specific steps of performing cluster analysis on the data set by adopting a sparse matrix-based spectral clustering method are as follows:
Inputting a data feature set C, and mapping the data feature set C to be segmented into a weighted undirected graph G (V, E);
Calculating a similarity matrix S, a weight matrix W and a diagonal matrix D among different data feature sets;
Constructing a symmetric normalized laplacian matrix L, wherein l=d-W;
performing feature decomposition on the Laplace matrix worker, solving feature values and feature vectors, performing feature decomposition, and taking the first k feature vectors;
and after the feature vectors are standardized, clustering by using K-means to obtain a result.
6. The personalized repair method for memory chips based on test equipment according to claim 5, wherein the calculation methods of the similarity matrix S, the weight matrix W and the diagonal matrix D are as follows:
;
;
;
wherein s ij∈S;ci、cj ε C; And W ij epsilon W, wherein n represents the total number of samples in the data characteristic set C.
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