CN119812014A - A method and structure for packaging a chip using vertical bonding and FC - Google Patents
A method and structure for packaging a chip using vertical bonding and FC Download PDFInfo
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- CN119812014A CN119812014A CN202510026237.5A CN202510026237A CN119812014A CN 119812014 A CN119812014 A CN 119812014A CN 202510026237 A CN202510026237 A CN 202510026237A CN 119812014 A CN119812014 A CN 119812014A
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Abstract
本发明公开了一种利用垂直打线和FC芯片封装方法及结构，属于芯片封装技术领域，去除了转接板冗余设计，可以减小产品的package的厚度尺寸，满足轻薄化的需求，同时因产品的尺寸改变，还可以降低封装的成本；另外因为使用FC芯片代替转接板，使产品在原来的基础上多增加了一颗芯片的性能，从而达到提升整个产品的性能目的。
The present invention discloses a method and structure for packaging a chip using vertical bonding and FC, belonging to the technical field of chip packaging. The redundant design of an adapter plate is removed, the thickness of the product package can be reduced, and the demand for thinness and lightness can be met. At the same time, the packaging cost can be reduced due to the change in product size. In addition, because the FC chip is used instead of the adapter plate, the performance of an additional chip is increased on the original basis of the product, thereby achieving the purpose of improving the performance of the entire product.
Description
Technical Field
The invention belongs to the technical field of chip packaging, and particularly relates to a packaging method and structure for a chip by utilizing vertical wire bonding and FC (fiber channel).
Background
Currently, POP (Package on Package ) products mainly rely on conventional WB (wire bond) routing and interposer (substrate) to realize packaging. In this process, the WB chip and the interposer are precisely attached to the substrate, and bonding connection is established between the chip and the substrate, and between the interposer and the substrate by bonding wires. The adapter plate plays a role of a transfer medium, and is mainly responsible for transmitting signals of one IC to the other IC, so that effective combination of the two ICs is realized.
However, when the interposer only functions as a relay medium, problems such as attenuation, electromagnetic interference, and insufficient heat dissipation performance during signal transmission may be encountered, which may affect the overall performance and reliability of the POP package.
Disclosure of Invention
The invention provides a packaging method and structure utilizing vertical routing and FC chips, which solves the problems that the attenuation, electromagnetic interference and insufficient heat dissipation performance in the signal transmission process are caused by the fact that an adapter plate adopted by the existing POP product is only used as a transfer medium for communication.
In order to achieve the above purpose, the present invention provides the following technical solutions:
a method of packaging with vertical routing and FC chips, comprising:
Arranging a substrate carrier comprising a top substrate and a bottom substrate;
arranging a chip layer and an FC chip on a bottom substrate;
Connecting the chip layer and the FC chip with the top substrate by utilizing vertical routing to realize a passage, so as to form a preliminary product;
And packaging the preliminary product, and removing the bottom substrate after packaging.
Preferably, the base substrate is a glass fiber board.
Preferably, the chip layer is connected with the top substrate through a FOW chip adhesive film.
Preferably, the upper surface of the top substrate is provided with solder balls.
Preferably, each layer of chips of the chip layer is connected to the top substrate through vertical routing.
Preferably, the FC chip is adhered to the bottom substrate by chip glue.
Preferably, a bump is provided on a side of the FC chip close to the base substrate.
Preferably, a plastic package filler is filled between the top substrate and the bottom substrate.
Preferably, the chips on the chip layer are connected through a chip adhesive film.
A packaging structure utilizing vertical wire bonding and FC chips is obtained based on a packaging method utilizing vertical wire bonding and FC chips.
Compared with the prior art, the packaging method has the advantages that the redundant design of the adapter plate is eliminated by using the vertical routing and FC chip packaging method, the thickness size of the package of the product can be reduced, the demand of light and thin is met, meanwhile, the packaging cost can be reduced due to the size change of the product, and in addition, the FC chip is used for replacing the adapter plate, so that the performance of one chip is increased on the basis of the original product, and the purpose of improving the performance of the whole product is achieved.
Drawings
FIG. 1 is a flow chart of a method of packaging using vertical routing and FC chips according to the present invention;
FIG. 2 is a front view of a package structure utilizing vertical routing and FC chips according to the present invention;
FIG. 3 is a front view of the present invention with the underlying substrate removed using vertical routing and FC chip packaging structures;
FIG. 4 is a top view of a package structure utilizing vertical routing and FC chips according to the present invention;
fig. 5 is a front view and external connection combination diagram of a package structure using vertical routing and FC chips according to the present invention.
In the figure, 1-tin ball, 2-top substrate, 3-FOW chip adhesive film, 4-chip, 5-chip adhesive film, 6-bottom substrate, 7-chip adhesive, bulb of 8-FC chip, 9-FC chip, 10-bonding wire, 11-plastic package material filling, 12-another IC
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the embodiments of the present invention, it should be noted that, if the terms "upper," "lower," "horizontal," "inner," and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and does not indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
Furthermore, the term "horizontal" if present does not mean that the component is required to be absolutely horizontal, but may be slightly inclined. As "horizontal" merely means that its direction is more horizontal than "vertical", and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.
In the description of the embodiments of the present invention, it should also be noted that, unless explicitly stated or limited otherwise, the terms "disposed," "mounted," "connected," and "connected" should be interpreted broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected through an intermediate medium, or communicating between two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In order to make the technical scheme of the present invention better understood by those skilled in the art, the present invention will be further described in detail with reference to the accompanying drawings.
As shown in fig. 3, the present invention provides a packaging method using vertical routing and FC chip, comprising:
s101, arranging a substrate carrier, comprising a top substrate 2 and a bottom substrate 6;
S102, arranging a chip layer and an FC chip 9 on a bottom substrate;
S103, connecting the chip layer and the FC chip 9 with the top substrate 2 by utilizing vertical routing to realize a passage, so as to form a preliminary product;
and S104, packaging the preliminary product, and removing the bottom substrate 6 after packaging.
Wherein the base substrate 6 is a glass fiber board.
The glass fiber board has high strength, good insulating property and thermal stability, can effectively support the packaging structure, and improves the reliability and stability of packaging. Meanwhile, the plastic has better processability, and is convenient to manufacture and process into the required shape and size.
The chip layer is connected with the top substrate through the FOW chip adhesive film.
The Film Over Wire (FOW) die adhesive Film can provide excellent electrical properties and mechanical strength, while having good thermal and chemical stability. The connection mode is helpful for ensuring firm connection between the chip layer and the top substrate and improving the overall reliability of the package.
The upper surface of the top substrate 2 is provided with solder balls 1.
The solder ball 1 is used as an external connection point, and can be conveniently connected with other electronic components or circuit boards. The connection mode has the characteristics of high density, low resistance and low inductance, and is beneficial to improving the electrical performance and the signal transmission speed of the package.
Each layer of chips of the chip layer is connected with the top substrate 2 through vertical routing.
The vertical wire bonding technology can realize high-density and high-reliability connection between the chip layer and the top substrate. The connection mode can remarkably reduce the packaging volume and improve the integration level and the performance of packaging.
The FC chip 9 is adhered to the base substrate 6 by the chip glue 7.
The chip glue 7 can provide a firm bonding effect, ensuring the stability and reliability of the FC chip 9 during packaging. At the same time, it also provides a certain cushioning and damping effect, helping to protect the FC chip 9 from mechanical damage.
The FC chip 9 is provided with a bump on a side close to the bottom substrate 6, so that a signal transmission path can be optimized, signal attenuation and reflection can be reduced, and electrical performance of the package can be improved.
And a plastic package filler 11 is filled between the top substrate 2 and the bottom substrate 6.
The plastic package material filler 11 can provide additional mechanical support and protection, and the overall structural strength of the package is enhanced. Meanwhile, the method can also prevent the erosion and damage of external factors such as moisture, dust and the like to the internal circuit of the package, and improve the reliability and stability of the package.
The chips on the chip layer are connected through a chip adhesive film 5.
The chip adhesive film 5 can provide stable connection effect, and ensure electrical connection and signal transmission between chips on a chip layer. Meanwhile, the chip can also provide certain buffering and damping effects, and is helpful for protecting the chip from mechanical damage. In addition, the connection mode can simplify the packaging process and reduce the manufacturing cost.
The invention also provides a packaging structure utilizing the vertical wire bonding and the FC chip, which is obtained based on the packaging method utilizing the vertical wire bonding and the FC chip.
Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above-described specific embodiments and application fields, which are merely illustrative, instructive, and not restrictive. Those skilled in the art, having the benefit of this disclosure, may make many forms without departing from the scope of the invention as claimed.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510026237.5A CN119812014A (en) | 2025-01-08 | 2025-01-08 | A method and structure for packaging a chip using vertical bonding and FC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510026237.5A CN119812014A (en) | 2025-01-08 | 2025-01-08 | A method and structure for packaging a chip using vertical bonding and FC |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN119812014A true CN119812014A (en) | 2025-04-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202510026237.5A Pending CN119812014A (en) | 2025-01-08 | 2025-01-08 | A method and structure for packaging a chip using vertical bonding and FC |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10276545B1 (en) * | 2018-03-27 | 2019-04-30 | Powertech Technology Inc. | Semiconductor package and manufacturing method thereof |
| CN110970414A (en) * | 2019-12-06 | 2020-04-07 | 华天科技（西安）有限公司 | A kind of multi-chip packaging structure and manufacturing method |
| CN115810588A (en) * | 2021-09-14 | 2023-03-17 | 铠侠股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN118782602A (en) * | 2023-03-30 | 2024-10-15 | 长鑫存储技术有限公司 | Chip stacking packaging structure and chip stacking packaging method |
-
2025
- 2025-01-08 CN CN202510026237.5A patent/CN119812014A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10276545B1 (en) * | 2018-03-27 | 2019-04-30 | Powertech Technology Inc. | Semiconductor package and manufacturing method thereof |
| CN110970414A (en) * | 2019-12-06 | 2020-04-07 | 华天科技（西安）有限公司 | A kind of multi-chip packaging structure and manufacturing method |
| CN115810588A (en) * | 2021-09-14 | 2023-03-17 | 铠侠股份有限公司 | Semiconductor device with a plurality of semiconductor chips |
| CN118782602A (en) * | 2023-03-30 | 2024-10-15 | 长鑫存储技术有限公司 | Chip stacking packaging structure and chip stacking packaging method |
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