CN119811456A - Shift register data transmission method and device based on multiplexer - Google Patents

Abstract

The invention relates to a shift register data transmission method and device based on a multiplexer, which acquire RGB data through an external interface and perform initialization configuration on a shift register. After initialization, RGB data is gradually transferred to corresponding MUX channels in a shift register, each MUX channel corresponds to a latch circuit respectively, and data transmission is carried out by taking MUX as a unit. In the data transmission process, the data of each MUX channel is latched, the data output by the latch circuit is corrected and adjusted through the source buffer, and finally the corrected data is output to the target display screen. In this way, the invention not only optimizes the data transmission and latching process, but also reduces the number of latching circuits, thereby effectively reducing the chip area and the production cost.

Description

Multiplexer-based shift register data transmission method and device

Technical Field

The present invention relates to the field of data processing technologies, and in particular, to a shift register data transmission method and apparatus based on a multiplexer.

Background

In conventional LCD LTPS (low temperature polysilicon) display driving, the multiplexer structure transmits signals to the individual channels on the glass. Data is transferred and latched by a shift register in units of each line. Specifically, RGB data is output to the display image through the source buffer via the shift register. The time units of each line in this process are used to latch the data. This approach, while simple, has significant problems:

1. a large number of latch circuits, one for each line, are required to store data. The number of lines increases if the resolution of the LCD is higher, thereby requiring more latch circuits. The addition of the latch circuit not only occupies the area of the chip but also causes an increase in production cost.

2. Size and cost problems in that a large number of latch circuits need to be arranged on a chip in order to store a large amount of data, which occupies a large area of the chip and increases manufacturing cost. For example, assuming a 24-channel number of multiplexers, a conventional data latching method requires 72 latches.

In summary, for conventional LCD LTPS display driving, data is transferred and latched in units of each line, resulting in a large number of latch circuits required at high resolution, thereby increasing chip area and production cost, and no solution is currently available.

Disclosure of Invention

The invention mainly aims to provide a shift register data transmission method and device based on a multiplexer, which are used for solving the technical problems that the chip area and the production cost are increased because a large amount of latch circuits are needed under high resolution due to the fact that data are transmitted and latched by each line as a unit in the traditional LCD LTPS display drive.

The invention provides a shift register data transmission method based on a multiplexer, which comprises the following steps of obtaining RGB data through an external interface and initializing the shift register, gradually transmitting the RGB data to corresponding MUX channels in the shift register after the shift register is initialized, carrying out data transmission by taking MUX as a unit, carrying out latch processing on the data transmitted to each MUX channel, wherein each MUX channel corresponds to one latch circuit, adopting a source buffer to correct and adjust the data output by each latch circuit, and outputting the corrected and adjusted data to a target display screen.

The invention also provides a shift register data transmission device based on the multiplexer, which comprises an initialization processing unit, a transmission unit, a latch unit and an output unit, wherein the initialization processing unit is used for acquiring RGB data through an external interface and initializing the shift register, the transmission unit is used for gradually transmitting the RGB data to corresponding MUX channels in the shift register after the shift register completes initialization configuration and transmitting the RGB data in units of MUX, the latch unit is used for latching the data transmitted to each MUX channel, each MUX channel corresponds to one latch circuit, and the output unit is used for correcting and adjusting the data output by each latch circuit by adopting a source buffer and outputting the corrected and adjusted data to a target display screen.

The invention also provides a computer device comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of any of the methods described above when the computer program is executed.

The invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the method of any of the preceding claims.

The invention provides a shift register data transmission method and device based on a multiplexer, which acquire RGB data through an external interface and perform initialization configuration on a shift register. After initialization, RGB data is gradually transferred to corresponding MUX channels in a shift register, each MUX channel corresponds to a latch circuit respectively, and data transmission is carried out by taking MUX as a unit. In the data transmission process, the data of each MUX channel is latched, the data output by the latch circuit is corrected and adjusted through the source buffer, and finally the corrected data is output to the target display screen. In this way, the invention not only optimizes the data transmission and latching process, but also reduces the number of latching circuits, thereby effectively reducing the chip area and the production cost.

In a word, the invention simplifies the design of the data transmission and latch circuit in the high-resolution display drive by introducing the multiplexer, effectively solves the problems of the chip area and the cost in the traditional method, and has obvious technical advantages and practical application value.

Drawings

FIG. 1 is a schematic diagram showing steps of a shift register data transmission method based on a multiplexer according to an embodiment of the present invention;

fig. 2 is a schematic diagram of a conventional STP transmission direction according to an embodiment of the present invention;

fig. 3 is a schematic diagram illustrating a first STP transmission direction based on a multiplexer according to an embodiment of the present invention;

Fig. 4 is a schematic diagram of a second STP transmission direction based on a multiplexer according to an embodiment of the present invention;

FIG. 5 is a block diagram showing a shift register data transmission apparatus based on a multiplexer according to an embodiment of the present invention;

fig. 6 is a block diagram schematically illustrating a structure of a computer device according to an embodiment of the present invention.

The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

Referring to fig. 1, an embodiment of the present invention provides a shift register data transmission method based on a multiplexer, including the following steps:

S1, acquiring RGB data through an external interface, and initializing a shift register;

s2, after the shift register completes initialization configuration, the RGB data are gradually transferred to a corresponding MUX channel in the shift register, and data transmission is carried out by taking MUX as a unit;

S3, latching the data transmitted to each MUX channel, wherein each MUX channel corresponds to one latch circuit;

and S4, correcting and adjusting the data output by each latch circuit by adopting a source buffer, and outputting the corrected and adjusted data to a target display screen.

In conventional LCD LTPS display driving, data transfer and latching are typically performed in units of each line, which requires one latch circuit for each line. As the resolution of LCDs increases, the number of lines increases, resulting in the need for more latch circuits, which not only occupies the area of the chip, but also significantly increases the production cost. In order to solve the problem, the present invention proposes a shift register data transmission method based on a Multiplexer (MUX) to reduce the chip area and the cost by reducing the number of latch circuits.

In the technical scheme, firstly, RGB data is acquired through an external interface, and the shift register is initialized. After initialization, the RGB data is transferred stepwise to corresponding MUX channels in the shift register, each MUX channel being a unit of data transfer. This design changes the traditional line-by-line data transfer scheme, but transfers in MUX units, so that only one latch circuit is needed per MUX channel to store the transferred data. In this way, the efficiency of data transfer and latching is significantly improved, especially at high resolution, reducing the number of latching circuits and thus the chip area.

Further, after data is transferred to each MUX channel, the data is latched by the corresponding latch circuit. At this time, the data of each MUX channel is precisely controlled in time, and is effectively stored by the latch circuit, so that a foundation is laid for subsequent data processing. Then, the data output by the latch circuits are corrected and adjusted through the source buffer, so that the accuracy and consistency of the data when being transmitted to the target display screen are ensured. The correction and adjustment of this process further optimizes the display effect so that the quality of the final output image is improved.

The key of this scheme is that data transfer and latching is performed in MUX units. Compared with the traditional method, the number of latches is reduced by 3 times, and the occupied area is reduced to one third of the original area. This not only reduces the manufacturing cost of the chip, but also frees up chip area for other functional circuit arrangements, such as strengthening the routing of power lines or integrating additional ESD circuitry to improve the overall performance of the chip. Through the improvement, the invention effectively solves the problem of overlarge occupied area of the latch circuit under high resolution, reduces the chip area and the cost, and improves the efficiency and the image quality of display driving.

In one example, initializing the shift register includes determining a resolution of a target display screen, determining a number of pixels per row and per column on the target display screen based on the resolution, determining a number of MUX channels based on the number of pixels per row and per column on the target display screen, repartitioning a storage unit of the shift register into areas of the number of MUX channels based on the number of MUX channels, and sequentially allocating the divided areas to the plurality of MUX channels such that each MUX channel has an independent storage area.

In this example, the shift register is initialized mainly to accommodate the resolution requirement of the target display screen, and the number of suitable MUX channels is determined according to the resolution, so that the data transmission and storage efficiency are optimized. This initialization process can be divided into the following key steps:

First, the system will determine the resolution of the target display screen, i.e., the number of pixels per row and column on the screen. Resolution is an important parameter affecting data transmission and display quality, so at initialization this information must first be clarified. For example, assuming a screen resolution of 1920×1080, there are 1920 pixels per row and 1080 pixels per column.

Next, based on the determined number of pixels per row and column, it is calculated how many MUX channels are needed to transmit the data. The number of MUX channels is typically determined by the resolution of the screen and the size of the shift register. For example, if one MUX channel can handle a certain amount of pixel data, it is necessary to distribute the pixel data reasonably among different MUX channels to ensure efficient transmission and storage of the data.

The memory cells of the shift register are then repartitioned based on the determined number of MUX channels. The purpose of this step is to allocate an independent memory area for each MUX channel, ensuring that the data for each channel can be stored and transferred independently. Specifically, the memory cells of the shift register are divided into a plurality of regions, each region corresponding to one MUX channel. For example, if the calculated number of MUX channels is 24, the memory unit of the shift register is divided into 24 regions, and each region is allocated to one MUX channel for use.

Finally, the system will sequentially allocate the divided regions to different MUX channels, ensuring that each channel has independent memory space. The method has the advantages that interference among different channels in the data transmission process can be avoided, and the efficiency and accuracy of data transmission are improved. In addition, the storage area of each MUX channel can be fully utilized in this way, and the use efficiency of the chip is further optimized.

In summary, the core of this initialization process is to reasonably determine the number of MUX channels according to the resolution of the target display screen, and scientifically divide the memory units of the shift register to ensure that each MUX channel has an independent memory area. The method not only improves the efficiency of data transmission, but also reduces the complexity of the circuit, and is beneficial to reducing the manufacturing cost of the chip.

In one example, after determining the number of MUX channels according to the number of pixels per row and per column on the target display screen, the shift register data transmission method further includes assigning a set of pixels to each MUX channel according to the number of pixels per row and per column on the target display screen and the number of MUX channels, wherein the MUX channels are configured to process data content corresponding to the assigned set of pixels.

In this example, after determining the resolution of the target display screen and the corresponding number of MUX channels, it is further desirable to assign a specific set of pixels to each MUX channel to ensure that each channel is capable of efficiently processing and transmitting the assigned pixel data. This process can be understood as classifying and grouping pixel data on a screen and distributing the grouped data to different MUX channels for processing.

The method comprises the following specific steps:

First, the number of pixels to be processed per MUX channel is calculated according to the number of pixels per row and column on the target display screen and the determined number of MUX channels. For example, if the resolution of the display screen is 1920x1080 and it is determined that there are 24 MUX channels, each of which will be responsible for processing approximately 45 lines of pixel data (assuming 1920 pixels per line, each channel processes approximately 86400 pixels).

Next, pixel data of the entire screen is divided in rows and columns to form a plurality of pixel sets. Each set of pixels contains a certain number of pixels, which belong to different parts of the screen. For example, assume that a screen is divided into 24 regions, and pixels in each region constitute one pixel set. In this way, the pixel data of the screen is divided into 24 independent sets, with the number of pixels in each set being approximately equal, so as to be equally distributed to each MUX channel.

These pixel sets are then assigned to the respective MUX channels. Each MUX channel is responsible for processing a particular set of pixels, meaning that the channel will process the data content corresponding to those pixels. For example, MUX channel 1 may be responsible for processing a portion of the pixels in the upper left corner of the screen, MUX channel 2 is responsible for the pixels in the middle left corner of the screen, and so on, until all pixel sets have been allocated.

During actual operation, each MUX channel receives the data content corresponding to its assigned set of pixels, and then transmits, latches, and ultimately displays the data content on the screen. This allocation makes the data transfer process more efficient, while also avoiding data collisions between different channels. Since each MUX channel only needs to process the data of its assigned set of pixels, this greatly simplifies the management of data transfer and optimizes the performance of the display driver.

In summary, the core of this process is to group the pixel data of the display screen reasonably and assign the grouped pixel sets to different MUX channels. In this way, each MUX channel is able to efficiently process and transfer the pixel data content for which it is responsible, thereby enabling a fast, accurate image display.

In one example, after each MUX channel has an independent storage area, the shift register data transmission method further comprises the steps of recalculating the frequency of clock signals of the shift register according to the number of the MUX channels, matching a time unit for each MUX channel so that the shift register can transmit data based on the time unit, and carrying out reconfiguration processing on start pulses and reset signals of the shift register, wherein the reconfigured start pulses are used for triggering the shift register to reset, enabling the shift register and the MUX channels to synchronously enter an initial state, and meanwhile, the reconfigured reset signals are used for triggering state clearing of the shift register so as to prevent residual data of a previous data period from affecting current data transmission.

In this example, further optimization of the shift register data transfer method involves adjustment of the clock signal frequency and reconfiguration of the start pulse and reset signals. The purpose of these steps is to ensure that the shift register and MUX channel are able to perform data transfer efficiently and synchronously while preventing the residual data of the previous data cycle from affecting the data processing of the current cycle. The following is a detailed explanation of these steps:

First, after each MUX channel is allocated an independent memory region, the system needs to recalculate the clock signal frequency of the shift register according to the number of MUX channels. The frequency of the clock signal directly affects the speed and efficiency of the data transmission. In particular, the clock frequency must be matched to the number of MUX channels and the refresh requirements of the display screen to ensure that each MUX channel can complete data processing within a specified time. To this end, the system matches each MUX channel with an appropriate time unit that represents the basic time interval for the transmission and processing of data in the channel. By adjusting the frequency of the clock signal, the shift register is able to synchronously transfer data to the various MUX channels in the appropriate time units.

Next, the system reconfigures the start pulse and the reset signal of the shift register. The start pulse is an important signal for the start of the shift register, which determines the start of the data transfer. By reconfiguration, the start pulse not only acts to initiate data transfer but also triggers a reset operation of the shift register to synchronize the shift register and MUX channels into an initial state. In this way, each data transmission cycle starts from a consistent, clean starting point, avoiding timing confusion or non-synchronization problems.

At the same time, the reset signal is also reconfigured. The reconfiguration of the reset signal is to trigger a state clearing of the shift register at the end of each data transfer period. This step is important because if the data residue of the previous cycle is not cleared, it may cause data confusion or errors, affecting the current data transmission accuracy. By reconfiguring the reset signal, it is ensured that all states and data in the shift register are cleared before a new data cycle begins, thereby providing a clean operating environment for the new data transfer cycle.

In summary, the method in this example achieves efficient synchronization of shift registers with MUX channels by recalculating clock signal frequencies, matching time units for MUX channels, and reconfiguring start pulses and reset signals. The design not only improves the precision and efficiency of data transmission, but also effectively avoids the influence of residual data of the previous data period on the current period, and ensures the stability and quality of the display image.

In one example, transferring RGB data stepwise into corresponding MUX channels in a shift register and transferring the data in MUX units includes starting each MUX channel to perform a sequential reset process based on a start pulse and a reset signal each time the RGB data is received so that subsequent data starts from a uniform start point, and allocating pixel sets based on the respective MUX channels to transfer the RGB data into the respective MUX channels according to a push of a clock signal.

In this example, the transmission process of RGB data is performed stepwise through the MUX channels in the shift register, ensuring that each MUX channel starts data processing at a uniform start point, thereby improving the accuracy and efficiency of data transmission. The following is a detailed explanation of this process:

First, when the shift register receives RGB data, the system starts a reset process of each MUX channel based on a start pulse and a reset signal. The function of the start pulse and the reset signal is to ensure that all MUX channels are in the same initial state at the beginning of the data transfer. Specifically, the start pulse is used to trigger the start of the shift register, and the reset signal is responsible for clearing the state of all MUX channels so that the previous data no longer affects the current transfer. Through the process, all MUX channels receive and process data from a unified and clean starting point, and the problems of inconsistent time sequence or data confusion are avoided.

Next, after each time RGB data is received, the system gradually transfers the data into the respective MUX channels according to the progress of the clock signal. The clock signal plays a synchronous role here, ensuring that the data is transferred in order at predetermined time intervals. Since each MUX channel has allocated a specific set of pixels, RGB data is accurately transferred to the corresponding MUX channel according to the allocation of the sets of pixels. For example, MUX channel 1 may be responsible for processing a set of pixel data in the upper left corner of the screen, MUX channel 2 is responsible for pixel data in the middle left portion of the screen, and so on.

This process ensures that RGB data is transferred in order into each MUX channel in a predetermined order and time node, and that data received by each MUX channel can be processed from the same initial state. Thus, not only the accuracy and consistency of data transmission are ensured, but also the quality and efficiency of image display are improved. By transmitting data in MUX units, the system can better control the data flow direction and reduce image distortion or flickering phenomenon caused by time sequence problems or data conflicts.

In summary, in this example, the transfer of RGB data is achieved through precise timing control and channel reset mechanisms. Each time RGB data is received, the system starts the resetting process of the MUX channels, so that the data starts from a unified starting point, and then the data is transmitted to each MUX channel according to the advance of the clock signal. The method effectively improves the stability of data transmission and the quality of image display.

In one example, latching data transferred to each MUX channel includes transferring the data of each MUX channel to a latch of a first one of the corresponding latch circuits of the MUX channel, and sequentially transferring the data in each latch circuit according to a connection order of the plurality of latches in the latch circuit in accordance with the advancement of the clock signal.

In this example, the latching of data transferred to each MUX channel involves primarily transferring the data from the MUX channel to its corresponding latch circuit, where it is then passed and latched in steps to ensure proper storage and subsequent output of the data. The following is a detailed explanation of this process:

first, each MUX channel, upon receiving data, will transfer the data to the first latch in its corresponding latch circuit. A latch circuit is understood to mean a sequence of a plurality of latches, each latch being capable of temporarily storing a certain amount of data. The transfer of data to the first latch is similar to the preliminary storage of data, ensuring that the data for each MUX channel has a fixed storage location ready for further processing.

Next, the advancement of the clock signal plays a key role in this process. The clock signal controls the order of data transfer in the latch circuit by generating a series of sync pulses. With each advance of the clock signal, the data in the first latch will be sequentially transferred to the next latch in the order of connection in the latch circuit. This step-by-step transfer and latching of data ensures that each piece of data can be stored in a predetermined order without causing data loss or confusion due to timing issues.

For example, assume that a latch circuit corresponding to a certain MUX channel is composed of three latches. When the first latch receives data, a first advance of the clock signal triggers the first latch to transfer the data to the second latch. Then, with the second advance of the clock signal, the second latch passes the data to the third latch, and so on. Thus, data is transferred and stored in the latch circuit step by step in accordance with the rhythm of the clock signal.

This latching mechanism helps to ensure that data is stably stored in the correct location at different times, thus laying the foundation for subsequent data processing and display. By controlling the sequential transfer of data in the latch circuit, the system can avoid data collision or confusion, and ensure that image signals can be output to the display screen in time and sequence. The method is particularly suitable for high-resolution displays, and can effectively improve the performance and display effect of the system under the conditions of large data volume and high processing speed requirement.

To summarize, in this example, the core of the latch processing of data transferred to each MUX channel is that data is transferred and stored in an ordered manner in a plurality of latches using the cooperation of a latch circuit and a clock signal. The method not only ensures the integrity of data and the consistency of time sequence, but also provides a reliable basis for subsequent image display.

In one example, a source buffer is adopted to correct and adjust data output by each latch circuit and output the corrected and adjusted data to a target display screen, the method comprises the steps of adopting the source buffer to receive the data output by each latch circuit and perform stable processing and synchronous calibration processing on the data, wherein the stable processing at least comprises the steps of filtering out instantaneous interference and noise, adopting a color correction algorithm built in the source buffer and performing color difference adjustment on the data according to preset correction parameters so as to compensate color deviation caused by a manufacturing process, acquiring a temperature detection value of the target display screen and performing temperature compensation processing on the data subjected to the color difference adjustment based on the temperature detection value, performing non-linear mapping processing on the data subjected to the temperature compensation processing according to a gamma curve built in the source buffer, converting the data subjected to the gamma correction into corresponding analog voltage signals, performing enhancement processing on linearity of the analog voltage signals to obtain output signals corresponding to each pixel, and correspondingly sending the output signals to each pixel of the target display screen so that the target display screen displays images based on the received output signals.

In this example, the source buffers are employed to correct and adjust the data output from the respective latch circuits, primarily to ensure optimal image quality for final output to the target display screen. This process involves a series of steps including the reception of data, stabilization processing, color correction, temperature compensation, gamma correction, and output of the final signal. The following is a detailed explanation of this process:

First, the source buffer receives data from each latch circuit. These data may be affected by external interference or noise during transmission, and thus the source buffer may be stabilized first. The core task of the stabilization process is to filter out transient disturbances and noise. This can be achieved by applying a filtering algorithm during the data transmission process, thereby removing noise components that may cause image instability, and ensuring the purity of the data.

The source buffer then performs color difference adjustment on the data using a built-in color correction algorithm. Color deviations may occur in the display screen due to manufacturing process variations, such as certain colors appearing too intense or dull. By applying preset correction parameters, the source buffer can adjust the deviations according to actual conditions, so that the finally displayed colors are more accurate and natural. This step is critical because it directly affects the realism and consistency of the image colors seen by the user.

After the color correction is completed, the source buffer also performs a temperature compensation process on the data. The temperature of the display screen may have an effect on the color appearance, for example, high temperatures may cause color warmth and low temperatures may cause color coldness. To cope with this problem, the source buffer acquires temperature detection values of the target display screen, and performs further compensation processing on the data that has been subjected to the color difference adjustment based on these values. In this way, the display screen maintains color accuracy at whatever temperature.

Next, the source buffer performs a non-linear mapping process of gamma correction on the data. Gamma correction is a common image processing technique used to adjust the brightness and contrast of an image to better conform to the perceived characteristics of the human eye. By gamma correction, the brightness and darkness levels of the image are more clear, and the detail expression is more abundant. The source buffer carries out nonlinear mapping on the data through the built-in gamma curve, so that the brightness and the contrast ratio of the image are more natural and reasonable when the image is finally displayed.

Finally, the gamma corrected data is converted into corresponding analog voltage signals. These signals are the key to driving each pixel of the display screen. To ensure that each pixel accurately reflects the data, the source buffer enhances the linearity of the analog voltage signal. This step ensures a more linear relationship between the voltage signal and the pixel brightness, thereby avoiding problems of image distortion or non-uniformity of brightness.

The output signal after the series of processing is sent to each pixel of the target display screen. Each pixel performs picture presentation processing based on the received output signal, and finally forms a clear, accurate and color-rich image on the screen. The process not only ensures the stability and accuracy of the image quality, but also can adapt to different temperature environments and manufacturing process differences, and provides the best visual experience for users.

In general, the present application proposes a technical solution for transmitting data in units of multiplexers (muxes) for a source channel for 3D printing, aiming at optimizing the data transmission and latching process in an LCD 3D printer station. Specifically, in a MUX circuit of an LCD Low Temperature Polysilicon (LTPS) structure, signals are transferred to channels on glass through a source driver of a DDIC, RGB data are transferred through a shift register in time units of each line, and then latched into corresponding latches, and finally outputted to a display screen through a source buffer to generate an image.

However, in the conventional art, as shown in fig. 2, data transmission of the shift register is latched in line units, which requires a large number of latch circuits to store data. The higher the resolution of the LCD, the greater the number of latches required, which not only occupies a large area of the chip, but also adds significant cost. For example, in the multiplexer 3 (MUX 3) data latch scheme, assuming that the number of channels is 24, the start pulse (as_lt_stp) is reset once at each data transfer, the data transfers are sequentially arranged AS MUX1, MUX2, MUX3, and finally the data is sequentially transferred to each channel by the clock signal (as_lt_clk). Under conventional approaches, 72 latches are required to complete the data storage, which results in a significant occupation of chip area.

In view of the above drawbacks, the present application proposes an improved MUX-type shift register (STREG) architecture, as shown in fig. 3, that switches the unit of data transfer from line to MUX. Specifically, in the present scheme, when data is transferred in MUX units, the data is sequentially arranged AS MUX1, MUX2, and MUX3 by resetting using a start pulse (as_lt_stp), and the data is sequentially transferred to a channel by a clock signal (as_lt_clk) and finally outputted to a display screen by a source buffer. In this structure, 72 pieces of data still need to be transmitted, but because the transmission mode of MUX is adopted as a unit, the data storage can be completed by only 27 latches, and compared with the traditional method, the chip area is reduced to one third of the original area.

In order to achieve accurate data transmission and output, the application also provides a supplementary scheme, namely, as shown in fig. 4, when data is transmitted to output, the data is firstly transmitted to a first latch (latch 1) in sequence, then transmitted to a second latch (latch 2) according to specific address requirements, and finally output through a source buffer. Thus, the latch data of each MUX will actually become the MUX data of the next time point, and the design effectively reduces the use quantity of latches, thereby saving the chip area.

The key innovation point of the technical scheme is that 1, the time unit of data transmission is switched from a line to MUX, the conversion not only reduces the number of latches, but also effectively reduces the chip area, thereby reducing the production cost, and 2, under the condition of higher resolution and more MUX, the data transmission mode adopting MUX as the unit can remarkably save the area, and the free space is used for wiring of other circuits or enhanced power lines.

Compared with the prior art, the embodiment of the application has obvious technical progress in the aspects of the utilization rate of the chip area, the control of the production cost, the flexibility of the circuit design and the like. This not only brings higher efficiency and lower cost for 3D printing technology, but also provides new ideas and references for related art circuit designs.

As shown in fig. 5, the embodiment of the present invention further provides a shift register data transmission device based on a multiplexer, including:

An initialization processing unit 1, configured to acquire RGB data through an external interface, and perform initialization processing on a shift register;

A transmission unit 2, configured to gradually transmit RGB data to a corresponding MUX channel in the shift register after the shift register completes the initialization configuration, and perform data transmission in units of muxes;

a latch unit 3 for latching the data transferred to the respective MUX channels, wherein each MUX channel corresponds to a latch circuit;

and an output unit 4 for correcting and adjusting the data output by each latch circuit by using the source buffer and outputting the corrected and adjusted data to the target display screen.

In this embodiment, for specific implementation of each unit in the above device embodiment, please refer to the above method embodiment, and detailed description is omitted here.

Referring to fig. 6, a computer device is further provided in an embodiment of the present invention, where the computer device may be a server, and the internal structure of the computer device may be as shown in fig. 6. The computer device includes a processor, a memory, a display screen, an input device, a network interface, and a database connected by a system bus. Wherein the computer is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used for communicating with an external terminal through a network connection. Which computer program, when being executed by a processor, carries out the above-mentioned method.

It will be appreciated by those skilled in the art that the architecture shown in fig. 6 is merely a block diagram of a portion of the architecture in connection with the present inventive arrangements and is not intended to limit the computer devices to which the present inventive arrangements are applicable.

An embodiment of the present invention also provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the above method. It is understood that the computer readable storage medium in this embodiment may be a volatile readable storage medium or a nonvolatile readable storage medium.

Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium provided by the present invention and used in embodiments may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (SYNCHLINK) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, apparatus, article, or method. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, apparatus, article, or method that comprises the element.

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and drawings of the present invention or direct or indirect application in other related technical fields are included in the scope of the present invention.

Claims (8)

1. A shift register data transmission method based on a multiplexer, comprising the steps of:

RGB data is obtained through an external interface, and initialization processing is carried out on a shift register;

After the shift register completes initialization configuration, gradually transmitting the RGB data to a corresponding MUX channel in the shift register, and transmitting data by taking MUX as a unit;

latching data transmitted to each MUX channel, wherein each MUX channel corresponds to one latch circuit;

And correcting and adjusting the data output by each latch circuit by adopting a source buffer, and outputting the corrected and adjusted data to a target display screen.

2. The shift register data transmission method according to claim 1, wherein initializing the shift register comprises:

Determining a resolution of the target display screen, and determining a number of pixels per row and column on the target display screen based on the resolution;

Determining the number of MUX channels according to the number of pixels of each row and each column on the target display screen;

And based on the number of the MUX channels, re-dividing the storage unit of the shift register into areas with the number of the MUX channels, and sequentially distributing the divided areas to the MUX channels, so that each MUX channel has an independent storage area.

3. The shift register data transmission method according to claim 2, wherein after determining the number of MUX channels based on the number of pixels per row and column on the target display screen, the shift register data transmission method further comprises:

and distributing a pixel set for each MUX channel according to the pixel number of each row and each column on the target display screen and the MUX channel number, wherein the MUX channel is used for processing the data content corresponding to the distributed pixel set.

4. A shift register data transfer method as claimed in claim 3, wherein after each of the MUX channels has an independent memory area, the shift register data transfer method further comprises:

recalculating the frequency of the clock signal of the shift register according to the number of the MUX channels, and matching a time unit for each MUX channel so that the shift register performs data transmission based on the time units;

And carrying out reconfiguration processing on the start pulse and the reset signal of the shift register, wherein the reconfigured start pulse is used for triggering the shift register to reset so as to enable the shift register and the MUX channel to synchronously enter an initial state, and the reconfigured reset signal is used for triggering the state of the shift register to be emptied so as to prevent residual data in the last data period from affecting current data transmission.

5. The shift register data transmission method as claimed in claim 4, wherein the step of transferring the RGB data stepwise to the corresponding MUX channel in the shift register and performing data transmission in MUX units comprises:

Starting each MUX channel to perform a sequential reset process based on the start pulse and the reset signal each time the RGB data is received, so that the subsequent data starts from a unified start point, and

And distributing pixel sets based on the MUX channels according to the pushing of the clock signals, and transmitting the RGB data to the MUX channels.

6. The shift register data transmission method according to claim 5, wherein the latch processing of the data transferred to the respective MUX channels includes:

Transmitting the data of each MUX channel to a latch of a first latch circuit corresponding to the MUX channel;

And according to the pushing of the clock signals, sequentially transmitting and latching the data in each latch circuit according to the connection sequence of a plurality of latches in the latch circuit.

7. The shift register data transmission method according to claim 6, wherein correcting and adjusting the data output from each latch circuit by using a source buffer and outputting the corrected and adjusted data to a target display screen, comprises:

The method comprises the steps of adopting a source buffer to receive data output by each latch circuit, and carrying out stabilization processing and synchronous calibration processing on the data, wherein the stabilization processing at least comprises the steps of filtering out instantaneous interference and noise;

adopting a color correction algorithm built in a source buffer, and performing color difference adjustment on the data according to preset correction parameters so as to compensate color deviation caused by a manufacturing process;

acquiring a temperature detection value of a target display screen, and performing temperature compensation processing on the data subjected to the color difference adjustment processing based on the temperature detection value;

According to the gamma curve built in the source buffer, performing nonlinear mapping processing of gamma correction on the data subjected to temperature compensation processing;

Converting the gamma corrected data into corresponding analog voltage signals, and enhancing the linearity of the analog voltage signals to obtain output signals corresponding to each pixel;

and correspondingly transmitting the output signals to each pixel of a target display screen so that the target display screen performs picture presentation processing based on the received output signals.

8. A multiplexer-based shift register data transmission apparatus, comprising:

The initialization processing unit is used for acquiring RGB data through an external interface and initializing the shift register;

The transmission unit is used for gradually transmitting the RGB data to a corresponding MUX channel in the shift register after the shift register completes initialization configuration, and transmitting data by taking MUX as a unit;

A latch unit for latching the data transferred to each MUX channel, wherein each MUX channel corresponds to one latch circuit;

And the output unit is used for correcting and adjusting the data output by each latch circuit by adopting the source buffer and outputting the corrected and adjusted data to the target display screen.