CN119811306A - Pixel circuit, display panel and display device - Google Patents
Pixel circuit, display panel and display device Download PDFInfo
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Abstract
本发明公开了一种像素电路、显示面板及显示装置，像素电路包括：驱动晶体管和至少一个开关晶体管；驱动晶体管包括第一有源层、设置于第一有源层的第一侧的第一栅极以及设置于第一有源层远离第一侧的第二栅极；至少一个开关晶体管包括第二有源层、设置于第二有源层的第一侧的第三栅极以及设置于第二有源层远离第一侧的第四栅极；其中，第一有源层与第二有源层同层设置；第一栅极作为驱动晶体管的控制端；第四栅极作为开关晶体管的控制端；第二栅极用于接收第一恒定电位；第三栅极用于接收第二恒定电位。本发明提供的技术方案，以在简化显示面板工艺的同时提升显示面板性能。
The present invention discloses a pixel circuit, a display panel and a display device, wherein the pixel circuit comprises: a driving transistor and at least one switching transistor; the driving transistor comprises a first active layer, a first gate arranged on a first side of the first active layer and a second gate arranged on the first active layer away from the first side; at least one switching transistor comprises a second active layer, a third gate arranged on a first side of the second active layer and a fourth gate arranged on the second active layer away from the first side; wherein the first active layer and the second active layer are arranged in the same layer; the first gate serves as a control terminal of the driving transistor; the fourth gate serves as a control terminal of the switching transistor; the second gate is used to receive a first constant potential; and the third gate is used to receive a second constant potential. The technical solution provided by the present invention can improve the performance of the display panel while simplifying the display panel process.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a pixel circuit, a display panel, and a display device.
Background
An Organic Light-Emitting Diode (OLED) refers to a phenomenon in which a Light-Emitting material emits Light by carrier injection and recombination under the driving of an electric field. Organic light emitting display devices are lighter and thinner than Liquid Crystal Display (LCD) devices, have better viewing angles and contrast ratios, and the like, and thus have received much attention.
The low temperature poly-oxide (Low Temperature Polycrystalline Oxide, LTPO) display panel is a combination of organic light emitting display OLED panel assembly low temperature poly-Silicon (LTPS) technology and indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) technology. However, the above combination makes the process flow of the display panel more complex, and has requirements for compatibility of the display panel, thereby increasing the manufacturing cost of the display panel.
Disclosure of Invention
The embodiment of the invention provides a pixel circuit, a display panel and a display device, which are used for improving the performance of the display panel while simplifying the process of the display panel.
In a first aspect, an embodiment of the present invention provides a pixel circuit including a driving transistor and at least one switching transistor;
The driving transistor comprises a first active layer, a first grid electrode arranged on a first side of the first active layer and a second grid electrode arranged on the first active layer far away from the first side;
At least one of the switching transistors includes a second active layer, a third gate electrode disposed on a first side of the second active layer, and a fourth gate electrode disposed on the second active layer away from the first side;
The first active layer and the second active layer are arranged on the same layer, the first grid electrode is used as a control end of the driving transistor, the fourth grid electrode is used as a control end of the switching transistor, the second grid electrode is used for receiving a first constant potential, and the third grid electrode is used for receiving a second constant potential.
In a second aspect, an embodiment of the present invention provides a pixel circuit including a driving transistor and at least one switching transistor;
The driving transistor comprises a first active layer, a first grid electrode arranged on a first side of the first active layer and a second grid electrode arranged on the first active layer far away from the first side;
At least one of the switching transistors includes a second active layer, a third gate electrode disposed on a first side of the second active layer, and a fourth gate electrode disposed on the second active layer away from the first side;
The first active layer and the second active layer are arranged in the same layer, the first grid electrode is used as a control end of the driving transistor, the second grid electrode is used for receiving a third constant potential, and the third grid electrode and the fourth grid electrode are used as control ends of the switching transistor.
In a third aspect, an embodiment of the present invention provides a pixel circuit including a driving transistor and at least one switching transistor;
The driving transistor comprises a first active layer, a first grid electrode arranged on a first side of the first active layer and a second grid electrode arranged on the first active layer far away from the first side;
At least one of the switching transistors includes a second active layer, a third gate electrode disposed on a first side of the second active layer, and a fourth gate electrode disposed on the second active layer away from the first side;
The first active layer and the second active layer are arranged on the same layer, the first grid electrode and the second grid electrode are used as control ends of the driving transistor, the fourth grid electrode is used as a control end of the switching transistor, and the third grid electrode is used for receiving a fourth constant potential.
In a fourth aspect, an embodiment of the present invention further provides a display panel, including the pixel circuit provided in any embodiment of the present invention.
In a fifth aspect, an embodiment of the present invention further provides a display apparatus, including a display panel provided by any embodiment of the present invention.
In the invention, the pixel circuit comprises a driving transistor and at least one switching transistor, wherein the driving transistor comprises a first active layer, a first grid electrode and a second grid electrode on two opposite sides of the first active layer, and the switching transistor comprises a second active layer, a third grid electrode and a fourth grid electrode on two opposite sides of the second active layer. The first active layer and the second active layer are arranged on the same layer, the first grid electrode and the third grid electrode are arranged on the same side, and the second grid electrode and the fourth grid electrode are arranged on the same side. In this embodiment, at least one of the first gate and the second gate may be used as a control terminal of the driving transistor, and at least one of the third gate and the fourth gate may be used as a control terminal of the switching transistor, where a control manner of the control terminal of the driving transistor and a control manner of the control terminal of the switching transistor are different to achieve different electrical properties, so that the switching transistor has a high mobility characteristic and a relatively strong stability. In this embodiment, only one active layer of full oxide is provided, so that stability of the driving transistor and high mobility of the switching transistor can be considered, and multiple active layers are not required to be provided to integrate LTPS technology and IGZO technology simultaneously to meet different electrical properties, so that the process flow of the display panel is simplified, the process cost is greatly reduced, and the circuit layout space can be increased. In addition, compared with LTPO technology, the embodiment is not easy to be influenced by water vapor and the like, reduces the technology difficulty and is convenient for realizing the mass production requirement of the display panel.
Drawings
Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a LTPO display panel according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
Fig. 4 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 6 is a layout diagram of the pixel circuit of FIG. 5;
FIG. 7 is a schematic cross-sectional view of the pixel circuit of FIG. 5 along the line a-a';
fig. 8 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
Fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
Fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
The embodiment of the invention provides a pixel circuit, as shown in fig. 1, and fig. 1 is a schematic structural diagram of the pixel circuit. Comprises a driving transistor T1 and at least one switching transistor T2;
The driving transistor T1 includes a first active layer 11, a first gate electrode 12 disposed on a first side of the first active layer 11, and a second gate electrode 13 disposed on a second side of the first active layer 11;
The at least one switching transistor T2 includes a second active layer 14, a third gate electrode 15 disposed on a first side of the second active layer 14, and a fourth gate electrode 16 disposed on a second active layer 14 away from the first side;
The first active layer 11 and the second active layer 14 are arranged in the same layer, the first gate 12 is used as a control terminal of the driving transistor T1, the fourth gate 16 is used as a control terminal of the switching transistor T2, the second gate 13 is used for receiving the first constant potential V1, and the third gate 15 is used for receiving the second constant potential V2.
In the embodiment of the invention, the pixel circuit comprises a driving transistor and at least one switching transistor, wherein the driving transistor comprises a first active layer, a first grid electrode and a second grid electrode on two opposite sides of the first active layer, and the switching transistor comprises a second active layer, a third grid electrode and a fourth grid electrode on two opposite sides of the second active layer. The first active layer and the second active layer are arranged on the same layer, the first grid electrode and the third grid electrode are arranged on the same side, and the second grid electrode and the fourth grid electrode are arranged on the same side. In this embodiment, at least one of the first gate and the second gate may be used as a control terminal of the driving transistor, and at least one of the third gate and the fourth gate may be used as a control terminal of the switching transistor, where a control manner of the control terminal of the driving transistor and a control manner of the control terminal of the switching transistor are different to achieve different electrical properties, so that the switching transistor has a high mobility characteristic and a relatively strong stability. In this embodiment, only one active layer of full oxide is provided, so that stability of the driving transistor and high mobility of the switching transistor can be considered, and multiple active layers are not required to be provided to integrate LTPS technology and IGZO technology simultaneously to meet different electrical properties, so that the process flow of the display panel is simplified, the process cost is greatly reduced, and the circuit layout space can be increased. In addition, compared with LTPO technology, the embodiment is not easy to be influenced by water vapor and the like, reduces the technology difficulty and is convenient for realizing the mass production requirement of the display panel.
The foregoing is the core idea of the present invention, and the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without making any inventive effort are intended to fall within the scope of the present invention.
The pixel circuit includes a driving transistor T1 and at least one switching transistor T2. The driving transistor T1 is used for generating a driving current for driving the corresponding light emitting element 111, and the switching transistor T2 is used for controlling the voltages of the gate and the source/drain of the driving transistor T1 so as to control the magnitude of the driving current output by the driving transistor T1. As shown in fig. 1, the display panel includes a substrate 31, and pixel circuits and light emitting elements 111 sequentially provided on the substrate 31. The driving transistor T1 includes a first active layer 11, a first gate electrode 12 at a first side of the first active layer 11, and a second gate electrode 13 at a second side of the first active layer 11. That is, the driving transistor T1 includes two gates respectively disposed at opposite sides of the first active layer 11. Similarly, the switching transistor T2 includes a second active layer 14, a third gate electrode 15 on a first side of the second active layer 14, and the second active layer 14 is distant from the third gate electrode 15 on the first side. The switching transistor T2 includes two gates respectively disposed on opposite sides of the second active layer 14. In this embodiment, the first side of the first active layer 11 may be a side close to the substrate 31 or a side far from the substrate 31, which is not particularly limited in this embodiment, and the first side of the first active layer 11 and the second active layer 14 close to the substrate 31 is exemplified in fig. 1. As shown in fig. 1, the first active layer 11 and the second active layer 14 are disposed in the same active layer, and are manufactured by the same process, and then the first gate electrode 12 and the third gate electrode 15 are disposed on the same side of the active layer, and the second gate electrode 13 and the fourth gate electrode 16 are disposed on the same side of the active layer. Alternatively, the active layer in this embodiment may be a full oxide layer, and the full oxide layer may implement an electrical adjustment or optimize a device during adjustment of two gate potentials of the transistors, so as to implement compatibility of transistors with different performances in the same display panel. Specifically, the potential control method of the two gates of the driving transistor T1 is different from the potential control method of the two gates of the switching transistor T2. In addition, the display panel may further include a source/drain layer 17, where the source/drain layer 17 can connect adjacent transistors to realize current signal transmission.
Optionally, the first gate 12 is used as a control terminal of the driving transistor T1, the second gate 13 is connected to the first constant potential V1, the fourth gate 16 is used as a control terminal of the switching transistor T2, and the third gate 15 is connected to the second constant potential V2. For the driving transistor T1, the first gate 12 is used as a control end, the first constant potential V1 of the second gate 13 affects the first active layer 11, so that the subthreshold swing of the first active layer 11 can be greatly changed, the subthreshold swing of the first active layer 11 is increased by the first constant potential V1, the subthreshold swing represents the change amount of the voltage value of the control end required by ten times of the change of the source leakage current (driving current) of the driving transistor T1, when the subthreshold swing is larger, if the voltage value of the control end slightly fluctuates, the driving current generated by the driving transistor T1 is not greatly disturbed, and the stability is stronger, especially under the low gray scale display picture, the driving force of the driving transistor T1 is strong, the picture is stable, and the display effect is good. For the switching transistor T2, the second constant potential V2 of the third gate 15 can control the speed of the carriers of the second active layer 14 forming the inversion layer, so as to increase the moving speed of the carriers in the electric field, so that the switching transistor T2 has high mobility, improves the conductivity, and realizes smaller subthreshold swing.
In this embodiment, only one active layer is provided, and by providing a double gate for each transistor, the gates of the driving transistor T1 and the switching transistor T2 adopt different control modes, so as to adjust the electrical properties of the devices of different transistors. In this embodiment, a few film layers and a simple film layer process are adopted, so that different device performances of the driving transistor T1 and the switching transistor T2 can be ensured at the same time. Fig. 2 is a schematic structural diagram of LTPO display panels according to an embodiment of the present invention. In the prior art, in order to simultaneously accommodate different device performances of the driving transistor and the switching transistor, a manufacturing process of LTPO is adopted, as shown in fig. 2, a transistor T1 'manufactured by a LTPO process, a transistor T2' manufactured by an IGZO process, and a light emitting element 111 'are disposed on a substrate 11', an active layer 12 'of the transistor T1' is low-temperature polysilicon, and in order to increase a subthreshold swing, a larger width-to-length ratio needs to be set, and an active layer 13 'of the transistor T2' is indium gallium zinc oxide, which has a higher mobility of carriers. LTPO the display panel needs to be provided with two active layers made of different materials, the process difficulty is complex, the compatibility requirement on the hybrid device is high, the cost is increased, and each pixel circuit occupies a large layout space, so that the difficulty of further development of the display panel is increased. In addition, since LTPO needs to give consideration to the performance of IGZO and LTPS devices at the same time, the electrical property of the IGZO device is easily affected by water vapor, the performance requirement on the process edge is high, and in order to ensure the low gray level visual effect and the uniformity of the picture, the LTPS needs to increase the width-to-length ratio of the driving transistor, further increases the layout space of the pixel circuit, and affects the PPI of the display panel. The embodiment adopts a film structure with simple and answering structure and small structural change, is compatible with different device performances of the driving transistor T1 and the switching transistor T2, and compared with LTPO technology, the technical process of the embodiment is simplified, the driving transistor T1 does not need to be provided with a larger width-to-length ratio, the layout space is reduced, and the device development difficulty is simplified. And the sensitivity of the switching transistor T2 is not high, and the stability is strong. In this embodiment, the device electrical property can be automatically adjusted by the first constant potential V1 and the second constant potential V2, so as to achieve different display requirements.
Alternatively, the materials of the first active layer 11 and the second active layer 14 may be oxides of a set metal including at least one of gallium, hafnium, tin, lanthanum, indium, praseodymium, and zinc. Along with the gradual aging of LTPO technologies, this embodiment is to reduce the cost, perform a process of full oxide, where the full oxide is an oxide of a set metal, and the set metal may include rare metals such as tin, hafnium, etc., rare earth metals such as lanthanum, praseodymium, etc., or may include rare metals such as gallium, indium, etc., or may further include relatively wide metal elements such as zinc, etc., to form the first active layer 11 and the second active layer 14 of full oxide, so that no active layer of low-temperature polysilicon material needs to be provided, thereby effectively simplifying the process flow of the pixel circuit.
Fig. 3 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention. Alternatively, each of the first active layer 11 and the second active layer 14 may include a first oxide layer 21 and a second oxide layer 22, the first oxide layer 22 being disposed on a side of the second oxide layer 22 near the first gate electrode 12 or the third gate electrode 15, and the mobility of carriers of the first oxide layer 21 being smaller than that of carriers of the second oxide layer 22. In this embodiment, the first active layer 11 and the second active layer 14 may each include a double oxide layer, i.e., a first oxide layer 21 and a second oxide layer 22, and the first oxide layer 21 and the second oxide layer 22 may have different electrical properties. Illustratively, because the first oxide layer 21 is disposed on the first side of the active layer near the control terminal of the driving transistor T1, the first oxide layer 21 may be disposed as a semiconductor layer having low mobility and strong stability to satisfy the device performance of the driving transistor T1, and because the second oxide layer 22 is disposed on the side of the active layer far from the first side near the control terminal of the switching transistor T2, the second oxide layer 22 may be disposed as a semiconductor layer having high mobility and weak stability to satisfy the device performance of the switching transistor T2. Optionally, the second oxide layer 22 has a relatively high content of metal elements such as gallium, tin, lanthanum, and hafnium, so as to achieve a relatively low carrier mobility. And the double full oxide layer can further amplify advantages brought about by structural changes, for example, the thickness ratio of the first oxide layer 21 and the second oxide layer 22 can be adjusted to further adjust the respective device performances.
Optionally, the thickness ratio of the first oxide layer 21 to the second oxide layer 22 may range from 3:1 to 1:1. Adjusting the thickness ratio of the first oxide layer 21 and the second oxide layer 22 can adjust mobility and stability of the entire active layer. In this embodiment, the width-to-length ratio of the driving transistor T1 needs to be reduced while ensuring the stability of the driving transistor T1, and the first oxide layer 21 may be provided closer to have a thicker film. Since the subthreshold swing needs to be increased by increasing the aspect ratio in the LTPS process, which increases the layout space of the pixel circuit and affects the PPI of the display panel, the present embodiment can increase the subthreshold swing of the entire active layer by only increasing the thickness of the first oxide layer 21, and the first oxide layer 21 is located at a side close to the control end of the driving transistor T1, and the first oxide layer 21 serves as the main driving layer of the driving transistor T1, further increasing the stability of the driving transistor T1. The second oxide layer 22 is disposed near the control terminal of the switching transistor T2, and the second oxide layer 22 serves as a main driving layer of the switching transistor T2, while increasing the stability of the driving transistor T1, maintaining the high mobility characteristic of the switching transistor T2.
Alternatively, the first oxide layer 21 may include indium oxide, gallium oxide, and zinc oxide, and the second oxide layer 22 may include indium oxide, gallium oxide, zinc oxide, and tin oxide. In this embodiment, the first oxide layer 21 includes indium oxide, gallium oxide, and zinc oxide, and the target is formed by sintering three oxide powders, which may be called IGZO, and the second oxide layer 22 includes indium oxide, gallium oxide, zinc oxide, and tin oxide, and the target is formed by sintering four oxide powders, which may be called IGZTO. The second oxide layer 22 increases tin oxide as compared to the first oxide layer 21, thereby enhancing mobility of carriers of the second oxide layer 22. When the first oxide layer 21 is IGZO material and the second oxide layer 22 is IGZTO material, the thickness ratio of the first oxide layer 21 to the second oxide layer 22 may be 2:1, so that the first oxide layer 21 meets the performance requirement of the driving transistor T1 for high subthreshold swing, and the second oxide layer 22 meets the performance requirement of the switching transistor T2 for high mobility, only one active layer is provided, so that the electrical performance of different transistor devices can be compatible, and in addition, the width-to-length ratio of both the driving transistor T1 and the switching transistor T2 can be kept small, the occupied area of the pixel circuit is reduced, and the PPI of the display panel is improved.
Of course, the first oxide layer 21 and the second oxide layer 22 may be other materials. Illustratively, the first oxide layer 21 may be a praseodymium (Pr) doped oxide (ITZO) system comprising indium, tin, and zinc, i.e., ITZO: pr. The above materials are excellent in light stability but low in mobility. The second active layer 14 may also be ITZO (In-rich ITZO) having a relatively high indium content, and the mobility of the In-rich ITZO material is high, but the light stability is poor. The two materials thus form a coupling relationship between mobility and stability. ITZO: pr formation assisted photoelectron relaxation (Carrier Relaxation Layer, CRL), in-rich ITZO forms the carrier transport layer (Carrier Transport Layer, CTL). When the active layer includes the first oxide layer 21 and the second oxide layer 22, the thickness ratio of the first oxide layer 21 and the second oxide layer 22 may be adjusted, and as shown in table 1, table 1 is a table of thickness ratio parameters of the first oxide layer and the second oxide layer, the total thickness of the first oxide layer 21 and the second oxide layer 22 may be set to 30nm, the thickness ratio of the first oxide layer 21 and the second oxide layer 22 may be defined, respectively, and the mobility μ FE and the shift amount Δvth of the threshold voltage under the negative bias illumination stress NBIS may be performed. Specifically, as shown In Table 1, when the active layer structures at 30nm are ITZO: pr, the mobility μ FE is 16.2, the threshold voltage shift ΔVth is-0.71, the mobility of the current carrier is low, the threshold voltage shift ΔVth is-1.12, the stability is excellent, when the active layer structures at 30nm are 15nm, the CRL thickness is 25nm, the mobility μ FE is 27.2, the threshold voltage shift ΔVth is-1.56, the mobility of the current carrier is gradually increased, the threshold voltage shift ΔVth is gradually increased, and the stability is reduced, similarly, when the active layer structures at 30nm are 10nm, the CRL thickness is 20nm, the mobility μ FE is 36.4, the threshold voltage shift ΔVth is-1.12, when the active layer structures at 30nm are 15nm, the CRL thickness is 15nm, the mobility μ FE is 43.3, the threshold voltage shift Δ70 is-1.20 nm, when the active layer structures at 30nm are 30nm, the threshold voltage shift ΔVth is 30.51, and the threshold voltage shift ΔVth is 50.51, when the threshold voltage shift ΔVth is 50.35.13, the threshold voltage shift ΔVth is 50.13, and the threshold voltage shift ΔVth is 50.13. from this, it is found that the mobility is high when the thickness of the CTL is increased, and the thickness ratio of the CTL to the CRL is 20/10, and the level of In-rich ITZO is nearly the whole, but the CRL is small at this time, so that the stability requirement of NBIS cannot be satisfied.
TABLE 1 thickness ratio parameter Table of first oxide layer and second oxide layer
Based on the above table 1, the present embodiment continues to increase the thickness of the CRL, and forms table 2, where table 2 is a table of the thickness ratio parameters of the first oxide layer and the second oxide layer after adjustment, because the CTL achieves higher mobility at the thickness of 20nm, the thickness of the CTL can be kept at 20nm, and the thickness of the CRL continues to be increased. As is clear from Table 1, when the CTL thickness was 20nm and the CRL thickness was 10nm, the mobility μ FE was 50.1, and the threshold voltage shift DeltaVth was-9.13. Referring to Table 2, the mobility μ FE was 47.1, the threshold voltage shift DeltaVth was-4.66, the CTL thickness 20nm, the CRL thickness 30nm, the mobility μ FE was 46.8, and the threshold voltage shift DeltaVth was-1.56, when the CTL thickness was 20nm, and the CRL thickness was 20 nm. As is clear from Table 2, the stability of NBIS was improved while the CRL thickness ratio was increased with the CTL thickness kept unchanged and the mobility was not greatly changed. In this embodiment, if the first oxide layer 21 is CRL and the second oxide layer 22 is CTL, the thickness of the first oxide layer 21 may be 30nm and the thickness of the second oxide layer 22 may be 20nm, so that the requirement of high subthreshold swing of the driving transistor T1 may be satisfied and the requirement of high mobility of the switching transistor T2 may be satisfied.
TABLE 2 thickness ratio parameter Table of adjusted first oxide layer and second oxide layer
| CTL/CRL | μFE(cm2/Vs) | NBIS△Vth(V) |
| 20/10 | 50.1 | -9.13 |
| 20/20 | 47.1 | -4.66 |
| 20/30 | 46.8 | -1.56 |
With continued reference to fig. 1, the display panel where the pixel circuit is located may optionally include at least a substrate 31, a first metal layer 32, an active layer 33 and a second metal layer 34 that are stacked, where the first active layer 11 and the second active layer 14 are both disposed on the active layer 33, the first gate 12 and the third gate 15 are disposed on the first metal layer 32, and the fourth gate 16 and the second gate 13 are disposed on the second metal layer 34. In this embodiment, the pixel circuit includes a first metal layer 32, an active layer 33, and a second metal layer 34 that are sequentially disposed away from the substrate 31, the active layer 33 is provided with the first active layer 11 and the second active layer 14, the first metal layer 32 is provided with the first gate electrode 12 and the third gate electrode 15, and the second metal layer 34 is provided with the fourth gate electrode 16 and the second gate electrode 13. Of course, in other embodiments of the present invention, as shown in fig. 4, fig. 4 is a schematic structural diagram of another pixel circuit provided in the embodiment of the present invention, the first gate electrode 12 and the third gate electrode 15 may be disposed on the second metal layer 34, and the fourth gate electrode 16 and the second gate electrode 13 may be disposed on the first metal layer 32. In this embodiment, the three-layer structure of the first metal layer 32, the active layer 33 and the second metal layer 34 is only used to realize compatibility of transistors with different electrical characteristics, and the process flow is simplified compared with LTPO process, so that the mass production efficiency of the display panel is improved. And the active layer 33 can be of a double-layer structure, so that the advantage brought by structural change is further amplified, and the performance adjustment is realized. And the thickness ratio (THICKNESS RATIO) of the bilayer structure can further adjust the device performance to meet the performance requirements of different types of transistors, for example, when the bilayer structure is a low mobility first oxide layer 21 and a high mobility second oxide layer 22, the first gate electrode 12 near the first oxide layer 21 is used as the control terminal of the driving transistor, and the fourth gate electrode 16 near the second oxide layer 22 is used as the control terminal of the switching transistor. Then for the driving transistor, which is bottom gate driving, the top gate inputs a constant potential, so as to greatly increase the subthreshold swing, improve the stability, and ensure the low gray scale display performance, on the basis, the stability is further increased by setting the first oxide layer 21 to be low mobility. For the switching transistor, the top gate is driven, the bottom gate is input with constant potential, the smaller width-to-length ratio is ensured, the smaller subthreshold swing is realized, the high mobility is realized, and the electrical property can be automatically regulated and the stability of the device can be optimized through the regulation of the constant potential of the bottom gate.
Optionally, the value range of the first constant potential V1 can be 0V-1.5V, and the value range of the second constant potential V2 can be-3V-0V. In the double-gate structure, if one gate is used as a control end, the other gate can be used as an auxiliary control end, the constant potential connected to the auxiliary control end can be set according to the requirements, the constant potential is different, and the auxiliary effect is different. The first gate 12 of the driving transistor T1 is a control end, the second gate 13 is used as an auxiliary control end to be connected with a constant voltage of 0V-1.5V, the fourth gate 16 of the switching transistor T2 is a control end, and the third gate 15 is used as an auxiliary control end to be connected with a constant voltage of-3V-0V. And because the second gate 13 is of a top gate structure, the first constant potential V1 accessed by the second gate 13 can realize fine control on the control end of the driving transistor T1, the third gate 15 is of a bottom gate structure, and the second constant potential V2 accessed by the third gate 15 is used for controlling the switching speed and stability of the switching transistor T2.
Alternatively, the first constant potential V1 and the second constant potential V2 may be the same. The second gate 13 of the driving transistor T1 and the third gate 15 of the switching transistor T2 may share one signal line to obtain a constant potential, thereby reducing the wiring density of the display panel and further improving the layout space of the display panel.
Alternatively, the second constant potential V2 may be multiplexed as the reference voltage signal Vref in the pixel circuit. Because the value range of the second constant potential V2 is preferably-3V to 0V, the second constant potential V2 in the embodiment can be multiplexed into the reference voltage signal Vref in the pixel circuit, so as to further reduce the panel wiring and reduce the panel power consumption. However, the thickness of the gate insulating layer between the top gate and the active layer is relatively thin, if the first constant potential V1 is connected to a negative value, the influence on the threshold voltage of the driving transistor T1 is relatively large, and the stability of the driving transistor T1 is reduced, so that the driving transistor T1 of the driving transistor T1 is preferably positive, the subthreshold swing of the driving transistor T1 is improved, the second constant potential V2 is preferably negative, and the switching speed of the switching transistor T2 is improved. Alternatively, the driving transistor T1 and the switching transistor T2 may be N-type transistors. Since the active layer in this embodiment is a full oxide material, each transistor in the pixel circuit can be an N-type transistor.
Taking an N-type transistor as an example, fig. 5 is a schematic circuit diagram of a pixel circuit according to an embodiment of the invention, fig. 6 is a schematic layout diagram of the pixel circuit in fig. 5, and fig. 7 is a schematic cross-sectional structure of the pixel circuit along a line segment a-a' in fig. 5. Referring to fig. 5 to 7, the pixel circuit may optionally further include a storage capacitor Cst and a light emitting element 111, the switching transistor T2 includes a first light emitting control transistor M1, a second light emitting control transistor M6, a first reset transistor M5, a second reset transistor M7, a threshold compensation transistor M4, and a data writing transistor M2, a control terminal of the first light emitting control transistor M1 is connected to a light emitting control signal EMIT, a first terminal of the first light emitting control transistor M1 is connected to a first power supply signal PVDD, a second terminal of the first light emitting control transistor M1 is electrically connected to a first terminal of the driving transistor T1, a control terminal of the driving transistor T1 is electrically connected to a first terminal of the second light emitting control transistor M6 through the storage capacitor Cst, a control terminal of the second light emitting control transistor M6 is used to be connected to the light emitting control signal EMIT, a second terminal of the second light emitting control transistor M6 is electrically connected to a first terminal of the light emitting element 111, the second electrode of the light emitting element 111 is connected to the second power signal PVEE, the control end of the first reset transistor M5 is connected to the first SCAN signal SCAN1, the first end of the first reset transistor M5 is connected to the reference voltage signal Vref, the second end of the first reset transistor M5 is electrically connected to the control end of the driving transistor T1, the control end of the second reset transistor M7 is connected to the second SCAN signal SCAN2, the first end of the second reset transistor M7 is connected to the reference voltage signal Vref, the second end of the second reset transistor M7 is electrically connected to the second end of the driving transistor T1, the control end of the threshold compensation transistor M4 is connected to the third SCAN signal SCAN3, the first end of the threshold compensation transistor M4 is electrically connected to the control end of the driving transistor T1, the second end of the threshold compensation transistor M4 is electrically connected to the second end of the driving transistor T1, the control end of the data writing transistor M2 is connected to the fourth SCAN signal SCAN4, the first end of the data writing transistor M2 is connected to the data signal SCAN1, and the second end of the data writing transistor vdm 2 is connected to the second end of the driving transistor T1.
The embodiment provides a schematic diagram of a 7T1C pixel circuit. The driving transistor T1 includes 6 switching transistors T2 (a first light emission control transistor M1, a second light emission control transistor M6, a first reset transistor M5, a second reset transistor M7, a threshold compensation transistor M4, and a data writing transistor M2). As shown in fig. 5, each transistor has a double-gate structure, and it should be noted that, in the double-gate structure shown in fig. 5, a gate with a deeper gray scale is a top gate, and a gate with a shallower gray scale is a bottom gate. The bottom gate of the driving transistor T1 is a control terminal, the top gate is connected to the first constant potential V1, the bottom gates of the other switching transistors T2 are connected to the second constant potential V2, and the top gate is a control terminal. The first SCAN signal SCAN1, the second SCAN signal SCAN2, the third SCAN signal SCAN3, the fourth SCAN signal SCAN4, and the emission control signal EMIT are used to control the pixel circuit to EMIT light. Optionally, the third SCAN signal SCAN3 is multiplexed into the fourth SCAN signal SCAN4. In the present embodiment, as shown in fig. 6, in order to further simplify the film layer arrangement of the display panel, the first constant potential V1 and the second constant potential V2 are set to be the same, and one constant potential transmission line 18 may be provided in the present embodiment.
Referring to fig. 6 and 7, which show only the film layers of the substrate 31, the first metal layer 32, the active layer 33, the second metal layer 34, and the source and drain layer 17, fig. 6 also shows a third metal layer 35, and the third metal layer 35 may be disposed on a side of the first metal layer 32 near the substrate 31, or may be disposed between the source and drain layer 17 and the substrate 31, so that the first metal layer 32 may be electrically connected to the constant potential transmission line 18 of the third metal layer 35 through the flying lead 19 on the source and drain layer 17. The first metal layer 32 may be provided with the first gate electrode 12 and the third gate electrode 15, the active layer 33 is provided with the first active layer 11 and the second active layer 14, the second metal layer 34 is provided with the second gate electrode 13 and the fourth gate electrode 16, and the source drain layer 17 may be provided with the data line 20 and the flying lead 19 outputting the data signal Vdata.
Fig. 7 shows the driving transistor T1 and the switching transistor M5. The top gate (fourth gate 16) of the switching transistor M5 serves as a control terminal of the switching transistor M5, and the bottom gate (third gate 15) is used to access a constant voltage. The top gate (second gate 13) of the driving transistor T1 is connected to a constant voltage through a connection line 171, and the bottom gate (first gate 12) is electrically connected as a control terminal to the switching transistor M5. As shown in fig. 6 and 7, compared with LTPO display panels, the present embodiment changes the existing LTPO complex process flow through structural design, so that the assumption of the full-oxide active layer 33 becomes possible, the top gate of the switching transistor is a control end, the bottom gate is connected to a constant voltage, the structural advantage is that the electrical property can be adjusted independently and the stability of the device is optimized, the bottom gate of the driving transistor T1 is a control end, the top gate is connected to a constant voltage, the subthreshold swing SS can be greatly increased, the low gray scale performance is ensured, meanwhile, the requirement on the width-to-length ratio W/L of the driving transistor T1 is low, the performance requirement of the driving transistor T1 can be met by a small-sized device, on the basis, the advantage brought by the structural change can be further amplified, the requirement of the switching transistor on small W/L, small SS and high mobility is met, and the requirement of the driving transistor on small W/L, large SS and low mobility is ensured. And the film layer has a simple structure, greatly improves layout space, and simplifies the development difficulty of devices. And the display panel is not easily affected by water vapor and the like, so that the process difficulty is reduced, and the mass production requirement of the display panel is conveniently realized.
Fig. 8 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, as shown in fig. 8, in another embodiment of the present invention, a pixel circuit is further provided, including:
The driving transistor T3 and the at least one switching transistor T4, wherein the driving transistor T1 comprises a first active layer 112, a first grid electrode 121 arranged on a first side of the first active layer 112 and a second grid electrode 131 arranged on a first side of the first active layer 112 far away from the first side, the at least one switching transistor T4 comprises a second active layer 141, a third grid electrode 151 arranged on a first side of the second active layer 141 and a fourth grid electrode 161 arranged on a second side of the second active layer 141 far away from the first side, the first active layer 112 and the second active layer 141 are arranged in the same layer, the first grid electrode 121 serves as a control end of the driving transistor T3, the second grid electrode 131 is used for receiving a third constant potential V3, and the third grid electrode 151 and the fourth grid electrode 161 serve as control ends of the switching transistor T4.
In the embodiment of the invention, the pixel circuit comprises a driving transistor and at least one switching transistor, wherein the driving transistor comprises a first active layer, a first grid electrode and a second grid electrode on two opposite sides of the first active layer, and the switching transistor comprises a second active layer, a third grid electrode and a fourth grid electrode on two opposite sides of the second active layer. The first active layer and the second active layer are arranged on the same layer, the first grid electrode and the third grid electrode are arranged on the same side, and the second grid electrode and the fourth grid electrode are arranged on the same side. In this embodiment, the first gate may be used as the control end of the driving transistor, the second gate receives the fineness of the third constant potential control end, and the third gate and the fourth gate are used as the control ends of the switching transistor, so that the control modes of the control ends of the driving transistor and the control modes of the control ends of the switching transistor are different to realize different electrical properties, so that the switching transistor has the characteristic of high mobility, and the driving transistor has relatively strong stability. In this embodiment, only one active layer of full oxide is provided, so that stability of the driving transistor and high mobility of the switching transistor can be considered, and multiple active layers are not required to be provided to integrate LTPS technology and IGZO technology simultaneously to meet different electrical properties, so that the process flow of the display panel is simplified, the process cost is greatly reduced, and the circuit layout space can be increased. In addition, compared with LTPO technology, the embodiment is not easy to be influenced by water vapor and the like, reduces the technology difficulty and is convenient for realizing the mass production requirement of the display panel.
Fig. 9 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention, as shown in fig. 9, in another embodiment of the present invention, a pixel circuit is further provided, including:
The driving transistor T5 and at least one switching transistor T6, wherein the driving transistor T5 comprises a first active layer 113, a first grid electrode 122 arranged on a first side of the first active layer 113 and a second grid electrode 132 arranged on a first side of the first active layer 113 away from the first side, the at least one switching transistor T6 comprises a second active layer 142, a third grid electrode 152 arranged on a first side of the second active layer 142 and a fourth grid electrode 162 arranged on a second side of the second active layer 142 away from the first side, the first active layer 113 and the second active layer 142 are arranged in the same layer, the first grid electrode 122 and the second grid electrode 132 serve as control ends of the driving transistor T5, the fourth grid electrode 165 serves as a control end of the switching transistor T6, and the third grid electrode 152 is used for receiving a fourth constant potential V4.
In the embodiment of the invention, the pixel circuit comprises a driving transistor and at least one switching transistor, wherein the driving transistor comprises a first active layer, a first grid electrode and a second grid electrode on two opposite sides of the first active layer, and the switching transistor comprises a second active layer, a third grid electrode and a fourth grid electrode on two opposite sides of the second active layer. The first active layer and the second active layer are arranged on the same layer, the first grid electrode and the third grid electrode are arranged on the same side, and the second grid electrode and the fourth grid electrode are arranged on the same side. In this embodiment, the first gate and the second gate may be used as the control end of the driving transistor, and the fourth gate is used as the control end of the switching transistor, where the third gate is connected to a fourth constant potential to control the switching speed and stability of the switching transistor, and the control mode of the control end of the driving transistor and the control mode of the control end of the switching transistor are different to implement different electrical properties, so that the switching transistor has a high mobility characteristic and a relatively strong stability. In this embodiment, only one active layer of full oxide is provided, so that stability of the driving transistor and high mobility of the switching transistor can be considered, and multiple active layers are not required to be provided to integrate LTPS technology and IGZO technology simultaneously to meet different electrical properties, so that the process flow of the display panel is simplified, the process cost is greatly reduced, and the circuit layout space can be increased. In addition, compared with LTPO technology, the embodiment is not easy to be influenced by water vapor and the like, reduces the technology difficulty and is convenient for realizing the mass production requirement of the display panel.
Based on the same concept, the embodiment of the present invention further provides a display panel, as shown in fig. 10, and fig. 10 is a schematic structural diagram of the display panel according to the embodiment of the present invention, including the pixel circuit 100 according to any embodiment of the present invention.
The display panel provided by the embodiment of the invention comprises the technical characteristics of the pixel circuit provided by any embodiment of the invention, and has the beneficial effects of corresponding technical characteristics.
The embodiment of the invention also provides a display device. Fig. 11 is a schematic structural diagram of a display device according to an embodiment of the present invention, and as shown in fig. 11, the display device according to an embodiment of the present invention includes a display panel 200 according to any embodiment of the present invention. The display device may be a mobile phone as shown in fig. 11, or may be a computer, a television, an intelligent wearable device, etc., which is not limited in this embodiment.
In this embodiment, the display device includes the technical features of the display panel provided in any embodiment of the present invention, and has the beneficial effects of the corresponding features, which are not described herein.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (16)
1. A pixel circuit is characterized by comprising a driving transistor and at least one switching transistor;
The driving transistor comprises a first active layer, a first grid electrode arranged on a first side of the first active layer and a second grid electrode arranged on the first active layer far away from the first side;
At least one of the switching transistors includes a second active layer, a third gate electrode disposed on a first side of the second active layer, and a fourth gate electrode disposed on the second active layer away from the first side;
The first active layer and the second active layer are arranged on the same layer, the first grid electrode is used as a control end of the driving transistor, the fourth grid electrode is used as a control end of the switching transistor, the second grid electrode is used for receiving a first constant potential, and the third grid electrode is used for receiving a second constant potential.
2. The pixel circuit according to claim 1, wherein materials of the first active layer and the second active layer are each an oxide of a set metal;
The setting metal includes at least one of gallium, hafnium, tin, lanthanum, indium, and zinc.
3. The pixel circuit of claim 1, wherein the first active layer and the second active layer each comprise a first oxide layer and a second oxide layer;
The first oxide is arranged on one side of the second oxide layer, which is close to the first grid electrode or the third grid electrode;
The mobility of the carriers of the first oxide layer is smaller than the mobility of the carriers of the second oxide layer.
4. The pixel circuit according to claim 3, wherein a thickness ratio of the first oxide layer and the second oxide layer ranges from 3:1 to 1:1.
5. The pixel circuit of claim 3 wherein the first oxide layer comprises indium oxide, gallium oxide, and zinc oxide and the second oxide layer comprises indium oxide, gallium oxide, zinc oxide, and tin oxide.
6. The pixel circuit according to claim 5, wherein the thickness ratio of the first oxide layer and the second oxide layer is 2:1.
7. The pixel circuit according to claim 1, wherein the display panel in which the pixel circuit is located includes at least a substrate, a first metal layer, an active layer, and a second metal layer which are stacked;
the first active layer and the second active layer are both arranged on the active layer, the first grid electrode and the third grid electrode are arranged on the first metal layer, and the fourth grid electrode and the second grid electrode are arranged on the second metal layer.
8. The pixel circuit according to claim 7, wherein the first constant potential has a value ranging from 0v to 1.5v;
the value range of the second constant potential is-3V-0V.
9. The pixel circuit of claim 8, wherein the second constant potential is multiplexed as a reference voltage signal in the pixel circuit.
10. The pixel circuit according to claim 7, wherein the first constant potential is the same as the second constant potential.
11. The pixel circuit according to claim 2, wherein the drive transistor and the switching transistor are both N-type transistors.
12. The pixel circuit according to claim 1, wherein the pixel circuit further comprises a storage capacitor and a light emitting element, the switching transistor comprises a first light emitting control transistor, a second light emitting control transistor, a first reset transistor, a second reset transistor, a threshold compensation transistor, and a data writing transistor;
The control end of the first light-emitting control transistor is connected with a light-emitting control signal, the first end of the first light-emitting control transistor is connected with a first power signal, the second end of the first light-emitting control transistor is electrically connected with the first end of the driving transistor, the control end of the driving transistor is connected with the first power signal through the storage capacitor, the second end of the driving transistor is electrically connected with the first end of the second light-emitting control transistor, the control end of the second light-emitting control transistor is used for being connected with the light-emitting control signal, the second end of the second light-emitting control transistor is electrically connected with the first electrode of the light-emitting element, and the second electrode of the light-emitting element is connected with a second power signal;
The control end of the first reset transistor is connected with a first scanning signal, the first end of the first reset transistor is connected with a reference voltage signal, the second end of the first reset transistor is electrically connected with the control end of the driving transistor, the control end of the second reset transistor is connected with a second scanning signal, the first end of the second reset transistor is connected with the reference voltage signal, and the second end of the second reset transistor is electrically connected with the second end of the driving transistor;
The control end of the threshold compensation transistor is connected with a third scanning signal, the first end of the threshold compensation transistor is electrically connected with the control end of the driving transistor, the second end of the threshold compensation transistor is electrically connected with the second end of the driving transistor, the control end of the data writing transistor is connected with a fourth scanning signal, the first end of the data writing transistor is connected with a data signal, and the second end of the data writing transistor is electrically connected with the first end of the driving transistor.
13. A pixel circuit is characterized by comprising a driving transistor and at least one switching transistor;
The driving transistor comprises a first active layer, a first grid electrode arranged on a first side of the first active layer and a second grid electrode arranged on the first active layer far away from the first side;
At least one of the switching transistors includes a second active layer, a third gate electrode disposed on a first side of the second active layer, and a fourth gate electrode disposed on the second active layer away from the first side;
The first active layer and the second active layer are arranged in the same layer, the first grid electrode is used as a control end of the driving transistor, the second grid electrode is used for receiving a third constant potential, and the third grid electrode and the fourth grid electrode are used as control ends of the switching transistor.
14. A pixel circuit is characterized by comprising a driving transistor and at least one switching transistor;
The driving transistor comprises a first active layer, a first grid electrode arranged on a first side of the first active layer and a second grid electrode arranged on the first active layer far away from the first side;
At least one of the switching transistors includes a second active layer, a third gate electrode disposed on a first side of the second active layer, and a fourth gate electrode disposed on the second active layer away from the first side;
The first active layer and the second active layer are arranged on the same layer, the first grid electrode and the second grid electrode are used as control ends of the driving transistor, the fourth grid electrode is used as a control end of the switching transistor, and the third grid electrode is used for receiving a fourth constant potential.
15. A display panel comprising a pixel circuit as claimed in any one of claims 1 to 14.
16. A display device comprising the display panel of claim 15.
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| CN202411907803.5A CN119811306A (en) | 2024-12-23 | 2024-12-23 | Pixel circuit, display panel and display device |
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