CN119815907B - Method for manufacturing semiconductor device and semiconductor device - Google Patents
Method for manufacturing semiconductor device and semiconductor device Download PDFInfo
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- CN119815907B CN119815907B CN202510272617.7A CN202510272617A CN119815907B CN 119815907 B CN119815907 B CN 119815907B CN 202510272617 A CN202510272617 A CN 202510272617A CN 119815907 B CN119815907 B CN 119815907B
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Abstract
The invention provides a manufacturing method of a semiconductor device and the semiconductor device, wherein a first type groove is formed on the side of a grid structure by etching part of a second interlayer dielectric layer and part of a first interlayer dielectric layer, and a second type groove is formed above the grid structure by etching part of the first interlayer dielectric layer; etching the second interlayer dielectric layer to form a convex part structure, a first wiring groove and a second wiring groove, wherein one side of the convex part structure is the first wiring groove, the other side of the convex part structure is the second wiring groove, etching the first interlayer dielectric layer and the second interlayer dielectric layer to deepen the first type groove and the second type groove until the first type groove is connected with metal silicide of the semiconductor structure and the second type groove is connected with a gate oxide layer of the gate structure, filling part of the second type groove to form a metal gate, simultaneously forming the first type groove and part of the second type groove to form a contact plug, and filling the first wiring groove and the second wiring groove to form a metal layer.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technology, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
In the fabrication of complementary metal oxide semiconductors (Complementary Metal Oxide Semiconductor, CMOS), the quality of the gate and contact formation is an important factor affecting device yield and reliability. During the gate and contact hole processing, etching and polishing results in depressions in the surface of the contact etch stop layer and uneven dielectric layer surface. And metal residues may be present after the gate is polished during the gate and contact hole process, thereby increasing the likelihood of shorting the contacts Kong Duanlu and gates. In addition, in the process of manufacturing the gate electrode and the contact hole, the surface of the metal gate electrode may bulge due to pattern loading, so that the turn-on voltage of the metal gate electrode is increased. Therefore, the forming yield of the gate and contact hole manufacturing process is low, resulting in low device reliability.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device and the semiconductor device, which can improve the molding yield of a CMOS semiconductor device and improve the reliability of the device.
In order to solve the technical problems, the invention is realized by the following technical scheme:
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
Providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a gate structure, and the gate structure is arranged on the substrate;
forming a first interlayer dielectric layer on the semiconductor structure, and forming a second interlayer dielectric layer on the first interlayer dielectric layer;
Etching part of the second interlayer dielectric layer and part of the first interlayer dielectric layer to form a first type groove at the side of the grid structure, and etching part of the first interlayer dielectric layer to form a second type groove above the grid structure;
Etching the second interlayer dielectric layer to form a convex part structure, a first wiring groove and a second wiring groove, wherein one side of the convex part structure is the first wiring groove, and the other side of the convex part structure is the second wiring groove;
Etching the first interlayer dielectric layer and the second interlayer dielectric layer, and extending the first type groove and the second type groove until the first type groove is connected with the metal silicide of the semiconductor structure and the second type groove is connected with the gate oxide layer of the gate structure;
Filling part of the second type trench, forming a metal gate, simultaneously filling the first type trench and part of the second type trench, forming a contact plug, and
And filling the first wiring groove and the second wiring groove to form a metal layer.
In an embodiment of the present invention, the step of forming the first interlayer dielectric layer includes:
A protective layer is formed over the semiconductor structure,
Forming a first interlayer dielectric layer on the protective layer, and
And grinding the first interlayer dielectric layer until the first interlayer dielectric layer is flush with the nitride layer of the gate structure, wherein the nitride layer covers the polysilicon layer of the gate structure.
In an embodiment of the present invention, after the second interlayer dielectric layer is formed, a stacked structure is formed on the second interlayer dielectric layer, where the stacked structure includes a protection layer, an anti-reflection layer, and a first photoresist layer.
In an embodiment of the present invention, in the step of etching the first type trench and the second type trench, an orthographic projection of an etching window of the first type trench on the substrate overlaps with a functional region of the semiconductor structure, and an orthographic projection of an etching window of the second type trench on the substrate overlaps with a polysilicon layer of the gate structure.
In an embodiment of the present invention, a width of an etching window for forming the second type trench is larger than a width of an etching layer window for forming the first type trench.
In an embodiment of the present invention, the step of forming the first wiring trench and the second wiring trench includes:
etching the second interlayer dielectric layer between adjacent first trenches to form the first wiring trenches, and
And etching part of the second interlayer dielectric layer between the first type groove and the second type groove to form the second wiring groove, and forming a convex structure between the first type groove and the second type groove.
In an embodiment of the present invention, in the step of forming the first type trench and the second type trench, a bottom of the first type trench is formed in a middle portion of the first interlayer dielectric layer, and a bottom of the second type trench is formed in a middle portion of the second interlayer dielectric layer.
In one embodiment of the present invention, after the first type trench and the second type trench are formed, a photoresist pattern is formed in the first type trench and the second type trench, and on the second interlayer dielectric layer between the first type trench and the second type trench.
In an embodiment of the present invention, after the first wiring trench and the second wiring trench are filled in the step of forming the metal layer, the metal layer is polished until the metal layer is flush with the surface of the convex structure.
The present invention provides a semiconductor device including:
A semiconductor structure comprising a substrate and a gate structure disposed on the substrate;
the first interlayer dielectric layer is arranged on the semiconductor structure;
the second interlayer dielectric layer is arranged on the first interlayer dielectric layer, wherein the second interlayer dielectric layer comprises a convex part structure, one side of the convex part structure is provided with a first wiring groove, and the other side of the convex part structure is provided with a second wiring groove;
the first type trenches penetrate through the first interlayer dielectric layer and the second interlayer dielectric layer and are connected with the metal silicide of the semiconductor structure, and the first type trenches are communicated with the first wiring trenches;
the second type of groove penetrates through the first interlayer dielectric layer and is connected with the gate oxide layer of the gate structure, and the second type of groove is communicated with the second wiring groove;
The metal grid electrode is filled in the second type groove and covers the grid oxide layer;
a contact plug filled in the first type trench and the second type trench and connected to the metal gate or the metal silicide, and
And a metal layer filled in the first wiring trench and the second wiring trench and connected to the contact plug.
As described above, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device, which have unexpected technical effects in that in the process of forming a gate and a contact hole, not only metal residues are avoided, but also non-preset depressions caused by overetching are avoided, so that the forming yield of the metal gate is high, and defects caused by a polishing process and a loading effect on the gate forming and the contact hole forming are reduced, thereby improving the yield of the forming process of the gate and the contact hole, and further improving the reliability of the semiconductor device. The manufacturing method of the semiconductor device and the semiconductor device provided by the invention have the advantages of low complexity of the manufacturing process and high manufacturing efficiency.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic view of a semiconductor structure according to an embodiment of the invention.
FIG. 2 is a schematic diagram of an embodiment of an etching stop layer.
FIG. 3 is a schematic diagram illustrating a structure of depositing a first interlayer dielectric layer according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of a polishing process for the first interlayer dielectric layer according to an embodiment of the invention.
FIG. 5 is a schematic diagram illustrating a stacked structure according to an embodiment of the invention.
FIG. 6 is a schematic diagram of a structure for forming a photolithographic trench according to an embodiment of the invention.
Fig. 7 is a schematic structural diagram of forming a first type trench and a second type trench according to an embodiment of the invention.
FIG. 8 is a schematic diagram illustrating a structure of forming a second photoresist layer according to an embodiment of the invention.
FIG. 9 is a schematic diagram of a structure for forming a second photoresist pattern according to an embodiment of the invention.
Fig. 10 is a schematic structural view of a protrusion structure according to an embodiment of the invention.
FIG. 11 is a schematic diagram of a device structure after removing the second photoresist pattern according to an embodiment of the invention.
Fig. 12 is a schematic structural diagram of a first type trench and a second type trench after deep development in an embodiment of the invention.
FIG. 13 is a schematic diagram of a second type of trench after deep development in accordance with an embodiment of the present invention.
Fig. 14 is a schematic view of a metal layer, a metal gate and a contact plug according to an embodiment of the invention.
FIG. 15 is a schematic diagram of a structure of a metal layer, a metal gate and a contact plug after polishing according to an embodiment of the present invention.
In the figure, 100, a semiconductor structure, 110, a substrate, 111, a deep well region, 112, a first well region, 113, a second well region, 114, a first doping region, 115, a second doping region, 116, a metal silicide, 120, a gate structure, 121, a gate oxide layer, 122, a polysilicon layer, 123, a side wall structure, 1231, a nitride layer, 200, a protective layer, 300, a first interlayer dielectric layer, 400, a second interlayer dielectric layer, 410, a protective layer, 420, a first anti-reflection layer, 430, a second anti-reflection layer, 440, a convex structure, 500, a first photoresist layer, 510, a photoetching groove, 520, a first type groove, 530, a second type groove, 600, a second photoresist layer, 610, a second photoresist pattern, 620, a first wiring groove, 630, a second wiring groove, 700, a metal layer, 710 and a contact plug.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The semiconductor device provided by the invention comprises a metal gate. And the semiconductor device provided by the invention can be one or more of a field effect Transistor (FIELD EFFECT Transistor, FET), a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a complementary Metal Oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS), an insulated gate bipolar Transistor (Insulated Gate Bipolar Transistor, IGBT), a high-speed recovery Diode (Fast Recovery Diode, FRD), a high-speed high-efficiency rectifier Diode (FIGH EFFICIENCY Diode, HED), a constant voltage Diode, a high-frequency Diode, a Light-Emitting Diode (LED), a gate Photo-blocking Thyristor (Gate Turn off Thyristor, GTO), a Photo-triggered Thyristor (LIGHT TRIGGERED christor, LTT), a Thyristor (Thyristor), a charge coupler (Charge Coupled Device, a CCD image sensor), a digital signal processing device (DIGITAL SIGNAL Processor, DSP), a Light Relay (Photo Relay), or a microprocessor (Micro Processor). In this embodiment, the semiconductor device is a CMOS semiconductor device.
Referring to fig. 1, in the method for manufacturing a semiconductor device according to the present invention, a semiconductor structure 100 is provided first. The semiconductor structure 100 includes a substrate 110. The substrate 110 is, for example, a silicon base material forming the semiconductor structure 100. The substrate 110 may include a base material, such as a semiconductor substrate material of silicon (Si), silicon carbide (SiC), sapphire (Al 2O3), gallium arsenide (GaAs), lithium aluminate (LiAlO 2), or the like, and a silicon layer disposed over the base material. Phosphorus ions or arsenic ions can be implanted into the silicon layer of the substrate 110 to form a deep well region 111 and a plurality of well regions, doped regions. Wherein a plurality of well regions, such as a first well region 112 and a second well region 113, are located above the deep well region 111. In the present embodiment, the doping ions of the first well region 112 and the second well region 113 are different. Specifically, the first well region 112 may be a P-well, and the second well region 113 may be an N-well. The well region continues to be implanted with a plurality of ions to form source and drain regions of semiconductor structure 100. And ions can be implanted into the well region, and the concentration of the implanted ions can be adjusted to form a heavily doped region or a lightly doped region, etc., which is not particularly limited in the present invention. In this embodiment, for example, a first doped region 114 is formed in the first well region 112. The second well region 113 is formed with, for example, a second doped region 115. It should be noted that the type and structure of the doped region are not limited in the present invention. If the first doped region 114 is a doped structure with a rectangular cross section, the second doped region 115 is doped with sigma. A metal silicide 116 is then formed on top of the first doped region 114 and the second doped region 115 by a metal silicide process.
Referring to fig. 1, in one embodiment of the present invention, a semiconductor structure 100 includes a gate structure 120. The gate structure 120 is disposed on the substrate 110, and the gate structure 120 is disposed between the source region and the drain region of the semiconductor structure 100. The gate structure 120 includes a gate oxide 121, a polysilicon layer 122, and a sidewall structure 123. In the present embodiment, the gate oxide layer 121 is disposed on the substrate 110. The drawings do not show the multilayer structure of the gate oxide layer 121. In this embodiment, the gate oxide layer 121 may be a stacked structure of an oxide and a high-K dielectric layer. For example, the gate oxide layer 121 includes a hafnium oxide layer and a titanium nitride layer. Wherein a polysilicon layer 122 is disposed on the gate oxide layer 121. The sidewall structure 123 is wrapped outside the polysilicon layer 122 and the gate oxide layer 121. In this embodiment, the sidewall structure 123 includes at least one silicon nitride layer and at least one silicon oxide layer. Wherein the silicon nitride layer is coated on the outside of the polysilicon layer 122 and the gate oxide layer 121, and the silicon oxide layer is disposed on the silicon nitride layer. Wherein the silicon nitride layer may be the nitride layer 1231 as shown in fig. 1.
Referring to fig. 1 and 2, in an embodiment of the present invention, a passivation layer 200 is formed on the semiconductor structure 100. In this embodiment, silicon nitride is deposited on the substrate 110, the gate structure 120, and the metal silicide 116 by chemical Vapor Deposition (Chemical Vapor Deposition, CVD) or plasma enhanced chemical Vapor Deposition (PLASMA ENHANCED CHEMICAL Vapor Deposition, PECVD), etc., so as to form a thin film-shaped protection layer 200 for protecting the semiconductor structure 100 from damage during subsequent processes. Wherein the protective layer 200 covers the semiconductor structure 100.
Referring to fig. 2 and 3, in an embodiment of the invention, a first interlayer dielectric layer 300 is formed on the passivation layer 200. In this embodiment, silicon oxide is deposited on the protective layer 200 by chemical vapor deposition or plasma enhanced chemical vapor deposition, so as to form the first interlayer dielectric layer 300. Wherein the thickness of the first interlayer dielectric layer 300 is greater than the height of the gate structure 120. Specifically, the first interlayer dielectric layer 300 covers the gate structure 120. As shown in fig. 3, when the first interlayer dielectric layer 300 is formed, the surface of the first interlayer dielectric layer 300 is uneven. Specifically, the area of the first interlayer dielectric layer 300 covering the gate structure 120 is higher than the area covering the substrate 110, and the area of the first interlayer dielectric layer 300 covering the gate structure 120 is higher than the area covering the metal silicide 116.
Referring to fig. 3 and 4, in an embodiment of the present invention, the surface of the first interlayer dielectric layer 300 is polished to expose the sidewall structure 123 covering the polysilicon layer 122, and the surface of the first interlayer dielectric layer 300 is level with the surface of the nitride layer 1231. In this embodiment, the nitride layer 1231 is a layer of silicon nitride directly covering the polysilicon layer 122 in the sidewall structure 123. And nitride layer 1231 is the innermost layer of sidewall structure 123. In this embodiment, the first interlayer dielectric layer 300 and a portion of the sidewall structure 123 are processed by chemical mechanical Polishing (CHEMICAL MECHANICAL Polishing). Specifically, the nitride layer 1231 covering the top of the polysilicon layer 122 is used as a polishing stop layer, and part of the first interlayer dielectric layer 300 and part of the sidewall structure 123 are removed by polishing. Wherein the removed portion of the sidewall structure 123 is the portion of the sidewall structure 123 over the nitride layer 1231 on top of the polysilicon layer 122. At this time, the surfaces of the first interlayer dielectric layer 300 and the nitride layer 1231 are flush.
Referring to fig. 4 to 6, in an embodiment of the invention, after polishing the first interlayer dielectric layer 300, a stacked structure is formed on the first interlayer dielectric layer 300. In this embodiment, borophosphosilicate glass (Boro phospho SILICATE GLASS, BPSG) is deposited on the first interlayer dielectric layer 300 by chemical vapor deposition or plasma enhanced chemical vapor deposition, etc., to form the second interlayer dielectric layer 400. Next, a passivation layer 410 is formed on the second interlayer dielectric layer 400. Wherein the protective layer 410 is an APF film and the material is amorphous carbon. A plurality of photolithography auxiliary layers are then formed on the overcoat layer 410. In this embodiment, the lithography-assist layer includes a first anti-reflective layer 420 and a second anti-reflective layer 430. Wherein the Anti-reflective layer is an ARC film (Anti-Reflection Coating, ARC). Next, a photoresist is spin-coated on the second anti-reflection layer 430 to form a first photoresist layer 500. The first photoresist layer 500 is patterned by exposure etching or the like to form a plurality of photolithography trenches 510, and the first photoresist layer 500 is converted into a first photoresist pattern. In this embodiment, the orthographic projection of a portion of the photolithographic trench 510 onto the gate structure 120 is located on the polysilicon layer 122, and the orthographic projection of another portion of the photolithographic trench 510 onto the substrate 110 is located on the metal silicide 116. And the trench width of the photolithographic trench 510 located on the polysilicon layer 122 is greater than the trench width of the photolithographic trench 510 located on the metal silicide 116. The present invention is not limited to the bottom of the photolithographic trench 510. The bottom of the photolithographic trench 510 in this embodiment may be the first anti-reflection layer 420.
Referring to fig. 6 and 7, in an embodiment of the present invention, the first type trench 520 and the second type trench 530 are formed by removing a portion of the first anti-reflection layer 420, a portion of the protective layer 410, a portion of the second interlayer dielectric layer 400, and a portion of the first interlayer dielectric layer 300 by dry etching using the first photoresist pattern as a mask. In this embodiment, when the etching environments are the same, and the etching objects are the same, the first type trenches 520 are formed by directly etching the first interlayer dielectric layer 300 to a larger etching depth because the trench width of the photolithographic trench 510 located on the metal silicide 116 is smaller. And the trench width of the photolithographic trench 510 located on the polysilicon layer 122 is larger, so the etching depth is smaller, and only the second interlayer dielectric layer 400 is etched, thereby forming the second type trench 530. Wherein the second type of grooves 530 have a greater groove width than the first type of grooves 520. In this embodiment, when the first trench 520 is formed, etching is stopped until the first interlayer dielectric layer 300 is etched at any position. For example, the etching may be stopped when etching to the middle of the first interlayer dielectric layer 300, forming the first type trenches 520 and the second type trenches 530. After the first type trenches 520 and the second type trenches 530 are formed, the first photoresist pattern, the first anti-reflection layer 420, the second anti-reflection layer 430, and the protective layer 410 are washed away, exposing the second interlayer dielectric layer 400.
Referring to fig. 7 to 9, in an embodiment of the present invention, a second photoresist layer 600 is formed by filling a photoresist into the first type trench 520 and the second type trench 530. In this embodiment, after the photoresist fills the first type trenches 520 and the second type trenches 530, the photoresist is continuously accumulated, and a film structure is formed on the second interlayer dielectric layer 400, as shown in fig. 8, so as to form the second photoresist layer 600. The second photoresist layer 600 is then processed by exposure and development, etc., to form a second photoresist pattern 610. When patterning the second photoresist layer 600, portions of the photoresist in the first type trenches 520 and the second type trenches 530 remain, and portions of the photoresist on the second interlayer dielectric layer 400 remain. In this embodiment, the second photoresist pattern 610 is located on the second interlayer dielectric layer 400, in the first type trench 520 or in the second type trench 530.
Referring to fig. 9 to 11, in an embodiment of the present invention, a portion of the second interlayer dielectric layer 400 is removed by using the second photoresist pattern 610 as a mask layer, so as to form a first wiring trench 620 and a second wiring trench 630, and form a protrusion structure 440. In the present embodiment, the second photoresist pattern 610 remaining in the first type trenches 520 and the second type trenches 530 can protect the portions of the first type trenches 520 and the second type trenches 530 from etching. And on the second interlayer dielectric layer 400, the region not covered by the second photoresist pattern 610 is etched until the top surface of the second photoresist pattern 610 located in the first type trench 520 and the second type trench 530 is etched, thereby forming the first wiring trench 620 and the second wiring trench 630. Wherein the bottom of the first wiring trench 620 connects the top surfaces of the second photoresist patterns 610 located in the first type trench 520 and the second type trench 530. In the present embodiment, a plurality of step-shaped protrusion structures 440 are formed on top of the second interlayer dielectric layer 400 while the first wiring trench 620 is formed. In this embodiment, the orthographic projection on the substrate 110 of the first wiring trench 620 connects the source of the first device and the drain of the second device. Wherein the first device and the second device are adjacent. The orthographic projection of the second wiring trench 630 on the gate structure 120 overlaps the polysilicon layer 122. In this embodiment, the orthographic projection of the second wiring trench 630 on the gate structure 120 covers the polysilicon layer 122. The second photoresist pattern 610 is then removed, exposing the first type trenches 520 and the second type trenches 530. In the present embodiment, the first wiring trench 620 communicates with the first type trench 520 of a different device. The second wiring trench 630 communicates with the second type trench 530.
Referring to fig. 11 and 12, in an embodiment of the present invention, the first type trench 520 is deep, such that the first type trench 520 extends to the top surface of the metal silicide 116. The second type trenches 530 are deep such that the second type trenches 530 extend to the top surface of the polysilicon layer 122. In this embodiment, the top surface of the metal silicide 116 is used as an etching stop layer to etch the first interlayer dielectric layer 300 to deep the first type trench 520. Meanwhile, the second interlayer dielectric layer 400 is etched using the top surface of the polysilicon layer 122 as an etch stop layer to extend the second type trenches 530. In this etching step, the surface of the exposed metal silicide 116 is used as an etching stop signal, so that the polysilicon layer 122 can be etched more than a part.
Referring to fig. 12 and 13, in an embodiment of the present invention, the polysilicon layer 122 is etched away to continue to deepen the second type trench 530 until the polysilicon layer 122 is completely removed. In this embodiment, the polysilicon layer 122 is removed by wet etching. In another embodiment of the present invention, in the step of deepening the first type trenches 520, after exposing the surface of the metal silicide 116, the etching of the polysilicon layer 122 may be continued until the polysilicon layer 122 is removed. Since the material of the metal silicide 116 and the polysilicon layer 122 are completely different, the surface of the metal silicide 116 is still not damaged during the step of removing the polysilicon layer 122.
Referring to fig. 1 and fig. 13 to fig. 15, in an embodiment of the present invention, a first type trench 520 and a second type trench 530 are filled to form a metal interconnection structure and a metal gate 800. And the surface of the metal interconnect structure is polished so that the top surface of the metal interconnect structure is flush with the top surface of the bump structure 440. In this embodiment, the first type trench 520, the second type trench 530, the first wiring trench 620 and the second wiring trench 630 are filled with a metal material, such as copper-aluminum alloy and tungsten, by chemical vapor deposition or sputtering, so that the metal gate 800 is formed in the second type trench 530, the contact plug 710 is formed in the first type trench 520 and the first wiring trench 620, and the metal layer 700 is formed in the second wiring trench 630. Wherein a metal gate 800 is disposed on the gate oxide 121. Wherein after the first and second wire trenches 620 and 630 are filled, the metal material continues to be accumulated, and the thickness of the metal layer 700 is increased. At this time, the metal layer 700 is electrically connected to the metal gate 800. In this embodiment, the metal layer 700 is subjected to a chemical mechanical polishing process, and the thickness of the metal layer 700 is reduced until the surface of the metal layer 700 is flush with the top surface of the bump structure 440, at which time the metal layer 700 is electrically connected to the source of one device and the drain of another device, and the metal gate 800 is separately led out. In this embodiment, to ensure that the convex structures 440 have a good separation effect, part of the convex structures 440 may be removed during polishing, so that the surfaces of the convex structures 440 are flush with the surface of the metal layer 700, and the semiconductor device structure of the present invention is formed. The structure of the metal gate 800 is shown separately in fig. 15 for ease of resolution. In the present invention, the metal gate 800, the contact plug 710 and the metal layer 700 are formed in the same step, and the materials used are identical.
The invention provides a method for manufacturing a semiconductor device and the semiconductor device, which are characterized in that a part of a second interlayer dielectric layer and a part of a first interlayer dielectric layer are etched, and forming a first type groove on the side of the gate structure, and etching part of the first interlayer dielectric layer to form a second type groove on the upper side of the gate structure. And etching the second interlayer dielectric layer to form a convex part structure, a first wiring groove and a second wiring groove, wherein one side of the convex part structure is the first wiring groove, and the other side of the convex part structure is the second wiring groove. Etching the first interlayer dielectric layer and the second interlayer dielectric layer, and extending the first type groove and the second type groove until the first type groove is connected with the metal silicide of the semiconductor structure and the second type groove is connected with the gate oxide layer of the gate structure. Filling part of the second type of grooves to form metal gates, and simultaneously filling the first type of grooves and part of the second type of grooves to form contact plugs. And filling the first wiring trench and the second wiring trench to form a metal layer. The invention has the unexpected technical effects that in the forming process of the grid electrode and the contact hole, metal residues are avoided, and non-preset concave occurrence caused by overetching is avoided, so that the forming yield of the metal grid electrode is high, and defects caused by the polishing process and the loading effect to the grid electrode forming and the contact hole forming can be reduced, thereby improving the yield of the forming process of the grid electrode and the contact hole and improving the reliability of the semiconductor device. The manufacturing method of the semiconductor device and the semiconductor device provided by the invention have the advantages of low complexity of the manufacturing process and high manufacturing efficiency.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
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| US12471343B2 (en) * | 2021-06-17 | 2025-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Gate isolation features in semiconductor devices and methods of fabricating the same |
| CN119451207B (en) * | 2024-11-12 | 2025-11-04 | 中国科学院微电子研究所 | A method for manufacturing a semiconductor device and a vertically stacked semiconductor device |
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