CN119815895A - Wafer substrate for improving warpage generated during epitaxial layer growth and use thereof - Google Patents

Abstract

The invention relates to a wafer substrate for improving the warping generated during the growth of an epitaxial layer and its use. The invention belongs to the field of semiconductors. In order to improve the warping problem generated during the growth of an epitaxial layer, the invention provides a first stress release area on the substrate, wherein the first stress release area is provided on the outer ring of the wafer and is symmetrically distributed around the center of the wafer; the first stress release area is an axisymmetric figure, wherein the axis of symmetry points to the center of the circle and gradually widens in a direction away from the center of the circle along the axis of symmetry; the invention has the beneficial effect of reducing the damage to the wafer caused by stress during the growth of the epitaxial layer, reducing the occurrence of bad warping, and in particular reducing the production restrictions on large-size wafers, thereby improving the yield and reliability of the device.

Description

Wafer substrate for improving warpage generated in epitaxial layer growth process and application thereof

Technical Field

The invention belongs to the field of semiconductors, and particularly relates to a wafer substrate for improving warpage generated in an epitaxial layer growth process and application thereof.

Background

Nitride semiconductor materials, such as gallium nitride, aluminum nitride, etc., have advantages of high electron mobility, high breakdown voltage, etc., over conventional silicon material devices in the fabrication of power devices.

In the fabrication of power devices of nitride semiconductor materials, the nitride semiconductor material is typically formed by epitaxial growth on a heterogeneous material substrate. For example, in a process flow for manufacturing a high electron mobility transistor of gallium nitride material, it is necessary to epitaxially grow an epitaxial layer of gallium nitride material on a substrate of silicon, silicon carbide or aluminum nitride material.

However, since the substrate material (silicon, silicon carbide, aluminum nitride, or the like) and the epitaxially grown nitride semiconductor material have a large lattice mismatch and a large difference in thermal expansion coefficient. Therefore, wafer warpage is easy to generate in a high-temperature epitaxial growth process and a process of cooling to normal temperature after the growth process, and more grown crystal defects can be caused under thermal stress, compared with a heating process, the warpage in the cooling process is more needed to be avoided, and micro cracks and even more crystal defects can be caused to epitaxial layer crystals due to material deformation in the cooling process.

The wafer warpage affects subsequent processing and affects the final product yield and reliability. In addition, as the wafer size increases, particularly in the wafer manufacturing process of 8 inches or more, the problem becomes more serious, thus limiting the increase in wafer size and the further decrease in production cost.

Disclosure of Invention

The invention provides a patterned heterogeneous substrate structure for epitaxial growth of nitride semiconductor materials. The invention provides a preparation method of a power device wafer of a nitride semiconductor material, which is beneficial to improving the problems of wafer warpage caused by epitaxial growth of the nitride semiconductor material and crystal defects caused by stress deformation.

The wafer substrate for improving the warping in the epitaxial layer growth process comprises a substrate and more than four first stress release areas arranged on the substrate, wherein the first stress release areas are arranged on the outer circle of the wafer and are symmetrically distributed around the center of the circle of the wafer, the first stress release areas are axisymmetric patterns, the symmetry axes of the first stress release areas point to the center of the circle, the first stress release areas gradually widen along the direction of the symmetry axes away from the center of the circle, the number of the first stress release areas can be 4, 6, 8 and the like, the center of the circle of the wafer is used as the center of symmetry to form central symmetry, the first stress release areas are axisymmetric patterns, and the symmetry axes are the radius of the wafer. For wafers with small sizes, the first stress release area positioned on the outer ring is only needed.

Further, a second stress release area with an area smaller than that of the first stress release area is further arranged above the substrate and in the middle of the adjacent first stress release area, the second stress release area is arranged on the inner ring of the wafer and is symmetrically distributed by taking the circle center of the wafer as the center, the second stress release area is in an axisymmetric graph, the symmetry axis of the second stress release area points to the circle center, and the second stress release area gradually widens along the direction away from the circle center of the symmetry axis. For the wafer with large size, on the basis of arranging the first stress release area positioned on the outer ring, a second stress release area positioned on the inner ring can be additionally arranged.

Further, the first stress release area comprises a first platform area and a first slope area which is uniformly transited from the plane of the first platform area to the plane of the substrate, wherein the included angle between the slope surface of the first slope area and the plane of the substrate is 2-45 degrees, or the second stress release area comprises a second platform area and a second slope area which is uniformly transited from the plane of the second platform area to the plane of the substrate, and the included angle between the slope surface of the second slope area and the plane of the substrate is 2-45 degrees.

Furthermore, the first stress release area or the second stress release area is in a triangular pyramid shape, and the slope area is the main area of stress consumption, so that the area of the slope area can be increased due to the triangular pyramid shape, the included angle between the slope area and the substrate can be reduced, and the fracture of the bottom of the slope caused by stress can be avoided.

Further, the first stress release area or the second stress release area is an isosceles triangle, the acute angle pointing to the center of the wafer is 2-30 degrees, or the first stress release area or the second stress release area is an isosceles trapezoid, and the ratio of the bottom edge of the isosceles trapezoid to the height is 0.05-0.5.

Further, the upper and/or lower bases of the isosceles trapezoid are arc-shaped edges, wherein the lower base is near or coincident with the wafer edge.

Further, the first stress relief area or the second stress relief area gradually increases in height along the direction away from the center of the circle along the symmetrical axis.

The invention also provides an application of the wafer substrate warped in the epitaxial layer growth process, the wafer substrate is used for manufacturing a power device made of nitride semiconductor materials, and the manufacturing method comprises the following steps: firstly, forming a nitride semiconductor epitaxial layer on the wafer substrate by an epitaxial method in a high-temperature environment, and then cooling to normal temperature to further manufacture the nitride semiconductor power device.

The manufacturing method further comprises the second step of setting the area, adjacent to the slope area, of 100-3000um as a defective area for rejecting in the wafer spot measurement and sorting process.

The invention has the beneficial effects that the wafer is damaged by the stress in the epitaxial layer growth process, the generation of warping defect is reduced, the production limit on the large-size wafer is especially reduced, and the yield and the reliability of the device are improved.

Drawings

FIG. 1 is a schematic illustration of the distribution of stress relief regions over a wafer substrate;

FIG. 2 is a top view of a differently shaped relief area;

FIG. 3 is another embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view of the line A-A ', B-B' in FIG. 3;

FIG. 5 is a graph of the stress analysis of FIG. 3;

FIG. 6 is a further embodiment of the present invention;

FIG. 7 is a schematic cross-sectional view of line A-A ', B-B' of FIG. 6;

FIGS. 8-9 are schematic illustrations of the formation of stress relief regions;

FIG. 10 is a further embodiment of the present invention;

Fig. 11 shows a region that can be removed as defective products in the wafer spot inspection and sorting process.

Detailed Description

The following describes the background of the related art. It is noted that corresponding positional words such as "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "vertical" as described in this document are relative positions corresponding to the reference drawings. The fixing direction is not limited in the specific implementation. It should be noted that the devices in the drawings are not necessarily drawn to scale. The doped regions and trenches in the drawings, the straight lines shown at the boundaries of the material layers, and the sharp corners formed by the boundaries are generally not straight lines and precise angles in practice.

The present invention will be described in detail below with reference to the drawings and examples.

The present invention proposes a wafer substrate 200 with a stress relief region 201 for forming a nitride semiconductor epitaxial layer.

In addition, a method for forming a power device wafer of the nitride semiconductor material of the present invention is as follows:

in a first step, a wafer substrate 200 having a stress relief region 201 is provided.

And secondly, forming a nitride semiconductor epitaxial layer on the substrate by an epitaxial method in a high-temperature environment, and cooling to normal temperature.

And thirdly, continuing processing to finally form the nitride semiconductor power device.

The wafer substrate 200 may be silicon, aluminum oxide, silicon carbide, or aluminum nitride material. In one embodiment, the wafer substrate 200 is a silicon material and the gallium nitride epitaxial layer is formed on the substrate by an epitaxial method. In another embodiment, the wafer substrate 200 is a silicon carbide material and the gallium nitride epitaxial layer is formed on the substrate by an epitaxial method.

Fig. 1 is a schematic diagram showing the distribution of stress relief regions 201 on a wafer substrate 200, where the stress relief regions 201 on the wafer have more than 4 stress relief regions and are symmetrically distributed around the wafer center and uniformly around the wafer periphery. The stress relief region 201 has a height different from the rest of the wafer, and the stress relief region 201 is typically 0.5-8um higher than the rest of the wafer.

The stress relief region 201 itself is an axisymmetric pattern, its axis of symmetry B-B' is generally directed toward the center of the wafer, and the stress relief region 201 may also increase in height gradually as it gets farther from the center, from 0 μm at the end closest to the center to 8 μm at the highest height at the end furthest from the center.

Fig. 2 shows a top view of a differently shaped relief area 201, one embodiment 2A shows that the relief area 201 is an isosceles triangle, the angle pointing towards the center of the wafer is an acute angle, the angle is between 2-30 °, one embodiment 2B shows that the relief area 201 is an isosceles trapezoid, the ratio of the bottom side to the height of the isosceles trapezoid is between 0.05-0.5, one variant embodiment 2C shows that the side of the relief area 201 pointing towards the center is an arc side, and one embodiment 2D shows that the side of the relief area 201 facing away from the center is an arc side, which may coincide with the side of the wafer or be close to the edge of the wafer.

In some embodiments, the stress relief region 201 may be disposed at the outermost periphery of the amorphous wafer, and thus the edge of the stress relief region 201 away from the center may be a straight line, or an edge of varying curvature, or even other more complex boundary.

Example 2

One embodiment is shown in FIG. 3, which is a top view of the stress relief region 201 of this embodiment, and FIGS. 4A and 4B are schematic cut-away views of the lines A-A ', B-B' of FIG. 3, respectively.

In this embodiment, the stress relief region 201 has a plateau region 202 that is higher than the rest of the wafer, and a ramp region 210 that transitions to the plateau region 202. In one practical embodiment, the mesa region 202 is 0.5-8um higher than the rest of the wafer, the angle @ between the slope of the ramp region 210 and the wafer is between 2-45 degrees, the slower the slope, the lower the stress of the wafer substrate 200 and epitaxial layer 102 at the ramp corners, and the less prone to crystal cracking at the corners.

The nitride semiconductor epitaxial layer 102 is formed on the wafer substrate 200 by an epitaxial method, and in the process of high-temperature re-cooling to normal temperature, the stress direction in the epitaxial layer 102 is changed according to the shape of the stress relief region 201 due to the existence of the stress relief region 201.

Fig. 5A and 5B are schematic views of stress directions during cooling of the nitride semiconductor epitaxial layer 102 to room temperature at the corresponding positions of 4A and 4B, respectively.

As shown in fig. 5A, in the direction perpendicular to the wafer spindle (tangent A-A '), the stress has a component in the height direction (Z-axis), which is advantageous for reducing the stress in the horizontal direction and for reducing wafer warpage in the tangent A-A'.

As shown in fig. 5B, in the direction along the wafer spindle (tangent line B-B '), the stress has a component in the height direction (Z axis), which is advantageous for reducing the stress in the horizontal direction and for reducing the wafer warpage in the tangent line B-B'.

Accordingly, the stress relief region 201 has a stress relief function in both directions perpendicular to the wafer spindle direction (tangent line A-A ') and the wafer spindle direction (tangent line B-B'). Providing symmetrical, uniform stress relief regions 201 on the wafer is advantageous for reducing warpage of the overall wafer, while reducing stress of the epitaxial layer on the wafer plane.

Example 3

Based on the embodiment of fig. 4, a variant embodiment is shown in fig. 6, and fig. 7 is a schematic cross-sectional view of the line A-A ', B-B' in fig. 6, respectively.

In this embodiment, the stress relief region 201 is a triangular pyramid structure having a gradually increasing height along the axis of symmetry B-B', wherein the plateau-free region 202 is absent and only the ramp region 210, compared to the embodiment of fig. 4, wherein the stress of the wafer substrate 200 and epitaxial layer 102 at the corners of the ramp is lower, which is advantageous in providing a less sloped ramp region 210, and in avoiding stress induced cracking at the bottom of the ramp.

In the above embodiment, the stress relief region 201 and the wafer substrate 200 are formed by default of the same material. In some embodiments, the stress relief region 201 portions may also be composed of a heterogeneous material that is different from the wafer substrate 200.

For example, in one embodiment, the wafer substrate 200 is comprised of a silicon material and the relief area 201 above the substrate may be comprised of silicon carbide, aluminum nitride, gallium nitride, or the like.

For another example, in one embodiment, the wafer substrate 200 is comprised of a silicon carbide material and the stress relief region 201 above the substrate may be comprised of aluminum nitride, gallium oxide, or the like.

Example 4

As mentioned in the above embodiments, there are various methods for forming the wafer structure of the wafer substrate 200 having the stress relief region 201.

One possible method of formation is as follows:

first, a patterned photoresist is formed on a planar substrate.

And secondly, etching the exposed substrate area under the protection of photoresist.

And thirdly, removing the photoresist. The region protected by the photoresist at this time is the stress relief region 201.

Another possible formation method is as follows:

in a first step, a heterogeneous material is formed on a planar substrate.

In a second step, a photoresist is formed over the heterogeneous material.

And thirdly, photoetching the heterogeneous material to form a patterned heterogeneous material.

And fourth, removing the photoresist. The patterned heterogeneous material region protected by the photoresist at this point is the stress relief region 201.

Another possible formation method is as follows:

in a first step, a heterogeneous material is formed on a planar substrate.

In a second step, a photoresist is formed over the heterogeneous material.

Third, the heterogeneous material is subjected to photolithography to form patterned heterogeneous material 232 and expose the substrate material.

And fourth, removing the photoresist.

Fifth, the substrate material is etched under the protection of the patterned heterogeneous material 232, as shown in fig. 8.

And sixthly, removing the heterogeneous material. The patterned substrate region protected by the heterogeneous material is now the stress relief region 201, as shown in fig. 9.

Example 5

In addition to the embodiments described above, the stress relief region 201 of the present invention may have a more complex distribution over the wafer, depending on the desired stress relief effect.

For example, on a larger wafer, more stress relief regions 201 are provided. As shown at 10A in fig. 10, on a wafer larger than 8 inches, 8 or more equally spaced stress relief regions 201 are provided around the periphery.

For another example, the stress relief region 201 may have multiple sets of different patterns, and multiple sets of different distances from the wafer center. As shown in fig. 10B, a set of inner ring stress relief regions 217 and a set of outer ring stress relief regions 218 are provided within the wafer. Wherein, the inner ring stress relief region 217 has a smaller area and the outer ring stress relief region 218 has a larger area, corresponding to the difference in distance from the wafer circle, the inner ring stress relief region 217 and the outer ring stress relief region 218 may be the same as or different from the stress relief region 201 in the previous embodiment. This arrangement is advantageous for balancing in-plane stresses in the wafer.

In one practical embodiment of the substrate structure, 8 or 16 symmetrical release areas are provided on a 8 inch and 700-1200um thick boron doped silicon material wafer substrate 200 wafer, the release areas are isosceles triangles and the short sides are 3-20um long, and the angle of the angle pointing to the center of the wafer is 10-30 degrees. The relief region 201 has a plateau region 202 and a ramp region 210, the plateau region being 1-5um higher than the wafer, the ramp region 210 being at an angle between 20-45 degrees from the wafer.

In an embodiment of forming a gallium nitride device by an epitaxial method using the above-described substrate structure, the epitaxial temperature is between 1100-1250 degrees, the thickness of the gallium nitride epitaxial layer 102 is between 1-5um, and the warpage of the gallium nitride epitaxial wafer formed after the epitaxy is less than 40um.

Example 6

In addition, since the stress relief region 201 has the slope region 210, crystal defects, crystal dislocation, etc. formed in the subsequent epitaxial process of the slope region 210 may be more. Therefore, devices in the region of the ramp region 210 in the release region 201 can be removed in response to the finally formed wafer, preventing the yield and reliability of the devices from being affected. As shown in fig. 11, in the wafer spot inspection and sorting process, the area (hatched area in the figure) adjacent to the slope area 210 of 100 to 3000um is set as a defective area for screening, that is, the area can be directly removed as a defective area.

Furthermore, those skilled in the art will appreciate that the structural features and process steps recited in each of the above-described embodiments of the invention may be combined with one another to form further device structures and manufacturing flows of the embodiments of the invention.

It will be appreciated by those skilled in the art that the above manufacturing steps list only key steps and do not demonstrate complete steps for forming the device. The specific details of the fabrication process may be suitably varied and increased according to the common general knowledge and process steps of the fabrication process known in the art.

Claims (9)

1. A wafer substrate for improving warping in an epitaxial layer growing process is characterized by comprising a substrate and more than four first stress release areas arranged on the substrate, wherein the first stress release areas are arranged on the outer ring of the wafer and are symmetrically distributed around the center of a circle of the wafer, the first stress release areas are axisymmetric patterns, symmetry axes of the first stress release areas point to the center of the circle, and the first stress release areas gradually widen along the direction away from the center of the circle along the symmetry axes.

2. The wafer substrate for improving the warpage in the epitaxial layer growth process according to claim 1, wherein a second stress relief area smaller than the first stress relief area is further arranged above the substrate and in the middle of the adjacent first stress relief area, the second stress relief area is arranged on the inner ring of the wafer and symmetrically distributed by taking the center of the circle of the wafer as the center, the second stress relief area is in an axisymmetric pattern, the symmetry axis of the second stress relief area points to the center of the circle, and the second stress relief area gradually widens along the direction away from the center of the circle along the symmetry axis.

3. The wafer substrate for improving warpage in epitaxial layer growth process of claim 1 or 2, wherein said first stress relief region comprises a first mesa region and a first slope region uniformly transitioning from a plane of said first mesa region to a plane of said substrate, an included angle between a slope of said first slope region and a plane of said substrate being 2-45 DEG, or

The second stress release areas comprise second platform areas and second slope areas which are uniformly transited from the planes of the second platform areas to the planes of the substrates, and the included angle between the slope surfaces of the second slope areas and the planes of the substrates is 2-45 degrees.

4. The wafer substrate for improving warpage in an epitaxial layer growth process according to claim 1 or 2, wherein the first stress relief region or the second stress relief region is triangular pyramid-shaped.

5. The wafer substrate for improving warpage in epitaxial layer growth process according to claim 1 or 2, wherein the first stress relief area or the second stress relief area is isosceles triangle, the acute angle pointing to the center of the wafer is 2-30 degrees, or the first stress relief area or the second stress relief area is isosceles trapezoid, and the ratio of the bottom side of the isosceles trapezoid to the height is 0.05-0.5.

6. A wafer substrate for improving warpage in an epitaxial layer growth process as set forth in claim 5 wherein the upper base and/or lower base of the isosceles trapezoid is curved, wherein the lower base is adjacent to or coincident with the wafer edge.

7. The wafer substrate for improving warpage in epitaxial layer growth process according to claim 1 or 2, wherein the first stress relief region or the second stress relief region gradually increases in height away from the center of the circle along the symmetry axis.

8. The method for manufacturing a power device of nitride semiconductor material, which is characterized in that, according to the use of the wafer substrate for improving the warpage in the epitaxial layer growth process as set forth in claim 1 or 2, the method for manufacturing the power device of nitride semiconductor material comprises the steps of forming a nitride semiconductor epitaxial layer on the wafer substrate by an epitaxial method in a high-temperature environment, and then cooling to normal temperature for further manufacturing the power device of nitride semiconductor.

9. The method of claim 8, wherein the wafer substrate for improving warpage in epitaxial layer growth further comprises removing the adjacent 100-3000um slope region as defective region during wafer spot measurement and sorting.