CN119814166A - Frequency domain equalization method, medium and device based on PD-DD-LMS architecture - Google Patents
Frequency domain equalization method, medium and device based on PD-DD-LMS architecture Download PDFInfo
- Publication number
- CN119814166A CN119814166A CN202510047146.XA CN202510047146A CN119814166A CN 119814166 A CN119814166 A CN 119814166A CN 202510047146 A CN202510047146 A CN 202510047146A CN 119814166 A CN119814166 A CN 119814166A
- Authority
- CN
- China
- Prior art keywords
- frequency domain
- vector
- polarization
- input
- vectors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
Abstract
本发明公开了一种基于PD‑DD‑LMS架构的频域均衡方法、介质及设备，涉及相干光通信系统数字信号处理领域，基于PD‑DD‑LMS架构的频域均衡方法主要包括：利用奇偶分离和串并转换方法将输入序列转换为多个数据块并进行快速傅里叶变换得到多个频域输入块向量，利用多输入多输出频域均衡器得到频域输出块向量并进行快速傅里叶逆变换，丢弃前面的预设数量的元素得到时域输出块向量；根据时域输出块向量，利用相位相关决策定向最小均方乘算法和梯度下降算法，更新滤波器抽头权重。实施本发明提供的基于PD‑DD‑LMS架构的频域均衡方法、介质及设备，能在不降低抗相位噪声和抗频率偏移性能的同时，降低计算复杂度。
The present invention discloses a frequency domain equalization method, medium and device based on PD-DD-LMS architecture, which relates to the field of digital signal processing of coherent optical communication systems. The frequency domain equalization method based on PD-DD-LMS architecture mainly includes: using odd-even separation and serial-to-parallel conversion methods to convert an input sequence into multiple data blocks and perform fast Fourier transform to obtain multiple frequency domain input block vectors, using a multi-input multi-output frequency domain equalizer to obtain a frequency domain output block vector and perform inverse fast Fourier transform, discarding the front preset number of elements to obtain a time domain output block vector; according to the time domain output block vector, using a phase-related decision-oriented least mean square algorithm and a gradient descent algorithm to update the filter tap weights. Implementing the frequency domain equalization method, medium and device based on PD-DD-LMS architecture provided by the present invention can reduce the computational complexity without reducing the anti-phase noise and anti-frequency offset performance.
Description
Technical Field
The invention relates to the field of digital signal processing of a coherent optical communication system, in particular to a frequency domain equalization method, medium and equipment based on a PD-DD-LMS architecture.
Background
With the rapid development of communication technology, an optical fiber communication system has become a mainstream transmission mode of a modern communication network due to the advantages of large bandwidth, high transmission rate, strong anti-interference capability and the like. However, as the scale and transmission rate of fiber optic communication networks continue to increase, the performance and transmission quality of the systems face increasingly complex challenges. In coherent optical communication systems, signals, after being transmitted through optical fibers, suffer from problems such as chromatic dispersion, nonlinear effects, frequency offset, etc., which can lead to serious degradation of signal quality, particularly in high-speed and large-capacity systems.
In order to overcome the negative effects caused by various injuries in the coherent optical transmission system, the adaptive FIR filter plays a very important role in the coherent optical transmission system. Tap coefficients of the FIR filter are updated by a tap adaptation algorithm. The performance of FIR filters with long delay taps is severely degraded when the phase noise of the transmitter laser and the local oscillator Laser (LO) and the frequency offset between them cause large carrier phase fluctuations within the delay time.
The new structure of the Finite Impulse Response (FIR) filter of the digital coherent optical receiver based on the phase correlation decision directed least mean square (PHASE-DEPENDENT DECISION-DIRECTED LEAST-meansquare algorithm, PD-DD-LMS) algorithm removes fast phase fluctuation from error signals updating the tap coefficients of the FIR filter by introducing a two-stage decision directed carrier phase estimator, and realizes stable self-adaption of the filter tap coefficients of a high-order Quadrature Amplitude Modulation (QAM) signal, and has better capability of resisting phase noise and frequency offset compared with the traditional DD-LMS method.
However, the computational complexity of the FIR filter increases with the number of delay taps, and it is difficult to implement the FIR filter having a large number of delay taps in an Application Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA) due to large power consumption and high gate density. There is therefore a need for a new equalization method that can reduce the computational complexity.
Disclosure of Invention
The invention aims to provide a frequency domain equalization method, medium and equipment based on a PD-DD-LMS architecture, which can effectively reduce the computational complexity while not reducing the performance of resisting phase noise and frequency offset.
The invention provides a frequency domain equalization method based on a PD-DD-LMS architecture, which comprises the following steps that S1, a plurality of data blocks are obtained by utilizing a parity separation and serial-parallel conversion method according to an input sequence;
S2, obtaining a plurality of frequency domain input block vectors by utilizing fast Fourier transform according to the plurality of data blocks, S3, obtaining a frequency domain output block vector by utilizing a multi-input multi-output frequency domain equalizer according to the plurality of frequency domain input block vectors, S4, carrying out fast inverse Fourier transform on the frequency domain output block vector and discarding the previous preset number of elements to obtain a time domain output block vector, and S5, updating filter tap weights by utilizing a phase correlation decision directed least mean square algorithm and a gradient descent algorithm according to the time domain output block vector.
Further, the step S1 specifically includes S11 of parity-separating the input sequence to obtainA polarization even sequence,An odd number of sequences,A polarization even sequence,An odd sequence of polarizations, said input sequence comprisingPolarized input sequencePolarization input sequence S12, utilizing serial-parallel conversion method to make said polarization input sequence according to preset quantityEven-numbered sequences of polarizations, saidOdd polarization sequences, theEven-numbered sequences of polarizations, saidThe polarization odd sequences are divided into a plurality of data blocks, respectively.
Further, the step S2 specifically includes obtaining a plurality of frequency domain input block vectors according to the plurality of data blocks by using fast Fourier transform, such as the formula:
,
Wherein, Represent the firstThe block vectors are input in the frequency domain,The fast fourier transform is represented by a set of coefficients,;The representation transposes the matrix.
Further, the step S3 specifically includes obtaining a frequency domain output block vector according to the multiple frequency domain input block vectors by using a multiple input multiple output frequency domain equalizer, such as the formula:
,
,
Wherein, Is thatPolarization of firstThe number of time-domain output block vectors,Is thatPolarization of firstThe number of time-domain output block vectors,、、、、、、AndTap coefficients respectively representing eight sub-equalizer frequency domain filters in the multiple-input multiple-output frequency domain equalizer; Representing a dot product operation between the frequency domain vectors; 、、、 Representing the respective even and odd sequences AndPolarization of firstThe block vectors are input in the frequency domain.
Further, the step S5 specifically comprises the steps of S51 of obtaining an error vector by utilizing a phase correlation decision directed least mean square multiplication algorithm according to the time domain output block vector, S52 of obtaining a frequency domain error vector by utilizing fast Fourier transform after filling the error vector by utilizing a preset number of 0S, S53 of obtaining a gradient vector according to the frequency domain error vector and the frequency domain input block vectors, and S54 of updating filter tap weights according to the gradient vector.
Further, the step S51 specifically includes obtaining an error vector according to the time domain output block vector by using a phase correlation decision directed least mean square multiplication algorithm, such as the formula:
,
,
,
,
,
Wherein, As a vector of the error it is,Representation ofPolarizationRepresentative ofAndPolarization) the desired signal in training mode or the decoded signal in tracking mode; Representation of The tap coefficient vector of the polarization first stage phase estimator,Representation ofThe tap coefficient vector of the polarization second stage phase estimator,Representing an equalizerAn output block vector on polarization; Is the step size parameter, the sign Meaning that the conjugate vector is taken out of it,Is a tap coefficient vector controlling the first stage phase estimatorIs a signal of error of (a); Is a step-size parameter that is used to determine, Is a tap coefficient vector controlling the second stage phase estimatorIs a function of the error signal.
Further, step S54 specifically includes updating filter tap weights according to the gradient vector, as shown in the formula:
,
Wherein, For updated filter tap weights applied to the next data block,To update the pre-filter tap weights applied to the current data block,For a step size parameter of random gradient descent,As a vector of the gradient,For representationAnd 0 s are filled.
The present invention also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the frequency domain equalization method described above based on the PD-DD-LMS architecture.
The invention also provides a computer device comprising a memory, a processor and a computer program stored on the memory and capable of running on the processor, wherein the processor executes the program to realize the steps of the frequency domain equalization method based on the PD-DD-LMS architecture.
The invention also provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the frequency domain equalization method based on the PD-DD-LMS architecture.
The frequency domain equalization method, medium and equipment based on the PD-DD-LMS architecture provided by the invention have the following beneficial effects:
The invention converts an input sequence into a plurality of data blocks by using a parity separation and serial-parallel conversion method and carries out fast Fourier transform to obtain a plurality of frequency domain input block vectors, obtains a frequency domain output block vector by using a multi-input multi-output frequency domain equalizer and carries out fast Fourier inverse transform, discards the previous preset number of elements to obtain a time domain output block vector, and updates the tap weight of a filter by using a phase correlation decision directed least mean square multiplication algorithm and a gradient descent algorithm according to the time domain output block vector. The invention is suitable for a polarization multiplexing transmission system, and reduces the computational complexity through block-by-block signal processing and effective realization of Discrete Fourier Transform (DFT) while having the same anti-phase noise and anti-frequency offset performance as time domain equalization.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
Fig. 1 is a flow chart of a frequency domain equalization method based on a PD-DD-LMS architecture provided by the present invention;
Fig. 2 is a schematic diagram of the overall structure of the frequency domain equalization method based on the PD-DD-LMS architecture provided by the present invention;
FIG. 3 is a schematic diagram of a phase correlation decision directed least mean square multiplication algorithm provided by the present invention;
FIG. 4 is a graph of performance versus simulation results for time domain equalization provided by the present invention;
FIG. 5 is a graph of experimental results of performance versus time domain equalization provided by the present invention;
FIG. 6 is a graph comparing the computational complexity of the time domain equalization provided by the present invention;
fig. 7 is a block diagram of a computer device according to the present invention.
Detailed Description
For a clearer understanding of technical features, objects and effects of the present invention, a detailed description of embodiments of the present invention will be made with reference to the accompanying drawings.
Fig. 1 shows a schematic diagram of a frequency domain equalization method based on the PD-DD-LMS architecture of this embodiment. In this embodiment, the frequency domain equalization method based on the PD-DD-LMS architecture includes the following steps:
s1, obtaining a plurality of data blocks by utilizing a parity separation and serial-parallel conversion method according to an input sequence;
In an exemplary embodiment, step S1 specifically includes:
S11, performing parity separation on the input sequence to obtain A polarization even sequence,An odd number of sequences,A polarization even sequence,An odd sequence of polarizations, said input sequence comprisingPolarized input sequenceA polarized input sequence;
s12, utilizing a serial-parallel conversion method to convert the data into a preset number Even-numbered sequences of polarizations, saidOdd polarization sequences, theEven-numbered sequences of polarizations, saidThe polarization odd sequence is divided into a plurality of data blocks respectively;
As an exemplary embodiment, in step S1, the input sequence is entered 、Each of which is parity-separated to obtain four odd/even sequences, each branch being further divided into a plurality of branches using serial-to-parallel (S/P) convertersThe block of dot data,Equal to the discrete frequency response of the frequency domain equalizer, i.e. the preset number is the discrete frequency response of the frequency domain equalizer, as shown in fig. 2, which is a schematic diagram of the overall structure of the frequency domain equalization method based on the PD-DD-LMS architecture of the present embodiment, fromAnd (3) withPolarized input sequenceThe division into odd and even sequences, since the frequency domain equalization is processed in blocks, the sequences are further divided into lengthFor data blocks of (2)Represent the firstLength of isInput of (a) a block vector;
s2, obtaining a plurality of frequency domain input block vectors by utilizing fast Fourier transform according to the plurality of data blocks;
In an exemplary embodiment, step S2 specifically includes obtaining a plurality of frequency domain input block vectors from the plurality of data blocks by using a fast fourier transform, as shown in the formula:
,
Wherein, Represent the firstThe block vectors are input in the frequency domain,The fast fourier transform is represented by a set of coefficients,;The representation transposes the matrix;
As an exemplary embodiment, in step S2, the data block is subjected to a Fast Fourier Transform (FFT) according to an overlap-and-hold method of 50% overlap, i.e., the frequency domain input block vector of the sub-equalizer (including the even sub-equalizer and the odd sub-equalizer) is represented as By using a 50% overlap factor, the input sequence includes L samples from the current data block and L samples from the previous data block;
S3, obtaining a frequency domain output block vector by utilizing a multi-input multi-output frequency domain equalizer according to the plurality of frequency domain input block vectors;
in an exemplary embodiment, step S3 specifically includes obtaining a frequency domain output block vector according to the plurality of frequency domain input block vectors by using a multiple input multiple output frequency domain equalizer, as shown in the formula:
,
,
Wherein, Is thatPolarization of firstThe number of time-domain output block vectors,Is thatPolarization of firstThe number of time-domain output block vectors,、、、、、、AndTap coefficients respectively representing eight sub-equalizer frequency domain filters in the multiple-input multiple-output frequency domain equalizer; Representing a dot product operation between the frequency domain vectors; 、、、 Representing the respective even and odd sequences AndPolarization of firstInputting block vectors in frequency domains;
As an exemplary embodiment, in step S3, the data block is correspondingly sent to a 2×2 butterfly Finite Impulse Response (FIR) filter to achieve frequency domain adaptive equalization, eight frequency domain filters are composed of even sub-equalizers and odd sub-equalizers, four even sub-equalizers in one 2×2 butterfly structure and four odd sub-equalizers in another 2×2 butterfly structure, and in the frequency domain, the output block vector is:
,
,
in step S3, L tap coefficient vectors of the sub-equalizer are used Filling with an equal number of 0 s and performing a 2L point FFT, the frequency domain tap coefficient vector of the sub-equalizer is expressed asWherein、Representation ofOr (b)The polarization of the light is changed,、Representing even sequences or odd sequences;
S4, carrying out inverse fast Fourier transform on the frequency domain output block vector, and discarding the preset number of elements to obtain a time domain output block vector;
As an exemplary embodiment, in step S4, an inverse FFT (IFFT) is performed and the pre-discard is performed Obtaining output block vector of time domain by each element、I.e. Inverse Fast Fourier Transform (IFFT) is performed on the frequency domain output block vector of the sub-equalizer and discardedFront partObtaining output block vector of time domain by each element;
S5, updating the tap weight of the filter by utilizing a phase correlation decision directed least mean square multiplication algorithm and a gradient descent algorithm according to the time domain output block vector;
in an exemplary embodiment, step S5 specifically includes:
S51, according to the time domain output block vector, utilizing a phase correlation decision directed least mean square multiplication algorithm to obtain an error vector;
in an exemplary embodiment, step S51 specifically includes obtaining an error vector according to the time domain output block vector by using a phase correlation decision directed least mean square multiplication algorithm, as the formula:
,
,
,
,
,
Wherein, As a vector of the error it is,Representation ofPolarizationRepresentative ofAndPolarization) the desired signal in training mode or the decoded signal in tracking mode; Representation of The tap coefficient vector of the polarization first stage phase estimator,Representation ofThe tap coefficient vector of the polarization second stage phase estimator,Representing an equalizerAn output block vector on polarization; Is the step size parameter, the sign Meaning that the conjugate vector is taken out of it,Is a tap coefficient vector controlling the first stage phase estimatorIs a signal of error of (a); Is a step-size parameter that is used to determine, Is a tap coefficient vector controlling the second stage phase estimatorIs a signal of error of (a);
s52, filling the error vectors by using a preset number of 0S, and obtaining frequency domain error vectors by using fast Fourier transform;
As an exemplary embodiment, in step S52, an equal number, i.e. 0 To fill in error vector and performPoint FFT (fast Fourier transform) to obtain frequency domain error vector,For representation0 Is filled;
S53, obtaining a gradient vector according to the frequency domain error vector and the plurality of frequency domain input block vectors;
as an exemplary embodiment, in step S53, a block vector is then input according to the frequency domain error vector Conjugation is taken and finally toPerforming inverse fast Fourier transform and discardingIs at the back of (1)Obtaining gradient vectors from each element;
S54, updating filter tap weights according to the gradient vector;
In an exemplary embodiment, step S54 specifically includes updating filter tap weights according to the gradient vector, as shown in the formula:
,
Wherein, For updated filter tap weights applied to the next data block,To update the pre-filter tap weights applied to the current data block,For a step size parameter of random gradient descent,As a vector of the gradient,For representation0 Is filled;
As an exemplary embodiment, in step S5, an error calculation is performed using a PD-DD-LMS algorithm in the time domain, the obtained error vector is converted into a frequency domain vector of length 2L after being complemented with L0S, and finally, filter tap weights are updated in the frequency domain by using a gradient descent algorithm.
In one embodiment, the frequency domain equalization method based on PD-DD-LMS architecture comprises the steps of inputting a sequence into a digital signal processing part at a signal receiving end、And respectively performing odd-even separation to obtain four odd/even sequences. Unlike time domain equalization, which uses sample-by-sample processing, frequency domain equalization uses block processing. Using a serial-to-parallel (S/P) converter, each leg is further divided into a number of L-point data blocks, L being equal to the discrete frequency response of the frequency domain equalizer, the data blocks are subjected to a Fast Fourier Transform (FFT) according to an overlap-preserving method of 50% overlap, after which the data blocks are correspondingly sent to a2 x 2 butterfly structure Finite Impulse Response (FIR) filter to achieve frequency domain adaptive equalization. Eight frequency domain filters consist of an even sub-equalizer and an odd sub-equalizer. Four even sub-equalizers are in one 2 x 2 butterfly structure and four odd sub-equalizers are in another 2 x 2 butterfly structure. In the frequency domain, the output block vector is:
,
,
Performing inverse FFT (IFFT) and discarding the first L elements to obtain an output block vector in the time domain 、And performing error calculation by adopting a PD-DD-LMS algorithm in a time domain, supplementing the obtained error vector with L0 s, converting the error vector into a frequency domain vector with the length of 2L, and finally updating filter tap weights in the frequency domain by using a gradient descent algorithm. FIG. 4 is a graph of the performance contrast simulation result of the time domain equalization provided by the invention, FIG. 5 is a graph of the performance contrast experiment result of the time domain equalization provided by the invention, and FIG. 6 is a graph of the computational complexity contrast of the time domain equalization provided by the invention;
It can be seen that the technical scheme of the invention can realize the same effect as time domain equalization after carrier phase estimation, but the computational complexity is greatly reduced.
In one embodiment, the frequency domain equalization method based on the PD-DD-LMS architecture may be implemented in the same manner as follows. FIG. 2 is a schematic diagram of the overall structure of an embodiment of the present invention, incorporating input sequences from x and y polarizationsThe division into odd and even sequences is further divided into data blocks of length L, since the frequency domain equalization is processed in blocksRepresenting the kth input block vector of length L.
The frequency domain input block vectors of the sub-equalizers (including even sub-equalizer and odd sub-equalizer) are expressed as:
,
By using a 50% overlap factor, the input sequence includes L samples from the current data block and L samples from the previous data block.
L tap coefficient vectors of sub equalizerFilling with an equal number of 0s and performing a 2L point FFT, the frequency domain tap coefficient vector of the sub-equalizer is expressed as:
,
Wherein p, q represent x or y polarization.
Inverse Fast Fourier Transform (IFFT) is performed on the frequency domain output block vector of the sub-equalizer and discardedThe first L elements obtain the output block vector of the time domain。
The tap coefficients of the sub-equalizer are updated in the frequency domain by using a gradient descent algorithm, and the expression is as follows:
,
Wherein the method comprises the steps of I.e. gradient vectors, are calculated by first calculating the error vector in the time domainFilling with an equal number of L0 s and performing 2L-point FFT to obtain:
,
Then input block vectors Conjugation is taken and finally toPerforming inverse fast Fourier transform and discardingIs obtained from the last L elements。
Error vectorThe method is obtained by calculating in a time domain by using a phase correlation decision directed least mean square multiplication algorithm (algorithm principle is shown in figure 3), and the expression is as follows:
,
Wherein the method comprises the steps of Representing the desired signal in the p-polarization (p representing x or y) training mode or the decoded signal in the tracking mode.Representing the tap coefficient vector of the p-polarized first-stage phase estimator,Representing the tap coefficient vector of the p-polarized second stage phase estimator,Representing the output block vector on the p-polarization of the equalizer.
The update expression of the tap coefficients of the first stage phase estimator is:
,
Is the step size parameter, the sign Meaning that the conjugate vector is taken out of it,Is a tap coefficient vector controlling the first stage phase estimatorThe expression of which is:
;
the update expression of the tap coefficients of the second-stage phase estimator is:
,
Is the step size parameter, the sign Meaning that the conjugate vector is taken out of it,Is a tap coefficient vector controlling the second stage phase estimatorThe expression of which is:
。
The present embodiment provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the frequency domain equalization method described above based on the PD-DD-LMS architecture. The storage medium may be a magnetic disk, an optical disc, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a Flash Memory (Flash Memory), a hard disk (HARD DISK DRIVE, HDD), or a Solid state disk (Solid-state-STATE DRIVE, SSD), and the like, and the storage medium may further include a combination of the above types of memories.
The present embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor implements the steps of the frequency domain equalization method based on the PD-DD-LMS architecture described above when the processor executes the program.
As shown in FIG. 7, the computer device 120 may include at least one processor 121, such as a central processing unit (Central Processing Unit, CPU), at least one communication interface 123, a memory 124, and at least one communication bus 122. Wherein the communication bus 122 is used to enable connected communication between these components. The communication interface 123 may include a Display screen (Display) and a Keyboard (Keyboard), and the optional communication interface 123 may further include a standard wired interface and a wireless interface. The memory 124 may be a high-speed random access memory (Random Access Memory, RAM) or a non-volatile memory (non-volatile memory), such as at least one disk memory. Memory 124 may also optionally be at least one storage device located remotely from the aforementioned processor 121. Wherein the memory 124 stores an application program and the processor 121 invokes the program code stored in the memory 124 for performing any of the method steps described above. The communication bus 122 may be a peripheral component interconnect (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. Communication bus 122 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one line is shown in fig. 7, but not only one bus or one type of bus. The memory 124 may include volatile memory (RAM), such as random-access memory (RAM), nonvolatile memory (non-volatile memory), such as flash memory (flash memory), hard disk (HARD DISK DRIVE, HDD) or solid state disk (solid-state drive-STATE DRIVE, SSD), and the memory 124 may include a combination of the above types of memory. The processor 121 may be a central processing unit (central processing unit, CPU), a network processor (network processor, NP) or a combination of CPU and NP, among others. The processor 121 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (programmable logic device, PLD), or a combination thereof. The PLD may be a complex programmable logic device (complex programmable logic device, CPLD), a field-programmable gate array (FPGA) GATE ARRAY, generic array logic (GENERIC ARRAY logic, GAL), or any combination thereof. Optionally, the memory 124 is also used for storing program instructions. The processor 121 may invoke program instructions to implement the frequency domain equalization method based on the PD-DD-LMS architecture as in the present embodiment.
The present embodiment provides a computer program product comprising a computer program which, when executed by a processor, implements the steps of the frequency domain equalization method based on the PD-DD-LMS architecture described above.
The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those having ordinary skill in the art without departing from the spirit of the present invention and the scope of the claims, which are to be protected by the present invention.
Claims (10)
1. The frequency domain equalization method based on the PD-DD-LMS architecture is characterized by comprising the following steps of:
s1, obtaining a plurality of data blocks by utilizing a parity separation and serial-parallel conversion method according to an input sequence;
s2, obtaining a plurality of frequency domain input block vectors by utilizing fast Fourier transform according to the plurality of data blocks;
S3, obtaining a frequency domain output block vector by utilizing a multi-input multi-output frequency domain equalizer according to the plurality of frequency domain input block vectors;
S4, carrying out inverse fast Fourier transform on the frequency domain output block vector, and discarding the preset number of elements to obtain a time domain output block vector;
and S5, updating the tap weight of the filter by utilizing a phase correlation decision directed least mean square multiplication algorithm and a gradient descent algorithm according to the time domain output block vector.
2. The frequency domain equalization method based on PD-DD-LMS architecture of claim 1, wherein step S1 specifically comprises:
S11, performing parity separation on the input sequence to obtain A polarization even sequence,An odd number of sequences,A polarization even sequence,An odd sequence of polarizations, said input sequence comprisingPolarized input sequenceA polarized input sequence;
s12, utilizing a serial-parallel conversion method to convert the data into a preset number Even-numbered sequences of polarizations, saidOdd polarization sequences, theEven-numbered sequences of polarizations, saidThe polarization odd sequences are divided into a plurality of data blocks, respectively.
3. The method for frequency domain equalization based on PD-DD-LMS architecture as set forth in claim 1, wherein step S2 specifically includes obtaining a plurality of frequency domain input block vectors by utilizing a fast Fourier transform according to the plurality of data blocks, as the formula:
,
Wherein, Represent the firstThe block vectors are input in the frequency domain,The fast fourier transform is represented by a set of coefficients,Represent the firstIn the data blockA sample number; the representation transposes the matrix.
4. The method for frequency domain equalization based on PD-DD-LMS architecture as set forth in claim 1, wherein step S3 specifically includes obtaining a frequency domain output block vector by utilizing a multiple-input multiple-output frequency domain equalizer according to the plurality of frequency domain input block vectors, as shown in the formula:
,
,
Wherein, Is thatPolarization of firstThe number of time-domain output block vectors,Is thatPolarization of firstThe number of time-domain output block vectors,、、、、、、AndTap coefficients respectively representing eight sub-equalizer frequency domain filters in the multiple-input multiple-output frequency domain equalizer; Representing a dot product operation between the frequency domain vectors; 、、、 Representing the respective even and odd sequences AndPolarization of firstThe block vectors are input in the frequency domain.
5. The frequency domain equalization method based on PD-DD-LMS architecture of claim 1, wherein step S5 specifically comprises:
S51, according to the time domain output block vector, utilizing a phase correlation decision directed least mean square multiplication algorithm to obtain an error vector;
s52, filling the error vectors by using a preset number of 0S, and obtaining frequency domain error vectors by using fast Fourier transform;
S53, obtaining a gradient vector according to the frequency domain error vector and the plurality of frequency domain input block vectors;
And S54, updating filter tap weights according to the gradient vector.
6. The method for frequency domain equalization based on PD-DD-LMS architecture as set forth in claim 5, wherein step S51 specifically includes obtaining an error vector from the time domain output block vector by using a phase correlation decision directed least mean square multiplication algorithm, as the formula:
,
,
,
,
,
Wherein, As a vector of the error it is,Representation ofPolarizationRepresentative ofAndPolarization) the desired signal in training mode or the decoded signal in tracking mode; Representation of The tap coefficient vector of the polarization first stage phase estimator,Representation ofThe tap coefficient vector of the polarization second stage phase estimator,Representing an equalizerAn output block vector on polarization; Is the step size parameter, the sign Meaning that the conjugate vector is taken out of it,Is a tap coefficient vector controlling the first stage phase estimatorIs a signal of error of (a); Is a step-size parameter that is used to determine, Is a tap coefficient vector controlling the second stage phase estimatorIs a function of the error signal.
7. The method of claim 5, wherein step S54 specifically comprises updating filter tap weights according to the gradient vector, as shown in the formula:
,
Wherein, For updated filter tap weights applied to the next data block,To update the pre-filter tap weights applied to the current data block,For a step size parameter of random gradient descent,As a vector of the gradient,For representationAnd 0 s are filled.
8. A computer readable storage medium having stored thereon a computer program, which when executed by a processor performs the steps of a frequency domain equalization method based on a PD-DD-LMS architecture according to any of claims 1-7.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the PD-DD-LMS architecture based frequency domain equalization method according to any of claims 1-7 when the computer program is executed.
10. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the frequency domain equalization method based on PD-DD-LMS architecture of any one of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510047146.XA CN119814166B (en) | 2025-01-13 | 2025-01-13 | Frequency domain equalization methods, media, and devices based on PD-DD-LMS architecture |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510047146.XA CN119814166B (en) | 2025-01-13 | 2025-01-13 | Frequency domain equalization methods, media, and devices based on PD-DD-LMS architecture |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN119814166A true CN119814166A (en) | 2025-04-11 |
| CN119814166B CN119814166B (en) | 2025-12-30 |
Family
ID=95278596
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202510047146.XA Active CN119814166B (en) | 2025-01-13 | 2025-01-13 | Frequency domain equalization methods, media, and devices based on PD-DD-LMS architecture |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN119814166B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070041116A1 (en) * | 2005-08-19 | 2007-02-22 | Sony Corporation | Tap coefficient determining method and apparatus, and digital signal phase locking method and apparatus |
| US20080028188A1 (en) * | 2006-07-25 | 2008-01-31 | Legend Silicon | Time de-interleaver implementation using sdram in a tds-ofdm receiver |
| US20080240273A1 (en) * | 2007-03-28 | 2008-10-02 | Koji Akita | Radio transmitting apparatus and radio receiving apparatus using ofdm |
| CN103763226A (en) * | 2014-01-06 | 2014-04-30 | 南京复实通讯科技有限公司 | Mixed time-frequency domain balancing method |
| CN106998229A (en) * | 2016-12-14 | 2017-08-01 | 吉林大学 | It is a kind of based on variable step without constraint FD LMS mode division multiplexing system Deplexing method |
| CN110830400A (en) * | 2018-08-13 | 2020-02-21 | 上海澜至半导体有限公司 | Decision feedback equalization processing device and method |
| US20210288859A1 (en) * | 2020-03-10 | 2021-09-16 | Ntwine, Llc | Bandwidth constrained communication systems with frequency domain information processing |
| CN114205204A (en) * | 2020-09-02 | 2022-03-18 | 中兴通讯股份有限公司 | Frequency domain generalized linear equalization method, device and system and nonvolatile storage medium |
| US20220321232A1 (en) * | 2019-12-20 | 2022-10-06 | Huawei Technologies Co., Ltd. | Frequency domain equalization method, equalizer, optical receiver, and system |
| CN115173952A (en) * | 2022-06-29 | 2022-10-11 | 苏州大学 | Optimized receiving method of optical general filtering multi-carrier optical access network |
| CN119210604A (en) * | 2024-09-26 | 2024-12-27 | 北京邮电大学 | A high-tolerance equalization method for carrier phase disturbance under fractional oversampling |
-
2025
- 2025-01-13 CN CN202510047146.XA patent/CN119814166B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070041116A1 (en) * | 2005-08-19 | 2007-02-22 | Sony Corporation | Tap coefficient determining method and apparatus, and digital signal phase locking method and apparatus |
| US20080028188A1 (en) * | 2006-07-25 | 2008-01-31 | Legend Silicon | Time de-interleaver implementation using sdram in a tds-ofdm receiver |
| US20080240273A1 (en) * | 2007-03-28 | 2008-10-02 | Koji Akita | Radio transmitting apparatus and radio receiving apparatus using ofdm |
| CN103763226A (en) * | 2014-01-06 | 2014-04-30 | 南京复实通讯科技有限公司 | Mixed time-frequency domain balancing method |
| CN106998229A (en) * | 2016-12-14 | 2017-08-01 | 吉林大学 | It is a kind of based on variable step without constraint FD LMS mode division multiplexing system Deplexing method |
| CN110830400A (en) * | 2018-08-13 | 2020-02-21 | 上海澜至半导体有限公司 | Decision feedback equalization processing device and method |
| US20220321232A1 (en) * | 2019-12-20 | 2022-10-06 | Huawei Technologies Co., Ltd. | Frequency domain equalization method, equalizer, optical receiver, and system |
| US20210288859A1 (en) * | 2020-03-10 | 2021-09-16 | Ntwine, Llc | Bandwidth constrained communication systems with frequency domain information processing |
| CN114205204A (en) * | 2020-09-02 | 2022-03-18 | 中兴通讯股份有限公司 | Frequency domain generalized linear equalization method, device and system and nonvolatile storage medium |
| CN115173952A (en) * | 2022-06-29 | 2022-10-11 | 苏州大学 | Optimized receiving method of optical general filtering multi-carrier optical access network |
| CN119210604A (en) * | 2024-09-26 | 2024-12-27 | 北京邮电大学 | A high-tolerance equalization method for carrier phase disturbance under fractional oversampling |
Non-Patent Citations (4)
| Title |
|---|
| DING, Q等人: "Parity-time symmetry in parameter space of polarization", 《APL PHOTONICS》, vol. 6, no. 7, 31 July 2021 (2021-07-31), XP012257948, DOI: 10.1063/5.0051064 * |
| 李响等人: "极端先验下的编码曝光运动目标模糊成像复原", 《小型微型计算机系统》, vol. 43, no. 6, 30 June 2022 (2022-06-30) * |
| 黄战华;王云立;李桂芳;张珊;: "少模光纤通信系统中的自适应频域均衡算法", 《激光技术》, no. 01, 25 January 2017 (2017-01-25) * |
| 黄战华;王云立;李桂芳;张珊;: "少模光纤通信系统中的自适应频域均衡算法", 激光技术, no. 01, 25 January 2017 (2017-01-25) * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN119814166B (en) | 2025-12-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Randel et al. | Complexity analysis of adaptive frequency-domain equalization for MIMO-SDM transmission | |
| JP6714095B2 (en) | Optical receiver, optical receiving method, and optical communication system | |
| CN102511136B (en) | Dispersion estimator and method for estimating dispersion | |
| CN108702221B (en) | Method for decoding optical signals and receiver for receiving and decoding optical signals | |
| WO2016107236A1 (en) | Self-adaptive equalization filtering apparatus and method in optical fibre communications, and storage medium | |
| Fougstedt et al. | ASIC design exploration for DSP and FEC of 400-Gbit/s coherent data-center interconnect receivers | |
| CN113271271A (en) | Step length adjusting method and device of adaptive equalizer, signal receiver and system | |
| CN103763228B (en) | Combination optimization self-adaptive frequency domain blind equalization method and system | |
| WO2011017852A1 (en) | Simulation device and simulation method | |
| JP2025513935A (en) | Learning-Based Nonlinear Compensation Using Physics-Information Neural Networks for Data Access | |
| CN119814166B (en) | Frequency domain equalization methods, media, and devices based on PD-DD-LMS architecture | |
| CN110266388B (en) | A PMD equalization method, device, electronic device and storage medium | |
| CN102884735A (en) | Method and apparatus for receiving optical burst signal, and optical burst signal receiver | |
| US7693233B2 (en) | Parallel Tomlinson-Harashima precoders | |
| CN119945855A (en) | Optimization method and device for adaptive equalizer of coherent optical communication system | |
| CN114205204A (en) | Frequency domain generalized linear equalization method, device and system and nonvolatile storage medium | |
| JP2004064681A (en) | Adaptive filter | |
| Berberdis et al. | Efficient block implementation of the LMS-based DFE | |
| CN115398827B (en) | Digital filter device for compensating group velocity dispersion in optical transmission system | |
| CN103346822B (en) | For the convertible equalizer of demodulator | |
| US20070014345A1 (en) | Low complexity Tomlinson-Harashima precoders | |
| CN107592194A (en) | Clock equalization methods, apparatus and system for QPSK systems | |
| JP7759008B2 (en) | Signal processing device and signal processing method | |
| CN113283592B (en) | Receiver-side equalization method and system based on low-complexity LSTM | |
| Perry et al. | An adaptive DFE for high data rate applications |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |