CN119814015A - An NMOS type high-side ideal diode based on differential amplifier - Google Patents

Abstract

The present invention relates to the field of diode technology, and in particular to an NMOS type high-end ideal diode based on a differential amplifier: the circuit is composed of an NMOS tube, a differential amplifier circuit, a voltage comparator, a bias power supply, etc.; the tube type in the differential amplifier circuit can be one of NPN, NMOS, PNP, and PMOS, and the differential amplifier circuit is used to compare the drain and source voltages of the NMOS tube, and the output signal is loaded into the voltage comparator again for amplification, and the voltage comparator outputs a signal to control the conduction and cutoff of the NMOS tube. The advantages are complemented by taking advantage of each other to achieve complementary advantages, and four high-end ideal diode circuits are designed. Software simulation verification shows that the designed circuit can realize the anti-backflow function, can meet the use of a wide current range, and protect the input power supply front-stage circuit. The circuit is simple, the cost is very low, and the practicability is strong.

Description

NMOS high-end ideal diode based on differential amplifier

Technical Field

The invention relates to the technical field of power diodes, in particular to an NMOS type high-end ideal diode based on a differential amplifier.

Background

The diode has unidirectional conduction characteristic and a backflow prevention function, so that the diode is increasingly applied, and particularly, the schottky diode has smaller voltage drop on a power supply connected in series, and is welcome by more designers. Because the voltage drop of the schottky diode is larger than that of the MOS transistor, for some voltage sensitive circuits, the MOS transistor with low impedance characteristic is more prone to be used, and the reliability of the product is improved.

At present, oring circuits are applied to a plurality of occasions, and the function is to ensure that all single power supplies are mutually independent and do not have the phenomenon of backflow, and are most commonly applied to current sharing circuits, so that different power requirements are met. Therefore, a low-loss high-end ideal diode and an ultralow-loss ideal diode are needed, so that the voltage drop is further reduced, the backflow prevention function is realized, the front-stage function is protected, the loss is reduced to the minimum, and the working time of the battery is prolonged.

The main technical scheme of the high-end ideal diode realized by the prior art is as follows.

The technical proposal of PMOS main pipe and PMOS auxiliary pipe (geminate transistor) is that the prior art patent (an ultralow-loss ideal diode, patent number: CN201821304820. X);

The NMOS main pipe and NMOS auxiliary pipe (pair pipe) technical scheme is that the NMOS main pipe is adopted to realize a high-end ideal diode, a circuit is composed of one NMOS main pipe, two NMOS auxiliary pipes, a bias power supply VBIAS and the like, and a load RL is positioned between the positive electrode of a power supply VCC and the NMOS main pipe;

The MOS main pipe and voltage comparator (operational amplifier) technical scheme is that the voltage comparator collects the voltage difference between the source electrode and the drain electrode of the MOS main pipe, and after comparison, an output signal controls the on and off of the MOS main pipe.

The differential amplifying circuit is evolved from an amplifying circuit with stable static working point, has different effects on different input signals, has a very strong inhibiting effect on common mode signals, has an amplifying effect on differential mode signals, has amplifying capability related to an output mode, and is widely used in circuits such as an audio amplifier, a voltage comparator, a data communication interface and the like.

The offset voltage, also known as the input offset voltage (Input Offset Voltage, abbreviated as VIO), reflects the degree of symmetry of the circuit, and is typically ±1 to 10mv. Overdrive voltage (Overdrive Voltage, abbreviated VOD) is the differential voltage generated between the positive and negative inputs of the voltage comparator on the offset Voltage (VIO), the absolute value of the voltage difference across the two input ports of the voltage comparator. To achieve accurate comparison, the overdrive Voltage (VOD) should be higher than the offset Voltage (VIO).

The input offset voltage (Input Offset Voltage, abbreviated as VIO) vio= ±0.37mV (typical value) of the voltage comparator chip LM393B of TI company, |vio|2.5 mV, and the input offset voltage (Input Offset Voltage) vio=3 mV (typical value) of the voltage comparator chip LMC7211AIM5, |vio|8 mV. When the voltage comparator is selected, the voltage comparator chip with lower offset voltage should be selected.

Because the voltage comparator works in a nonlinear region, the voltage comparator circuit is often connected into a hysteresis voltage comparator mode in an actual application circuit, so that the anti-interference capability of the circuit is enhanced. If the circuit has hysteresis characteristics, the return difference voltage is generally required to be larger than the offset voltage, namely DeltaV= |VT1-VT 2|is not less than VIO=2mV, which means that the conduction current ID of a drain-source channel through the MOS tube is greater than VIO/RD (ON) S.

When the NMOS tube is conducted, the drain-source channel resistance RDS (ON) is smaller, and if RDS (ON) =10mΩ, ID > VIO/RDS (ON) =2mV/10mΩ=0.2A, the voltage comparator can work normally only when the current is larger than 0.2A, and the NMOS tube is obviously suitable for the working occasion of large current.

The drain-source channel resistance RDS (ON) of the PMOS tube is larger, the RDS (ON) =100deg.M omega, ID > VIO/RDS (ON) =2mV/100deg.M omega=0.02A, which means that the voltage comparator with current larger than 0.02A can work normally, and the PMOS tube is obviously suitable for the working occasion with small current.

Then for the occasion that the working current is smaller than 0.2A, the solution is that the PMOS tube model with RDS (ON) more than 100mΩ can be selected to meet RDS (ON) x ID > VIO, namely RDS (ON) x ID > VIO/ID, and a current detection resistor R can be connected in series with the drain electrode or the source electrode of the original POS tube to meet (R+RDS (ON)) x ID > VIO, namely R > VIO/ID-RDS (ON).

The power type NMOS transistor is characterized in that a certain conduction resistance exists when the NMOS transistor or the PMOS transistor is conducted, for example, the conduction resistance of the power type NMOS transistor is about tens of milliohms and is lower than that of the PMOS transistor under the same condition, once the NMOS transistor is conducted, a conduction voltage drop (the product of the conduction current and the conduction resistance) is generated, the conduction voltage drop is the voltage difference between the drain electrode and the source electrode of the MOS transistor, the voltage difference is loaded to a double-input port of a differential amplifying circuit, the differential amplifying circuit is utilized to amplify signals (namely, the difference between the two signals), the two output ends output differential signals to be loaded to a voltage comparator (an identical-phase end and an opposite-phase end) again, and the conduction and the cut-off of a main pipe are controlled, so that the ideal diode function is realized.

According to the technical scheme, the characteristics of the differential amplifying circuit (the double input port and the double output port) and the hysteresis voltage comparator are combined, the complementary advantages are realized by taking advantage of the complementary advantages, and the novel high-end ideal diode device based on the differential amplifying technology is designed to meet the use occasion of a wide current range.

Disclosure of Invention

The invention aims to solve the technical problem of providing an NMOS type high-end ideal diode based on a differential amplifier based on the technical content.

In order to solve the technical problems, the technical scheme provided by the invention is that the NMOS type high-end ideal diode based on the differential amplifier comprises an NMOS main pipe V1, a differential amplifying circuit, a voltage comparator U1 and a bias power supply VBIAS;

The double input ports of the differential amplifying circuit are respectively connected with the drain electrode and the source electrode of the NMOS main pipe V1 and compare the voltage, the double input ends of the voltage comparator U1 receive output information of the differential amplifying circuit, and the output ends are connected to the grid electrode of the NMOS main pipe V1 to control the on or off of the NMOS main pipe V1.

Preferably, the differential amplifying circuit comprises a transistor pair tube and a peripheral circuit;

The transistor pair tube comprises any one of NPN pair tube, NMOS pair tube, PNP pair tube and PMOS pair tube.

Preferably, the transistor pair is NPN auxiliary transistors V2 and V3, and the peripheral circuit comprises resistors R1-R5, wherein the resistor R2=R3 and the resistor R4=R5;

the bases of the NPN auxiliary tubes V2 and V3 are used as double input ports of the differential amplifying circuit and are respectively connected to the source electrode and the drain electrode of the NMOS main tube V1 through resistors R4 and R5;

The collectors of the NPN auxiliary tubes V2 and V3 are used as double output ports of the differential amplifying circuit to be respectively connected with an inverting end and an non-inverting end of the voltage comparator, the collectors of the NPN auxiliary tubes V2 and V3 are respectively connected to a bias power supply VBIAS through resistors R2 and R3, and the emitters are mutually connected to the ground through a resistor R1.

Preferably, the transistor pair is NMOS auxiliary transistors V2 and V3, and the peripheral circuit comprises resistors R1-R5, wherein the resistor R2=R3 and the resistor R4=R5;

The grid electrodes of the NMOS auxiliary tubes V2 and V3 are used as double input ports of the differential amplifying circuit and are respectively connected to the source electrode and the drain electrode of the NMOS main tube V1 through resistors R4 and R5;

the drains of the NMOS auxiliary tubes V2 and V3 are used as double output ports of the differential amplifying circuit to be respectively connected with an inverting end and an non-inverting end of the voltage comparator, the drains of the NMOS auxiliary tubes V2 and V3 are respectively connected to a bias power supply VBIAS through resistors R2 and R3, and the sources are mutually connected to the ground through a resistor R1.

Preferably, the transistor pair is PNP auxiliary transistors V2 and V3, and the peripheral circuit includes resistors R1 to R5, where the resistor r2=r3 and the resistor r4=r5;

The bases of the PNP auxiliary tubes V2 and V3 are used as double input ports of the differential amplifying circuit and are respectively connected to the source electrode and the drain electrode of the NMOS main tube V1 through resistors R4 and R5;

the collectors of the PNP auxiliary tubes V2 and V3 are respectively connected to the inverting terminal and the non-inverting terminal of the voltage comparator as double output ports of the differential amplifying circuit and are grounded through resistors R2 and R3;

the emitters of the PNP auxiliary tubes V2 and V3 are connected to a bias power supply VBIAS through a resistor R1.

Preferably, the transistor pair is PMOS auxiliary transistors V2 and V3, and the peripheral circuit includes resistors R1 to R5, where resistor r2=r3 and resistor r4=r5;

the grid electrodes of the PMOS auxiliary tubes V2 and V3 are used as dual input ports of the differential amplifying circuit and are respectively connected to the source electrode and the drain electrode of the NMOS main tube V1 through resistors R4 and R5;

The drains of the PMOS auxiliary tubes V2 and V3 are used as double output ports of the differential amplifying circuit and are respectively connected to the inverting terminal and the non-inverting terminal of the voltage comparator and are grounded through resistors R2 and R3;

the sources of the PMOS auxiliary tubes V2 and V3 are connected to a bias power supply VBIAS through a resistor R1.

Compared with the prior art, the invention has the advantages that the characteristics of a differential amplifying circuit (double input ports and double output ports) and a hysteresis voltage comparator are combined, and the differential amplifier and the voltage comparator are used for double amplification in application, so that the differential amplifier and the voltage comparator are suitable for use occasions with wide current ranges. The circuit has the function of preventing backflow, can protect a front-stage circuit, has lower loss, small quiescent current loss, simple circuit, low cost and strong practicability.

Drawings

FIG. 1 is a schematic diagram of an NMOS (main pipe) high-end ideal diode implemented by an NPN pair-pipe differential amplifier;

FIG. 2 is a schematic diagram of an NMOS (main pipe) high-end ideal diode implemented by an NMOS pair-pipe differential amplifier;

FIG. 3 is a schematic diagram of an NMOS (main pipe) high-side ideal diode implemented by a PNP pair-pipe differential amplifier;

FIG. 4 is a schematic diagram of an NMOS (main pipe) high-end ideal diode implemented by a PMOS pair-pipe differential amplifier;

FIG. 5 is a forward conduction simulation of FIG. 1;

FIG. 6 is a reverse cut-off simulation of FIG. 1;

FIG. 7 is a forward conduction simulation of FIG. 2;

FIG. 8 is the reverse cut-off simulation of FIG. 2;

FIG. 9 is a forward conduction simulation of FIG. 3;

FIG. 10 is the reverse cut-off simulation of FIG. 3;

FIG. 11 is a forward conduction simulation of FIG. 4;

fig. 12 is the reverse cut-off simulation of fig. 4.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

Embodiment one

An NMOS type high-end ideal diode based on a differential amplifier is shown in fig. 1, and comprises an NMOS main pipe V1, a differential amplifier, a voltage comparator U1, a bias power supply VBIAS and the like. The differential amplifier is composed of NPN pair transistors V2 and V3, resistors R1-R5 and the like, and is a common emitter circuit, wherein R2=R3 and R4=R5. The two bases of NPN pair transistors V2 and V3 are used as dual input ports of a differential amplifier, source voltage and drain voltage of an NMOS main transistor V1 are detected respectively, the two collector potentials of the V2 tube and the V3 tube are used as dual output ports through the amplification action of the pair transistors V2 and V3 of the differential amplifier, differential signals U-, U+ are output respectively, the two collector potentials are connected with an inverting terminal and an in-phase terminal of a voltage comparator U1 respectively, and an output signal V1G of the voltage comparator U1 controls the on and off of the NMOS main transistor V1.

Differential amplifiers can overcome the problem of temperature drift. Under the action of the differential mode signal, the current change of the R1 is 0, namely the resistor R1 has no feedback action on the differential mode signal and is equivalent to short circuit, so that the amplifying capability of the differential mode signal is greatly improved, the circuit is simplified, and the power supply and the signal source are also in common ground. The differential amplifier is also called a differential amplifier, and the term "differential" means that an output voltage varies (amount of change) only when there is a difference (amount of change) in potential between the two input ports.

In general, a differential amplifier requires ideal symmetry of parameters, r2=r3 and r4=r5, and the input characteristic curves and the output characteristic curves of NPN pair transistors V2 and V3 are completely overlapped. Because of the dispersion of the transistor characteristics, the parameters of any component cannot be ideal symmetrical, namely zero drift cannot be completely restrained, but because adjacent components have good symmetry in an integrated circuit, the parameters are basically equal, and the ideal symmetry of the parameters can be generally approximately realized, NPN pair transistors V2 and V3 are preferably packaged together to ensure that the parameters of the two transistors are basically equal.

The specific working principle is as follows.

When the direct current power supply vcc=vcc 1 is powered on (forward conduction), the current output by VCC firstly passes through the body diode of the NMOS tube V1 (vout=vcc-V _F,V_F is diode conduction voltage drop), when the output current is gradually increased, the internal power supply VCC is higher than the external voltage, vout (VCC > Vout), voltage VA > VC, NPN tube V2 is conducted more thoroughly than NPN tube V3 (drain-source channel conduction impedance V2R _CE of V2 tube is smaller than drain-source channel conduction impedance V3R _CE of V3 tube, conduction degree depends on base voltage), meaning that the differential signal U-, u+ output by differential amplifier is transmitted to voltage comparator U1, voltage comparator U1 outputs high level, i.e. V1G is about VBIAS, when V1 _GS＝V1G-VCC＞V_TN(V_TN is NMOS tube conduction threshold voltage, drain-source channel conduction of NMOS tube V1, source current passes through source low impedance channel of NMOS tube V1 to load RL (no longer passes through body diode high impedance channel of NMOS tube V1), drain-source channel conduction impedance of NMOS tube V1 is smaller than drain channel conduction loss of VCC diode, power supply efficiency is reduced.

When the external voltage vout=vcc 2 is greater than the internal power supply VCC (Vout > VCC), the voltage VC > VA, the NPN tube V3 is turned on more thoroughly than the NPN tube V2 (the drain-source channel on-resistance V3R _CE of the V3 tube is smaller than the drain-source channel on-resistance V2R _CE of the V2 tube, the on-degree depends on the base voltage), that is, the voltage U- > u+, the differential signal U-, u+ output by the differential amplifier is transferred to the voltage comparator U1, the voltage comparator U1 outputs a low level, that is, v1g≡0V, when the drain-source channel of the V1 _GS＝V1G-VCC≈-VCC＜V_TN, the NMOS tube V1 is turned off, the power supply VCC is isolated from the external voltage Vout, and the current of the external power supply (other power supply connected in parallel with the voltage Vout) cannot flow backward into the power supply VCC, so as to achieve the purpose of protecting the power supply VCC 1.

Further, the voltage comparator has a hysteresis loop transmission characteristic (also called a schmitt trigger), and the threshold voltage of the voltage comparator is accelerated to change along with the change of the output voltage, so that the anti-interference capability is improved. The hysteresis voltage comparator has hysteresis characteristics, namely inertia, so that the hysteresis voltage comparator has certain anti-interference capability, and the stronger the anti-interference capability is, the worse the sensitivity is. The hysteresis voltage comparator circuit has two threshold voltages, the input voltage VCC enables the output voltage Vout to generate a threshold voltage VT1 of transition in the gradual increasing process, the input voltage VCC enables the output voltage Vout to generate a threshold voltage VT2 of transition in the gradual decreasing process, and the circuit has hysteresis characteristics. The same as the single-limit voltage comparator is that the output voltage Vout jumps only once when the input voltage changes in a single direction.

Further, the NMOS main pipe V1 may use NMOS pipes with different on-current magnitudes. For high-power supply control, the NMOS main pipe can select an on-resistance R _DS(ON) between a drain electrode and a source electrode to pass through a high-current power tube device, and the on-voltage drop is small when the high-current power tube passes through the high-current power tube device, namely the high-power NMOS main pipe has very low forward voltage, and can be similar to an ideal diode.

Second embodiment

The circuit is shown in fig. 2, and the circuit is basically the same as the first circuit in the embodiment, wherein the first differential amplifying circuit uses NPN pair transistors, the second embodiment uses NMOS pair transistors to replace NPN pair transistors V2 and V3, wherein resistance values of r2=r3, r4=r5, R2 and R4 are megaohm orders, and the circuit belongs to a common source circuit, and the specific working principle is basically the same as that of the first circuit in the embodiment, and detailed description of the first embodiment is omitted.

Embodiment III

An NMOS type high-end ideal diode based on a differential amplifier is shown in fig. 3, the circuit comprises an NMOS main pipe V1, a differential amplifier, a voltage comparator U1, a bias power supply VBIAS and the like, the differential amplifier comprises PNP pair pipes V2 and V3, resistors R1-R5 and the like, and the differential amplifier belongs to a common emitter circuit, wherein R2=R3 and R4=R5. The two bases of PNP pair pipe V2, V3 are used as dual input ports, detect the source electrode of NMOS person in charge V1, drain electrode voltage respectively, the amplification effect of PNP pair pipe V2, V3 through differential amplifier, two collectors of V2 pipe, V3 are used as dual output ports, output differential signal U-, U+ respectively connect voltage comparator U1's inverting terminal, homophase end, voltage comparator U1's output signal V1G controls the switching on and off of NMOS person in charge V1, specific theory of operation is as follows.

When the direct current power supply vcc=vcc 1 is powered on (forward conduction), the current output by VCC firstly passes through the body diode of the NMOS tube V1 (vout=vcc-V _F,V_F is diode conduction voltage drop), when the output current is gradually increased, the internal power supply VCC is higher than the external voltage, vout (VCC > Vout), i.e. voltage VA > VC, PNP tube V3 is conducted more thoroughly than PNP tube V2 (drain-source channel conduction impedance V3R _CE of V3 tube is smaller than drain-source channel conduction impedance V2R _CE of V2 tube, the conduction degree depends on the difference between bias power supply VBIAS and base voltage), meaning that the differential signal U-, u+ output by the differential amplifier is transmitted to the voltage comparator U1, the voltage comparator U1 outputs a high level, i.e. v1g≡vbias, when V1 _GS＝V1G-VCC＞V_TN, the drain-source channel of NMOS tube V1 is conducted, the current passes through the drain-source low impedance channel of NMOS tube V1 to load RL (no longer passes through the body diode high impedance channel of NMOS tube V1), the drain-source channel conduction efficiency is reduced than that of the drain-source channel impedance of NMOS tube V1, i.e. the power supply loss is reduced.

When the external voltage vout=vcc 2 is greater than the internal power supply VCC (Vout > VCC), the voltage VC > VA, the PNP transistor V2 is turned on more thoroughly than the PNP transistor V3 (the drain-source channel on-resistance V2R _CE of the V2 transistor is lower, the V3R _CE＞V2R_CE is turned on to a degree depending on the difference between the bias power supply VBIAS and the base voltage), that is, the voltage U- > u+, the differential signal U-, u+ output by the differential amplifier is transferred to the voltage comparator U1, the voltage comparator U1 outputs a low level, that is, v1g≡0V, when the drain-source channel of the NMOS transistor V1 is turned off, the power supply VCC is isolated from the external voltage Vout, and the current of the external power supply (other power supply connected in parallel with the voltage Vout) cannot flow backward into the power supply VCC, thereby achieving the purpose of protecting the power supply VCC 1.

Fourth embodiment

The circuit is shown in fig. 4, and basically the same as the third circuit in the embodiment, wherein the third differential amplifying circuit uses PNP pair tubes, the fourth embodiment uses PMOS pair tubes to replace PNP pair tubes, and the circuit belongs to a common source circuit, wherein the resistance values of R2=R3, R4=R5, and R2 and R4 are megaohm orders. The specific working principle is basically the same as that of the third embodiment, and detailed description of the third embodiment is omitted.

According to the circuit schematic diagrams shown in fig. 1-4, simulation software Multisim (version V14.0) of National Instruments is used for simulation test, the model selected by the voltage comparator is LMC7211AIM5, the rail-to-rail operational amplifier is used for realizing approximate full swing by push-pull amplification, the model selected by the PMOS tube is ON Semiconductor, the model is NVTFS5124PLTAG, the minimum value V _TP(MIN) = -1.5V and the maximum value V _TP(MAX) = -2.5V of the ON threshold voltage are adopted, the typical value V _TP is not given, the ON current can reach-6A, and the ON resistance R _DS(ON)＝0.26Ω(V_GS＝-10V)、R_DS(ON)＝0.38Ω(V_GS = -4.5V. The NMOS tube is selected from NXP company, the model is 2N7002E, the minimum value V _TN(MIN) =1V and the maximum value V _TN(MAX) =2.8V of the conducting voltage, the typical value V _TN is not given, the conducting current I _D is 10A/30V, the conducting impedance R _DS(ON)≤0.03Ω(V_GS＝10V)、R_DS(ON)≤0.05Ω(V_GS =4.5V, the NPN tube is selected from Generic company, the model is 2N2222A, the PNP tube is selected from Generic company, the model is 2N2905, and the load resistance RL=10Ω, and the specific simulation test is as follows.

Embodiment one simulation

The direct current power supply forward conduction simulation test comprises the steps of setting r1=r2=r3=10kΩ, r4=r5=100deg kΩ, vbias=20v, vcc=v1=12v (switch J1 is closed), and as shown in fig. 5, when in forward conduction, the output voltage Vout of the NMOS main tube V1 is about 12.0V, the base current of the NPN auxiliary tube V2 is 4.66 μa (detection point PR 6), the base voltage va=11.5V (PR 2, measured by a universal meter) and can be regarded as conducting the NPN auxiliary tube V2, the base current of the NPN auxiliary tube V3 is 4.42 μa (PR 8), the base voltage vc=11.5V (PR 1, measured by a universal meter) and can be regarded as conducting the NPN auxiliary tube V3, the NPN tube V2 is more thoroughly than the NPN tube V3, the output voltage u+ =14.7V (PR 10), the base current of the voltage comparator U- =14.5V (PR 9), namely, the voltage comparator u+ > U-, is high-level, namely, the base current of the NPN auxiliary tube V1=v20.6v=6v is 4.6v, the base current of the drain current of the NPN auxiliary tube V3 is regarded as conducting the drain current of the NMOS main tube V1=6kΩ=6v, and the drain current of the direct current source current of the direct current power supply is regarded as being about 328v.

After the switch J1 is closed, i.e., vout=vcc 2=12.1v, vout > VCC, voltage vc=11.6v (test point PR1, multimeter measured voltage 11.593V), va=11.6v (test point PR2, multimeter measured voltage 11.586V), U- =15. V, U + =14.1v, i.e., voltage U- > u+, NPN tube V3 is more thoroughly turned on than NPN tube V2, voltage comparator U1 outputs a low level, i.e., v1g≡4.76mv, v1 _GS＝V1G-VCC≈-12V＜V_TN, drain-source channel of NMOS tube V1 is turned off, as shown in fig. 6, power VCC1 outputs current 4.09 μa for bias of V2 tube, VCC2 outputs a reverse current (node VCC current: 4.09 μa-4.13 μa= -0.04 μa= -40 nA) to power VCC1, which can be considered as negligible, and VCC1 is protected from external voltage Vout 1 can be realized.

For the use occasions of different currents, the resistance value of the load resistor RL is changed, and the obtained simulation test results are shown in table 1.

Table 1 load current simulation test

From the load current simulation test in table 1, it can be seen that r1=r2=r3=r4=r5=10kΩ, the amplification factor of this group of parameters is better, load rl=12kΩ, load current is 1ma, conduction voltage drop v1 _SD = 21.933 μv of nmos main pipe V1 (corresponding conduction impedance R _DS(ON) = 21.933mΩ), the parameters according to the data manual are met, the difference between the amplified output u+ and U-is 1.198mV through the differential amplifier, the amplification factor of the differential amplifier is au=1.198 mV/21.933 μv= 54.62, and the amplification factor of the other two groups of parameters is less than 10 times. If the differential amplifier is used, the corresponding on current I _D = 0.1367A/54.62 =2.5mA, the theoretical on current is larger than 2.5mA, the offset voltage of the LMC7211AIM5 can be achieved, and the combined use response time of the differential amplifier and the voltage comparator is reduced along with the increase of the driving voltage.

Implementation two simulation

The DC power supply forward conduction simulation test comprises the steps of setting R1=R2=R3=10kΩ, R4=R5=100deg kΩ, VBIAS=20V, VCC=VC1=12V (switch J1 is closed), wherein the NMOS main pipe V1 outputs voltage Vout (12.0V), voltage VA (VC (12.0V) (measured by a universal meter: VA= 11.999V, VC = 11.973V), U+ =15.6V, U- =14.5V, namely U+ > U-, the voltage comparator U1 outputs high level, namely V1G=VBIAS=20.0V (PR 4), V1 _GS＝V1G-VCC≈20V-12V＝8V＞V_TN, the drain-source channel of the NMOS main pipe V1 is conducted, the conduction voltage drop is about 26.159mV (measured by the universal meter), the conduction voltage drop is lower than V _F =0.6V, the power supply positive electrode outputs current 1.20A, and the corresponding drain-source channel conduction impedance R _DS(ON) = 26.159/1.20A=21.8mΩ.

After the switch J1 is closed, namely vout=vcc 2=12.1v, vout > VCC, voltage va=12. V, VC =12.1v, u+ =13.2v, U- =16.9v, namely U- > u+, output low level of the voltage comparator U1, namely v1g=4.76 mV (PR 4), V1 _GS＝V1G-VCC≈-12V＜V_TN, drain-source channel of the NMOS main V1 is cut off, as shown in fig. 8, the output current of the power VCC1 is 0A, the VCC2 outputs a reverse current (node VCC current: 0A-1.38 na= -1.38 nA) to the power VCC1, which can be ignored, and the VCC1 can be considered isolated from the external voltage Vout, thereby achieving the purpose of protecting the power VCC 1.

Embodiment three simulation

The DC power supply forward conduction simulation test comprises the steps of setting R1=R2=R3=10kΩ, R4=R5=100deg kΩ, VBIAS=20V, VCC=VC1=12V (switch J1 is closed), wherein the output voltage Vout of the NMOS main tube V1 is about 12.0V, the voltage VA (VC=12.3V (measured by a multimeter: VA= 12.293V, VC =12.29V), U+ =3.66V, U- =3.39V, namely U+ > U-, the voltage comparator U1 outputs a high level, namely V1G=VBIAS=20.0V (PR 4), V1 _GS＝V1G-VCC≈20V-12V＝8V＞V_TN, the drain-source channel of the NMOS main tube V1 is conducted, the conduction voltage drop is about 26.159mV (measured by a multimeter), the conduction voltage drop V _F =0.6V of the diode is lower, the output current of the power supply positive electrode is 1.20 mV, and the corresponding drain-source channel conduction impedance R _DS(ON) = 26.159/1.20A=21.8mΩ.

After the switch J1 is closed, i.e. vout=vcc 2=12.1v, vout > VCC, voltage va=12.3v, vc=12.4v, u+=2.98v, U- =4.01V, i.e. U- > u+, output low level of the voltage comparator U1, i.e. v1g=4.76 mV (PR 4), V1 _GS＝V1G-VCC≈-12V＜V_TN, drain-source channel of the NMOS main V1 is cut off, as shown in fig. 10, the bias power supply VBIAS outputs bias current from 3.48 μa to the power supply VCC1, VCC2 outputs reverse current (node VCC current: 3.55 μa-3.48 μa= -0.07 μa= -70 nA) to the power supply VCC1, which is negligible, and the purpose of protecting the power supply VCC1 can be considered as isolating the power supply VCC1 from external voltage Vout.

Implementation four simulation

The DC power supply forward conduction simulation test comprises the steps of setting R1=R2=R3=10kΩ, R4=R5=100deg kΩ, VBIAS=20V, VCC=VC1=12V (switch J1 is closed), wherein the NMOS main pipe V1 outputs voltage Vout (about 12.0V) when in forward conduction, voltage VA (about 12.0V) (measured by a multimeter as VA= -99.992mV and VC= -2.42 mu V), U+ = 7.02V, U- = 1.05mV, namely U+ > U-, the voltage comparator U1 outputs high level, namely V1G=VBIAS=20.0V (PR 4), V1 _GS＝V1G-VCC≈20V-12V＝8V＞V_TN, drain-source channel conduction of the NMOS main pipe V1 is about 26.159mV, conduction voltage drop V _F =0.6V of a lower than that of a diode, power supply positive electrode output current 1.20A, and corresponding drain-source channel conduction resistance R _DS(ON) = 26.159/1.20A=21.8mΩ.

After the switch J1 is closed, namely vout=vcc 2=12.1v, vout > VCC, voltage va=12.0V, vc=12.1v, u+ =1.05 mV, U- =6.99V, namely U- > u+, output low level of the voltage comparator U1, namely v1g=4.76 mV (PR 4), V1 _GS＝V1G-VCC≈-12V＜V_TN, drain-source channel of the NMOS main pipe V1 is cut off, as shown in fig. 12, the output current of the power supply VCC1 is 0A, the VCC2 outputs a backward current (node VCC current: 0A-24 pa= -24 pA) to the power supply VCC1, which can be ignored, and the VCC1 can be considered isolated from the external voltage Vout, thereby realizing the purpose of protecting the power supply VCC 1.

The invention has the advantages that under the same condition, the main pipe of the high-end ideal diode is a PMOS pipe with the voltage drop of about 0.3V, and is suitable for occasions with smaller working current, while the main pipe is an NMOS pipe with the voltage drop of tens of millivolts, and is suitable for occasions with larger working current, and is suitable for use occasions with wide current range due to the double amplification of the differential amplifier and the voltage comparator. The circuit has the function of preventing backflow, can protect a front-stage circuit, has lower loss, small quiescent current loss, simple circuit, low cost and strong practicability.

The foregoing describes in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be made in accordance with the concepts of the invention by one of ordinary skill in the art without undue burden. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by the person skilled in the art according to the inventive concept shall be within the scope of protection defined by the claims.

Claims (6)

1. The NMOS high-end ideal diode based on the differential amplifier is characterized in that the circuit comprises an NMOS main pipe V1, a differential amplifying circuit, a voltage comparator U1 and a bias power supply VBIAS;

The double input ports of the differential amplifying circuit are respectively connected with the drain electrode and the source electrode of the NMOS main pipe V1 and compare the voltage, the double input ends of the voltage comparator U1 receive output information of the differential amplifying circuit, and the output ends are connected to the grid electrode of the NMOS main pipe V1 to control the on or off of the NMOS main pipe V1.

2. The NMOS high-side ideal diode based on differential amplifier as set forth in claim 1, wherein said differential amplifier circuit comprises a transistor pair and a peripheral circuit;

The transistor pair tube comprises any one of NPN pair tube, NMOS pair tube, PNP pair tube and PMOS pair tube.

3. The NMOS high-end ideal diode based on the differential amplifier as set forth in claim 2, wherein said transistor pair is NPN auxiliary transistors V2 and V3, and the peripheral circuit comprises resistors R1-R5, wherein the resistor R2=R3 and the resistor R4=R5;

the bases of the NPN auxiliary tubes V2 and V3 are used as double input ports of the differential amplifying circuit and are respectively connected to the source electrode and the drain electrode of the NMOS main tube V1 through resistors R4 and R5;

The collectors of the NPN auxiliary tubes V2 and V3 are used as double output ports of the differential amplifying circuit to be respectively connected with an inverting end and an non-inverting end of the voltage comparator, the collectors of the NPN auxiliary tubes V2 and V3 are respectively connected to a bias power supply VBIAS through resistors R2 and R3, and the emitters are mutually connected to the ground through a resistor R1.

4. The NMOS high-end ideal diode based on the differential amplifier as set forth in claim 2, wherein said transistor pair is NMOS auxiliary transistors V2 and V3, and the peripheral circuit comprises resistors R1-R5, wherein the resistor R2=R3 and the resistor R4=R5;

The grid electrodes of the NMOS auxiliary tubes V2 and V3 are used as double input ports of the differential amplifying circuit and are respectively connected to the source electrode and the drain electrode of the NMOS main tube V1 through resistors R4 and R5;

the drains of the NMOS auxiliary tubes V2 and V3 are used as double output ports of the differential amplifying circuit to be respectively connected with an inverting end and an non-inverting end of the voltage comparator, the drains of the NMOS auxiliary tubes V2 and V3 are respectively connected to a bias power supply VBIAS through resistors R2 and R3, and the sources are mutually connected to the ground through a resistor R1.

5. The NMOS high-end ideal diode based on the differential amplifier as set forth in claim 2, wherein said transistor pair is PNP auxiliary transistors V2 and V3, and the peripheral circuit comprises resistors R1-R5, wherein the resistor R2=R3 and the resistor R4=R5;

The bases of the PNP auxiliary tubes V2 and V3 are used as double input ports of the differential amplifying circuit and are respectively connected to the source electrode and the drain electrode of the NMOS main tube V1 through resistors R4 and R5;

the collectors of the PNP auxiliary tubes V2 and V3 are respectively connected to the inverting terminal and the non-inverting terminal of the voltage comparator as double output ports of the differential amplifying circuit and are grounded through resistors R2 and R3;

the emitters of the PNP auxiliary tubes V2 and V3 are connected to a bias power supply VBIAS through a resistor R1.

6. The NMOS high-end ideal diode based on the differential amplifier as set forth in claim 2, wherein said transistor pair is PMOS auxiliary transistors V2, V3, and the peripheral circuit comprises resistors R1-R5, wherein the resistor R2=R3 and the resistor R4=R5;

the grid electrodes of the PMOS auxiliary tubes V2 and V3 are used as dual input ports of the differential amplifying circuit and are respectively connected to the source electrode and the drain electrode of the NMOS main tube V1 through resistors R4 and R5;

The drains of the PMOS auxiliary tubes V2 and V3 are used as double output ports of the differential amplifying circuit and are respectively connected to the inverting terminal and the non-inverting terminal of the voltage comparator and are grounded through resistors R2 and R3;

the sources of the PMOS auxiliary tubes V2 and V3 are connected to a bias power supply VBIAS through a resistor R1.