CN119787816B

CN119787816B - Buck converter in COT mode

Info

Publication number: CN119787816B
Application number: CN202510287589.6A
Authority: CN
Inventors: 林友实; 甘戈
Original assignee: Yutai Semiconductor Co ltd
Current assignee: Yutai Semiconductor Co ltd
Priority date: 2025-03-12
Filing date: 2025-03-12
Publication date: 2025-06-27
Anticipated expiration: 2045-03-12
Also published as: CN119787816A

Abstract

The present invention provides a buck converter in COT mode, a main comparator, an on-time generation module and a PWM generation module, wherein the main comparator is used to compare a feedback voltage and a reference voltage, the on-time generation module is used to provide an on-time signal of the COT mode, and the PWM generation module is configured to: when the on-time signal changes from 0 to 1, determine whether the feedback voltage is less than the reference voltage; if the feedback voltage is less than the reference voltage, skip the off-time, so that the high-side power tube continues to be turned on, until the feedback voltage is greater than or equal to the reference voltage, and the high-side power tube of the buck converter is turned off. The buck converter in COT mode of the present invention uses the output voltage of the main comparator as a judgment standard to determine whether to reduce or skip the off-time, to extend the on-time of the high-side power tube, so that the output voltage obtains more power, which is more conducive to the scene that requires more power.

Description

Buck converter in COT mode

Technical Field

The present invention relates to a buck converter, and more particularly to a buck converter in a COT mode. The buck converter in the COT mode may be a conventional buck converter in the COT mode, or may be another type of buck converter in the COT mode, such as an ACOT (adaptive fixed on Time, adaptive Constant On-Time) buck converter.

Background

Fig. 1 shows the most basic example of a buck converter in the ACOT (adaptive fixed on-time) mode. The buck converter in the ACOT mode includes a main comparator Cp1, an on-time generating module T1, a PWM generating module P1 connected to both outputs, and a driver D1 connected to the output of the PWM generating module P1.

In the Buck converter in the ACOT mode, the output end of the driver D1 is connected to the gates of the high-side power transistor HS and the low-side power transistor LS of the Buck circuit (i.e., buck converter), so that the PWM generation module P1 amplifies the PWM signal by using the driver D1 to drive the large MOSFET. One input end of the main comparator Cp1 is connected with a feedback signal FB of the buck converter, and the other input end is connected with a reference voltage V _ref. The grid of the high-side power tube HS, the grid of the low-side power tube LS and an inductor are commonly connected to a switch node SW, and the other end of the inductor is the voltage output end of the buck converter. Thus, a portion of the inductor current IL acts as a capacitor current I _C flowing through the equivalent series resistance ESR and the output capacitor C _out of the buck converter, and another portion acts as an output current I _O (i.e., load current ILOAD) of the buck converter.

As shown in fig. 2, the feedback voltage FB can be divided into a voltage ripple of the equivalent series resistance ESR and a capacitor voltage ripple. The product of the capacitance current i _C and the equivalent series resistance ESR is the voltage across the equivalent series resistance ESR, so that the change of the voltage across the equivalent series resistance ESR is caused by the change of the capacitance current i _C, and the peak value of the voltage ripple of the ESR is the product of the difference between the maximum value and the minimum value of the capacitance current i _C and the equivalent series resistance ESR. The capacitive voltage ripple is a voltage ripple generated by a change in the internal charge of the capacitor, which is caused by a change in the capacitive current i _C.

The main comparator Cp1 compares the feedback voltage FB with the reference voltage V _ref, whenever the feedback voltage FB drops below the reference voltage V _ref, the output voltage Vea of the main comparator Cp1 will become high level, and since the output terminal of the main comparator Cp1 is connected to the Set terminal Set of the PWM generation module P1, the high level of the output voltage Vea of the main comparator Cp1 causes the high-side power transistor on signal HSON generated by the PWM generation module P1 to generate a turn-on pulse (i.e., hson=1) for driving the high-side power transistor HS to be turned on by the driver D1. The high side power transistor turn-on signal HSON is proportional to the switching node voltage VSW.

Meanwhile, since the PWM generating module generates the PWM signal and sends the PWM signal to the driver D1, and the PWM generating module is connected to a voltage controlled on-time generating module T1 to receive the on-time signal Ton, the on-time signal Ton becomes a high level at the end of the on-time, and thus, the on pulse (i.e., hson=1) drives the high-side power transistor HS to be turned on through the driver D1 until the on-time generating module T1 sends the high-level on-time signal Ton to reset the high-side power transistor on signal HSON, the high-side power transistor on signal HSON becomes 0, so that the high-side power transistor HS is turned off and the low-side power transistor is turned off.

The on-time generating module T1 is connected to the voltage input terminal of the buck converter to detect the input voltage VIN, so that a constant switching frequency is realized by the on-time being proportional to the input voltage VIN when the input voltage VIN changes. Similarly, the on-time generating module T1 needs to be connected to the voltage output terminal of the buck converter to detect the output voltage VOUT (also referred to as VOUT) of the buck converter, so as to realize a constant switching frequency by directly proportional to the output voltage VOUT when the output voltage VOUT reaches different voltage values.

As shown in fig. 2, when the feedback voltage FB just falls below the reference voltage V _ref, the high-side power transistor will immediately turn on, causing the ESR ripple and the capacitance ripple to rise again. Soon, the feedback voltage FB will be higher than the reference voltage V _ref again, so that the output voltage Vea of the main comparator Cp1 immediately becomes low level. Therefore, from the analysis of the buck converter in the conventional ACOT mode, the duty ratio of the output voltage Vea of the main comparator Cp1 is very small and the pulse shape thereof is a slim waveform at the time of the conventional operation in the COT mode. In fact, all the down-converters in the COT mode have relatively slim waveforms output by the error amplifier Vea during normal operation.

Fig. 3 and 4 show two operation scenarios in which the buck converter in the prior art ACOT mode is limited in operation, fig. 3 shows waveforms of the high-side power-transistor on signal HSON when the load step rises, and fig. 4 shows waveforms of the maximum duty cycle of the high-side power-transistor on signal HSON when the input voltage VIN steps down below the output voltage adjustment point. The output voltage adjustment point refers to a Direct Current (DC) value of the output voltage VOUT corresponding to the feedback voltage FB when the valley value of the feedback voltage FB is equal to the reference voltage Vref. And in practice, the average value vfb_average of the feedback voltage FB is equal to the sum of the reference voltage Vref and 1/2 of the feedback voltage ripple.

In the operating scenario shown in fig. 3, the feedback voltage FB is lower than the reference voltage Vref due to the load current ILOAD stepping up and being higher than the average value of the inductor current IL, which results in the output voltage VOUT falling below the output voltage regulation point. Subsequently, the output voltage Vea of the main comparator Cp1 is maintained at 1 for a relatively long time until the average value of the inductor current IL is higher than the load current ILOAD, at which time the ripple of the feedback voltage FB is again higher than the reference voltage Vref.

In the operation scenario shown in fig. 4, since the input voltage VIN is lower than the output voltage adjustment point, the maximum output voltage VOUT is equal to the input voltage vin×the maximum duty cycle of the high-side power transistor on signal HSON, and thus the maximum output voltage VOUT is also far lower than the output voltage adjustment point, the feedback voltage FB will always be lower than Vref. In this case, the output voltage Vea of the main comparator Cp1 is always equal to 1.

Although the two cases described above are different, there is a common point that the "output voltage Vea of the main comparator Cp1 is equal to 1" for a long time (temporary or permanent). Thus, the waveform of Vea is not a conventional slim waveform. Moreover, the output voltage Vea of the main comparator Cp1 is still equal to 1 even at the end of the on-period of the high-side power transistor on signal HSON, which is achieved by the on-time generating module T1 sending the on-signal Ton.

As shown in fig. 3, once the load changes from light to heavy, the load current ILOAD steps up so that the output voltage VOUT drops, the buck converter in the prior art ACOT mode will attempt to bring the inductor current to the present load level by turning on the high side fet.

However, if the step change in load is rapid and large, existing ACOT mode or COT mode buck converters may require multiple COT (fixed on time) cycles to ramp up inductor current. Each COT cycle is separated by at least a minimum OFF-TIME (Min OFF-TIME).

Obviously, a longer minimum off-time can adversely affect the COT load step response. In order to obtain a better load step response, it is necessary to reduce the minimum off-time or to temporarily skip the off-time according to certain criteria.

Disclosure of Invention

It is an object of the present invention to provide a buck converter in COT mode to increase the maximum duty cycle of the high side power transistor turn-on signal by extending the turn-on time and improve the fast load step response.

In order to achieve the above object, the present invention provides a buck converter in a COT mode, a main comparator, an on-time generating module and a PWM generating module, wherein the main comparator is used for comparing a feedback voltage with a reference voltage, the on-time generating module is used for providing an on-time signal of the COT mode, the PWM generating module is used for judging whether the feedback voltage is smaller than the reference voltage when the on-time signal is changed from 0 to 1, and if the feedback voltage is smaller than the reference voltage, the turn-off time is skipped, so that a high-side power tube is continuously turned on until the feedback voltage is larger than or equal to the reference voltage, and the high-side power tube of the buck converter is turned off.

The PWM generation module is further configured to turn off the high-side power tube when a timing time from the turn-on of the high-side power tube reaches a maximum turn-on time.

The PWM generation module receives the on-time signal and the extended on-time signal obtained by processing the output voltage of the main comparator, and uses the extended on-time signal as a reset signal of the on-signal of the high-side power tube, and the high-side power tube is turned off when the high-side power tube is reset.

The buck converter in the COT mode comprises a delay module connected with the conduction time signal, a conduction time expansion capacity detection module connected with the conduction time signal and the output voltage of the main comparator, and an AND gate, wherein two input ends of the AND gate are respectively connected with the conduction time delay signal output by the delay module and the conduction time expansion capacity detection signal output by the conduction time expansion capacity detection module, and the AND gate is used for outputting the expansion conduction time signal.

The delay module is configured to perform fixed delay on the on-time signal to obtain an on-time delay signal.

The fixed delay is 3ns-7ns.

The on-time expansion capability detection module is a D trigger, a clock end of the D trigger is connected with the on-time signal, a data port is connected with a high level, a reset end of the D trigger is connected with the output voltage of the main comparator, and an inverting output end of the D trigger outputs an on-time expansion detection signal.

The reset end of the conduction time expansion capability detection module is connected with an output signal of a NOR gate so as to be connected with an inverted signal of the output voltage of the main comparator and one of a maximum current indication signal and a maximum conduction time signal of the high-side power tube through the NOR gate.

The maximum current indication signal of the high-side power tube is changed from 0 to 1 when the current of the high-side power tube reaches the maximum protection current, the maximum conduction time signal is changed from 0 to 1 when the timing time from the conduction of the high-side power tube reaches the maximum conduction time, the output voltage of the main comparator is changed from 1 to 0 when the feedback voltage is larger than the reference voltage, and the conduction time expansion capability detection module resets when the output signal of the NOR gate is equal to 0, so that the conduction time expansion detection signal is changed to 1, and the high-side power tube of the buck converter is turned off.

The PWM generation module is further configured to enable the buck converter to enter a 100% duty cycle mode if the feedback voltage is less than the reference voltage when the maximum on-time is reached, with a continuous preset number of times, wherein the high-side power tube can be always turned on and turned off only when the feedback voltage is greater than or equal to the reference voltage or when the current of the high-side power tube reaches the maximum protection current.

The buck converter in the COT mode uses the output voltage of the main comparator as a judging standard to judge whether to reduce or skip the turn-off time, so as to prolong the turn-on time of the high-side power tube, and the output voltage can obtain more power, thereby being more beneficial to the scene requiring more power.

Drawings

Fig. 1 is a diagram showing the most basic example of a buck converter in the prior art ACOT (adaptive fixed on time) mode.

Fig. 2 is a waveform diagram of the buck converter in the prior art ACOT mode when in operation.

Fig. 3 and 4 are waveforms of the buck converter in the conventional ACOT mode in two operation scenarios, in which fig. 3 shows the waveform of the high-side power transistor turn-on signal when the load step rises, and fig. 4 shows the waveform of the maximum duty cycle of the high-side power transistor turn-on signal when the input voltage step falls below the output voltage adjustment point.

Fig. 5, 6A and 6B are graphs showing the waveforms of the prior art buck converter and the buck converter of the present invention using the output voltage of the main comparator at the end of the on-time of the high side power tube as the criterion for skipping the off-time, wherein fig. 5 shows the waveform when the load step rises, fig. 6A shows the waveform of the maximum duty cycle when the input voltage step falls below the output voltage adjustment point, and fig. 6B shows the waveform of the maximum duty cycle of the on-signal of the high side power tube when the input voltage step falls above the output voltage adjustment point.

Fig. 7 is a specific structural diagram of a buck converter in a COT mode according to one embodiment of the present invention.

Fig. 8 is a circuit diagram of a modified portion of the buck converter in the COT mode according to one embodiment of the present invention.

Fig. 9 is a schematic diagram of the generation of the second charging current.

Fig. 10 is a typical waveform diagram of a buck converter in the COT mode of the present invention.

Fig. 11 is a waveform diagram of a buck converter in the prior art ACOT mode in an analog scenario corresponding to a fast load jump situation.

Fig. 12 is a waveform diagram of the buck converter in the ACOT mode of the present invention in an analog scenario corresponding to a fast load jump situation.

Fig. 13 is a waveform comparison diagram of a buck converter in the present and inventive ACOT modes in an analog scenario corresponding to a maximum duty cycle limit.

Fig. 14 shows a partial magnified view of waveforms of the buck converter in the present and inventive ACOT mode in the maximum duty cycle limited analog scenario shown in fig. 13.

Fig. 15 is a graph of the actual load step response of the buck converter in the ACOT mode of the present invention.

Fig. 16A to 16D show oscillograms of the buck converter in the ACOT mode of the present invention in a scene of maximum duty cycle.

Detailed Description

The buck converter in the COT mode of the present invention is based mainly on the following principle:

A longer minimum off time may cause the output voltage to be under-powered in some scenarios, thereby adversely affecting the COT load step response. When the output voltage needs more power, the key idea is to prolong the on time of the high-side power tube HS. To obtain a better load step response, the output voltage may be made more power by reducing the minimum off time, or by temporarily skipping the off time according to certain criteria, further increasing the duty cycle of the high side power transistor on signal HSON.

In the invention, the output voltage Vea of the main comparator CP1 is used as a judging standard to judge whether to reduce or skip the turn-off time, so as to prolong the turn-on time of the high-side power tube and enable the output voltage to obtain more power.

As described above in detail, in normal operation, the output voltage Vea of the main comparator CP1 has a slim waveform and is equal to 1 only for a short time at the rising edge of the switching node SW. Therefore, the present invention can add a logic to detect the state of the output voltage Vea of the main comparator CP1 at the end of the on-time of the high-side power transistor HS. If the output voltage Vea of the main comparator CP1 is still equal to 1 at the end of the on-time of the high-side power transistor HS (i.e. the on-time signal Ton is changed from 0 to 1), this indicates that the integrated circuit is in an abnormal state, in which case the buck converter obviously requires more power. Therefore, in this case, the off-time will be skipped and the on-time will be continued until the output voltage Vea of the main comparator CP1 is zero or the timing time from the high-side power transistor on (i.e., HSON becomes 1) reaches the maximum on-time (i.e., the maximum on-time signal ton_max becomes 1 from 0).

Fig. 5, 6A and 6B show a comparison of waveforms of the prior art buck converter and the buck converter of the present invention using the output voltage Vea of the main comparator CP1 at the end of the on-time of the high-side power transistor HS as a criterion for skipping the off-time, wherein fig. 5 shows a waveform when the load step rises, fig. 6A shows a waveform of the maximum duty ratio when the input voltage VIN is stepped down below the output voltage adjustment point, and fig. 6B shows a waveform of the maximum duty ratio of the high-side power transistor on-signal HSON when the input voltage VIN is stepped down above the output voltage adjustment point. In fig. 5, 6A and 6B, in the present embodiment, the buck converter in the COT mode is specifically a buck converter in the ACOT mode, the waveform of the new buck converter is orange, and the waveforms of the new buck converter each further increase the duty cycle of the high-side power transistor on signal HSON.

As shown in fig. 5, in the case of the load step rising, if the output voltage Vea of the main comparator CP1 is still equal to 1 at the end of the on-time of the high-side power transistor HS (i.e., on-time signal ton=1), the off-time is skipped, as shown by the blue circle of fig. 5.

The limiting of the maximum duty cycle of the buck converter before and after modification can be described in connection with fig. 6A and 6B.

As shown in fig. 6A, when the input voltage VIN falls below the output voltage adjustment point, the output voltage VOUT corresponding to the input voltage VIN is lower than the target output voltage vout_settingand thus the output voltage VOUT is always lower than the output voltage adjustment point, in which case the duty cycle is discussed. At this time, the output voltage Vea of the main comparator is always at a high level.

In practice, the average value of the output voltage VOUT can only be reached:

VIN×max_duty = VIN×(T-min_off_time)/T,

wherein VIN is an input voltage, max_duty is a maximum duty ratio of a high-side power transistor turn-on signal, and T is a switching period.

For example, in the existing buck converter, if the minimum off time min_off_time=150 ns and the switching frequency is 600khz (i.e. the switching period t=1.667 μs), and the input voltage vin=the target output voltage vout_seting=5v, the maximum output voltage VOUT is equal to:

5×(1.667-0.15)/1.667 = 4.55V。

Therefore, in fig. 6A, in order to increase the output voltage, the conventional buck converter faces the same situation as the load step up shown in fig. 5, and it is necessary to decrease the minimum off time min_off_time or increase the On time On-time to increase the duty ratio. Whereas the existing buck converter in the ACOT mode does not support both methods.

In this embodiment, the buck converter in the ACOT mode is arranged to perform the following logic:

When the on-time of the high-side power tube HS is over (i.e., the on-time signal Ton is changed from 0 to 1), judging whether the output voltage Vea of the main comparator CP1 is 1, if the output voltage Vea of the main comparator is equal to 1 (i.e., the feedback voltage FB < the reference voltage Vref), skipping the off-time, so that the high-side power tube HS continues to be conducted until the output voltage Vea of the main comparator is zero or the timing time from the high-side power tube conduction (i.e., HSON is changed to 1) reaches the maximum on-time, and turning off the high-side power tube HS.

The same logic can also be applied to buck converters in the normal COT mode to improve the maximum duty cycle limit of the high-side power transistor turn-on signal HSON of the existing buck converter.

In other embodiments, the maximum on-time is not set. In the case where the buck converter performs the logic described above and the value of the input voltage VIN is insufficient to allow VOUT to reach the target output voltage vout_settingthe buck converter will always turn on the high-side power transistor HS if the maximum on time is not set. This is the operation of the buck converter in a mode where it is continuously conducting with a 100% duty cycle.

While a 100% duty cycle continuous conduction mode is possible, it is often necessary to provide other charge pump circuits or periodically briefly turn on the low-side power transistor LS to charge the bootstrap capacitor, or to set the high-side power transistor HS to a PMOS transistor to support continuous conduction of the high-side power transistor HS.

In this embodiment, the present invention adopts an NMOS transistor as the high-side power transistor, and a voltage 5V higher than the voltage of the switching node SW is required to drive this NMOS transistor. One common way to achieve this is to add an additional circuit called a bootstrap capacitor. The bootstrap capacitor is simply a capacitor, one terminal of which is connected to the drive circuit and is supplied by a 5V voltage source via a diode, and the other terminal is connected to the switching node SW. When the low side power tube LS is turned on, the bootstrap capacitor will be charged by the 5V voltage source. The buck converter of the present invention will drive the high-side power transistor HS with the energy stored by the bootstrap capacitor.

But in 100% duty cycle mode there is no time to recover energy for the bootstrap capacitor since the low side power tube LS is not conducting. Bootstrap capacitors gradually lose energy over time, and we need other circuits such as charge pump circuits to replenish this portion of the lost energy of the bootstrap capacitor. Therefore, if it is desired that the buck converter of the present invention is capable of operating in a 100% duty cycle continuous conduction mode with the NMOS transistor as the high side power transistor HS, a charge pump circuit is required at the power supply terminal of the capacitor to supplement the energy lost by the bootstrap capacitor.

In other embodiments, if the high-side power transistor HS is a PMOS transistor, the present invention does not require a new charge pump to support continuous turn-on of the high-side power transistor HS at 100% duty cycle. In addition, if the present invention allows the low-side power transistor LS to be turned on at the same time within the maximum on time ton_max after the high-side power transistor HS is turned on, a new charge pump is not required. Because, as previously described, the energy in the bootstrap capacitor is recovered after the low-side power transistor LS is turned on.

In the present embodiment, the maximum on time=30 μs. Since the maximum on-time is only 30 mus, the energy lost by the bootstrap capacitor during this period is practically negligible, so that a good output voltage can be maintained, thereby extending the duration of the battery. Moreover, each time the low-side FET is turned on, the energy is updated. Therefore, in the present embodiment, a new charge pump circuit is not required. At the same time, a maximum on-time of 30 μs causes the switching frequency to not produce audible noise.

In the present embodiment, the maximum on time=30 μs, and the minimum off time min_off_time=150 ns. When the high-side power tube on signal reaches the maximum duty ratio, the switching period T is the sum of the maximum on time and the minimum off time min_off_time, so the duty ratio is 99.5%. On the basis of 99.5% of duty cycle, the input voltage is 5V, so the output voltage can reach 4.975V. The output voltage of the buck converter is obviously improved compared with the calculation result of the output voltage of 4.55V of the existing buck converter.

As shown in fig. 6B, when the input voltage VIN decreases but still is above the output voltage adjustment point, the maximum value of the output voltage VOUT corresponding to the input voltage VIN is still slightly higher than the target output voltage vout_settingbut the average output voltage VOUT cannot reach the target output voltage vout_settingdue to the limitation of the COT mode, in which case the duty cycle is discussed.

For example, in the buck converter in the existing COT mode, under the condition that the input voltage vin=5.2V, the switching frequency is 600khz (i.e. the switching period t=1.667 μs), and the minimum off-time min_off_time is 150ns, the maximum output voltage VOUT is only equal to:

VOUT = (1.667-0.15)/1.667×5.2 = 4.73V

It is apparent that the input voltage VIN of 5.2V cannot support the 5V output in the existing buck converter in the COT mode.

In this embodiment, however, the buck converter in the COT mode is arranged to perform the following logic:

when the on-time of the high-side power tube HS is over (i.e., on-time signal ton=1), it is determined whether the output voltage Vea of the main comparator CP1 is 1, and if the output voltage Vea of the main comparator is equal to 1, the off-time will be skipped, so that the high-side power tube HS continues to be turned on until the output voltage Vea of the main comparator is zero or the timing time from the high-side power tube on (i.e., HSON becomes 1) reaches the maximum on-time. At this time, the high-side power transistor HS is turned off.

Therefore, in the present embodiment, the on-time is extended to VOUT/(VIN-VOUT) ×min_off_time=3.75 μs, but the maximum on-time (30 μs) has not yet been reached. Thus, in theory, the buck converter in the COT mode of the present invention is able to support a 5V output with a 5.2V input.

In the present embodiment, since the input voltage VIN is still high enough, the buck converter in the COT mode of the present invention can pull the feedback voltage FB above the reference voltage Vref. Then, the high-side power transistor on signal HSON is reset when the output voltage vea=0 of the main comparator CP 1. The on-time of the high-side power transistor HS depends on the length of time for which the output voltage vea=1 of the main comparator CP 1.

Thus, in practice, in this case shown in fig. 6B, the buck converter in the COT mode of the present invention will operate in an operation mode with a fixed off time (i.e. off time = minimum off time min_off-time) and a variable on time. The buck converter of the present invention transitions from a constant on-time mode to a constant off-time mode by executing the logic described above.

The specific structure of the buck converter in the COT mode according to one embodiment of the present invention is described below with reference to fig. 7 and 8. In the embodiment shown in fig. 7 and 8, the buck converter in the COT mode is a buck converter in the ACOT mode.

As shown in fig. 7 and 8, the buck converter in the COT mode of the present invention includes a main comparator Cp1, an on-time generating module T1, a PWM generating module P1, and a driver D1 connected to an output terminal of the PWM generating module P1.

The main comparator is configured to compare the feedback voltage FB with the reference voltage Vref and to make the output voltage Vea of the main comparator become a high level (vea=1) when the feedback voltage FB is smaller than the reference voltage Vref. The on-time generation module is used for providing an on-time signal TON of the COT mode.

The PWM generation module P1 is connected to the output voltage Vea of the main comparator Cp1 to use it as a 1-setting signal of the high-side power-transistor on signal HSON, and the high level of the output voltage Vea of the main comparator Cp1 makes the high-side power-transistor on signal HSON generated by the PWM generation module P1 become high level.

And the PWM generation module is used for judging whether the feedback voltage FB is smaller than the reference voltage Vref when the on-time signal Ton of the high-side power tube HS is changed from 0to 1, and if the feedback voltage FB is smaller than the reference voltage Vref, skipping off time to enable the high-side power tube HS to be continuously conducted until the feedback voltage FB is larger than or equal to the reference voltage Vref, and turning off the high-side power tube HS. Specifically, the PWM generation module P1 is connected to the on-time signal of the on-time generation module T1 and the extended on-time signal ton_ext processed by the output voltage Vea of the main comparator Cp 1to serve as a reset signal for the high-side power transistor on signal HSON, thereby realizing the above function.

Thus, the extended on-time signal ton_ext replaces the existing on-time signal TON that is a reset signal of the high-side power transistor on-signal HSON, and when the extended on-time signal ton_ext is at a high level (i.e., ton_ext=1), the reset of the high-side power transistor on-signal HSON is implemented to turn off the high-side power transistor HS.

One input end of the main comparator Cp1 is connected with the feedback signal FB of the buck converter, the other input end is connected with the reference voltage V _ref, and the output end is used for outputting the output voltage Vea of the main comparator Cp 1.

Since the buck converter in the COT mode is a buck converter in the ACOT mode, the on-time provided by the buck converter varies with the input voltage and the output voltage, the on-time generating module T1 includes a second comparator Cp2, the inverting input terminal of the second comparator Cp2 is connected to the voltage output terminal of the buck converter to receive the output voltage VOUT, the non-inverting input terminal of the second comparator Cp2 is simultaneously connected to the grounded first timing capacitor Cton, the grounded first grounding switch tube NM3, and the first charging current Iton, and the output terminal of the second comparator Cp2 is the output terminal of the on-time generating module T1 and is used for the on-time signal TON. When the on-time signal TON is 1, it indicates that the on-time of the high-side power transistor HS is completed, and the on-time can be provided.

The source electrode of the first grounding switch tube NM3 is grounded, the drain electrode is connected to the positive input end of the second comparator Cp2, the gate electrode is connected to the high-side power tube conducting signal HSON outputted by the PWM generation module P1 through the NOT gate NOT1, and the first grounding switch tube NM3 is turned on when the high-side power tube conducting signal hson=0 outputted by the PWM generation module P1, so that the first timing capacitor Cton cannot be charged, so that the conduction time generation module T1 starts to time from the time when the high-side power tube conducting signal hson=1, and therefore, the conduction time signal TON becomes 1 when the time from the time when the high-side power tube is turned on (i.e., HSON becomes 1) reaches the conduction time.

Since the inverting input terminal of the second comparator Cp2 is connected to the voltage output terminal of the buck converter to receive the output voltage VOUT, when the output voltage reaches different voltage values, a constant switching frequency is achieved by the on-time being proportional to the output voltage VOUT.

The first current source is for providing a first charging current Iton proportional to the input voltage VIN. In this embodiment, the first current source is a current output terminal of a first current mirror, where sources of all switching transistors of the first current mirror are connected to a voltage input terminal of the buck converter to receive the input voltage VIN, and the current output terminal of the first current mirror is connected to a non-inverting input terminal of the second comparator Cp2, which means that a current flowing into the first timing capacitor Cton is proportional to the input voltage VIN. Thus, the current of the current source into the first timing capacitor Cton is proportional to the input voltage VIN, and a constant switching frequency is achieved by the on-time being proportional to the input voltage VIN as the input voltage VIN changes.

In this embodiment, the first current mirror is a PMOS current mirror, which includes a first current mirror switching tube PM1 and a second current mirror switching tube PM2 with gates connected to each other, and sources connected to the input voltage VIN. The drain electrode of the first current mirror switch tube PM1 is connected with the grid electrode, and the drain electrode is grounded through a current mirror resistor Rvin and connected with the current output end of the second current mirror. Thus, the current mirror resistor Rvin can set the output current of the first current mirror, and the set output current is proportional to the input voltage VIN. The drain electrode of the second current mirror switch tube PM2 is a current output end of the first current mirror, and is used for providing a first charging current Iton.

The second current mirror is an NMOS current mirror, and includes a third current mirror switching transistor NM1 and a fourth current mirror switching transistor NM2, whose gates are connected to each other. The drain electrode of the third current mirror switching tube NM1 is connected with the grid electrode, and is connected with the input voltage VIN through a first resistor R1, and the source electrode of the third current mirror switching tube NM1 is grounded through a current mirror grounding switching tube PM3 in a diode connection mode. The drain electrode of the fourth current mirror switching tube NM2 is the current output end of the second current mirror, the source electrode is grounded through a second current mirror resistor Rvin, and the resistance value of the second current mirror resistor Rvin is the same as the resistance value of the current mirror resistor Rvin.

In the present embodiment, since the ratio of the first current mirror is 1x/1x, the first charging current Iton is a current flowing through the second current mirror switching tube PM2, which is equal to a current flowing through the first current mirror switching tube PM 1.

And the current flowing through the first current mirror switching tube PM1 is equal to the sum of the currents flowing into the current mirror resistor Rvin and the second current mirror resistor Rvin.

The current through the second current mirror resistor Rvin2 = voltage threshold of the current mirror ground switch tube PM 3/second current mirror resistor Rvin2 = VT _ PM3/Rvin,

The current flowing through the current mirror resistor Rvin = (input voltage VIN-voltage threshold of the first current mirror switching tube PM 1)/the current mirror resistor Rvin = (VIN-vt_pm1)/Rvin,

Therefore, the first charging current Iton is:

Iton=(VIN-VT_PM1)/Rvin+VT_PM3/Rvin,

Because the first current mirror switch tube PM1 and the current mirror ground switch tube PM3 are in the same process and are similar to each other, the voltage threshold vt_pm1 of the first current mirror switch tube approximates the voltage threshold vt_pm3 of the current mirror ground switch tube.

The first charging current Iton is:

Iton=(VIN-VT_PM1)/Rvin+VT_PM3/Rvin=VIN/Rvin+(VT_PM3-VT_PM2)/Rvin=VIN/Rvin

Thus, the first charging current Iton provided by the first current source is proportional to the input voltage VIN. The actual circuit implementing the first charging current Iton (i.e., the bias current proportional to the input voltage VIN) may be more complex.

The structure of the invention is consistent with the specific structure of the buck converter in the prior ACOT mode. Therefore, in the ACOT mode, the on-time generating module T1 sets the high-side power transistor on signal HSON to 1 according to the rising edge of the output signal Vea of the comparator, so that the high-side power transistor HS starts to be turned on, and resets the high-side power transistor on signal HSON according to the rising edge of the on-time signal TON to turn off the high-side power transistor HS.

The on-time generated by the on-time generating module T1 (as shown in the red box of fig. 8) is the time when the voltage in the first timing capacitor Cton reaches or exceeds the voltage of the inverting input terminal (i.e., the output voltage VOUT) of the second comparator Cp 2. From the basic equation for the charge stored in the capacitor, q=v×c=i×t, the on-time Ton of the buck converter can be found as:

Ton=V×C/I=VOUT×Cton/Iton,

the above-described pre-calculated first charging current Iton is equal to VIN/Rvin. Thus, the on-time Ton of the buck converter is obtained as:

Ton = VOUT×Cton/(VIN/Rvin) = (VOUT/VIN)×(Cton×Rvin)

Therefore, in the ACOT mode, the on-time signal TON is set to be proportional to both the output voltage VOUT and the input voltage VIN.

For a buck converter, we can also easily calculate its switching period or switching frequency when we know its on-time.

T (buck converter) =ton/D, where duty cycle d=vout/VIN

- > T (buck converter) =ton/(VOUT/VIN) = (VIN/VOUT) ×ton)

Substituting the on-time calculated in the above-mentioned ACOT mode into an equation will result in a switching period T (ACOT) of the buck converter in ACOT:

T(ACOT)=(VIN/VOUT)×Ton=(VIN/VOUT)×(VOUT/VIN)×(Cton×Rvin)=Cton×Rvin,

The end result of the switching cycle here does not include VIN, VOUT. It depends only on the preselected first timing capacitance Cton, the current mirror resistance Rvin. Therefore, we can say that in the ACOT mode, the switching frequency is constant regardless of the values of the input voltage VIN and the output voltage VOUT. This is the meaning of the letter "a" (Adaptive) in buck converters in ACOT mode.

As shown in fig. 8, the buck converter in the COT mode of the present invention is added with a delay module DL1, a conduction time expansion capability detection module DET1, AND an AND gate AND1 having two input terminals respectively connected to the conduction time delay signal ton_dl of the delay module DL1 AND the conduction time expansion capability detection signal nExt _ton of the conduction time expansion capability detection module DET1, based on the buck converter in the prior art COT mode. The extended on-time signal ton_ext outputted from the AND gate AND1 is used as a reset signal of the high-side power transistor on signal HSON. The extended on-time signal ton_ext replaces the existing on-time signal TON to be used as a reset signal of the high-side power tube on-signal HSON, and when the extended on-time signal ton_ext is at a high level (i.e., ton_ext=1), the reset of the high-side power tube on-signal HSON is realized to turn off the high-side power tube HS.

The delay module DL1 is an RC delay timer. The delay module DL1 is configured to perform a fixed delay on the on-time signal TON for 5ns, so as to obtain the on-time delay signal ton_dl, so as to make room for the detection circuit DET1 to operate. In practice, the increased delay may cause the on-time to slightly exceed the ratio of the output voltage VOUT/the input voltage VIN. But this effect is too small to be negligible.

The fixed delay of the delay module DL1 is in a time range equal to 5ns (±40%). This means that the delay time of the delay module DL1 will range between 3ns and 7 ns.

The on-time expansion capability detection module DET1 is a D flip-flop, the clock terminal CLK of which is connected to the on-time signal TON, the data port D is connected to a high level (5V), and the reset terminal R is connected to the output signal nEXT _rs of a NOR gate NOR to connect the maximum current indication signal IMAX of the high-side power transistor, the maximum on-time signal ton_max, and the inverted signal of the output voltage Vea of the main comparator through the NOR gate NOR. The inverting output terminal QB of the on-time expansion capability detection module DET1 outputs the on-time expansion detection signal nExt _ton.

In other embodiments, the high-side power tube maximum current indication signal IMAX and the maximum on-time signal ton_max may be omitted, and thus the reset terminal R may be directly connected to the output voltage Vea of the main comparator. Or one of the high-side power tube maximum current indication signal IMAX and the maximum on-time signal ton_max may be omitted, so that the reset terminal R is connected to the inverted signal of the output voltage Vea of the main comparator through the NOR gate NOR, and one of the high-side power tube maximum current indication signal IMAX and the maximum on-time signal ton_max.

The on-time expansion capability detection module DET1 is a conventional D flip-flop whose positive output terminal Q outputs a signal at the clock terminal CLK having a rising edge equal to the input of the data port D thereof, and resets to a default state when the signal at the reset terminal R is 0, i.e., the output of the positive output terminal Q becomes 0 and the output of the negative output terminal QB becomes 1. In this circuit, the on-time signal TON is an input clock of the on-time expansion capability detection module DET 1.

Since the output signal nEXT _rs of the NOR gate NOR is connected to the reset terminal R of the on-time expansion capability detection module DET1, when the output signal nEXT _rs of the NOR gate NOR received by the reset terminal R of the on-time expansion capability detection module DET1 is equal to 0, the on-time expansion capability detection module DET1 is reset to a default state and the on-time expansion detection signal nExt _ton output by the inverting output terminal thereof becomes 1.

In this embodiment, three input terminals of the NOR gate NOR are respectively connected to the maximum current indication signal IMAX of the high-side power transistor, the maximum on-time signal ton_max, and the inverted signal of the output voltage Vea of the main comparator.

The maximum current indication signal IMAX of the high-side power tube is changed from 0 to 1 when the current of the high-side power tube reaches the maximum protection current. The maximum on-time signal ton_max changes from 0 to 1 when the timing from when the high-side power transistor turns on (i.e., HSON changes to 1) reaches the maximum on-time. The output voltage Vea of the main comparator changes from 1 to 0 when the feedback voltage FB is greater than the reference voltage Vref.

Thus, the on-time expansion capability detection module DET1 resets when the output signal nEXT _rs of the NOR gate NOR is equal to 0 (i.e., the output voltage vea=0 or ton_max=1 or imax=1 of the comparator), so that the on-time expansion detection signal nExt _ton output from the inverting output terminal thereof becomes 1, and the high-side power transistor HS of the buck converter is turned off. If none of the above three conditions exist, the on-time expansion capability detection module DET1 latches the result of the high level at the rising edge of the on-time signal TON, so that the on-time expansion detection signal nExt _ton output from the inverting output terminal thereof becomes 0 (i.e., 0V) within less than 1ns after the on-time signal ton=1. During the period when the change of the on-time extension detection signal nExt _ton is incomplete, the on-time delay signal ton_dl is still equal to 0 because the delay time of the on-time delay signal ton_dl with respect to the on-time signal TON is 5ns.

Therefore, at the rising edge of the on-time signal TON, if the output voltage vea=1 of the main comparator (when the high-side power transistor HS is just turned on, ton_max=0 and imax=0 are necessarily satisfied), the on-time extension detection signal nExt _ton=0 will block the output of the on-time delay signal ton_dl and keep the extension on-time signal ton_ext equal to zero (0V) so that the high-side power transistor HS continues to be turned on, until one of the following three conditions (vea=0, ton_max=1, imax=1) occurs, the extension on-time signal ton_ext becomes 1 so that the high-side power transistor HS is turned off.

Therefore, the present invention successfully converts the constant on-time mode into the constant off-time mode by the simple circuit composed of the delay block DL1, the on-time expansion capability detection block DET1, AND the AND gate AND1 described above.

The high-side power tube maximum current indication signal IMAX is the output of the high-side power tube maximum current protection circuit. When the high-side power tube HS is conducted, the current sensing circuit senses the current passing through the high-side power tube HS and changes the maximum current indication signal IMAX of the high-side power tube from 0 to 1 when the current reaches the maximum protection current so as to turn off the high-side power tube HS. This is to ensure that the high-side power tube HS operates in a current safe operating region.

The maximum time generation module is a timer, and is configured to generate a maximum on-time signal ton_max, where the maximum on-time signal ton_max is changed from 0 to 1 when a timing time from when the high-side power transistor is turned on (i.e., HSON is changed to 1) reaches the maximum on-time.

The maximum time generation module includes a third comparator Cp3, where an inverting input end of the third comparator Cp3 is connected to a third comparator reference voltage (1.2V), and a non-inverting input end is simultaneously connected to a grounded second timing capacitor Ctmax, a grounded second grounding switch tube NM4, and a second charging current Itmax. Thus, the maximum on-time signal ton_max provides the maximum on-time by charging the second timing capacitor Ctmax with the second charging current Itmax until the voltage of the second timing capacitor Ctmax reaches the third comparator reference voltage (1.2V), which is very accurate.

The maximum on-time is in the range of 30 mus (+ -15%), which means that it will be in the range of 25.5 mus to 34.5 mus. The second charging current Itmax is a constant current and is generated by a simple bias current circuit. Specifically, as shown in fig. 9, the second charging current Itmax is a mirror current of the base bias current, the base bias circuit includes a buffer B1 for generating the base bias current and a third current mirror having a current input terminal connected to the base bias current, and an output terminal of the third current mirror is for outputting the second charging current Itmax. The non-inverting input end of the buffer B1 is connected with the buffer input voltage (1.2V), the inverting input end of the buffer B1 is connected with the third current mirror resistor R3 and is connected with the source electrode of the fifth switching tube NM5, the output end of the buffer B1 is connected with the grid electrode of the fifth switching tube NM5, and the source electrode of the fifth switching tube NM5 is connected with the current input end of the third current mirror and generates base bias current. Thus, the base bias current generated by buffer B1 is equal to 1.2V/R3. The third current mirror resistor R3 has a trimming network to trim the maximum time generation module during mass production.

Typical waveforms of the buck converter in the COT mode of the present invention are shown in fig. 10. In fig. 10, the input voltage VIN of about 5.75V is quite low for a target output voltage of 5.5V. On the rising edge of the on-time signal TON, we can see that the output voltage vea=1 of the main comparator (i.e. the feedback voltage FB < the reference voltage Vref). Accordingly, the on-time expansion capability detection block DET1 detects the Vea state and sets the on-time expansion detection signal nExt _ton=0 in a time of about 1 ns.

The on-time delay signal ton_dl represents a signal delayed by 5.5ns from the on-time signal TON. The extended on-time signal ton_ext is an AND function of the on-time delay signal ton_dl AND the on-time extension detection signal nExt _ton. The extended on-time signal ton_ext remains at 0 until the feedback voltage FB is higher than VREF (i.e., the output voltage vea=0 of the main comparator) to reset the on-time extended capability detection module DET1 and to reset the high-side power transistor on signal HSON. The on-time is extended from 1.3565 mus to 5.064 mus to increase the maximum duty cycle.

Fig. 11 and 12 show waveforms of the buck converter in the present and inventive ACOT mode in an analog scenario corresponding to a fast load jump situation (load current at 1 mus from 0- > 8A).

Fig. 11 shows that vin=12v, vout=5.5v, load current steps 0- > 8A, taking 1 μs, and the output voltage undershoot of the buck converter in the prior art ACOT mode is 344.5mV.

Fig. 12 shows that vin=12v, vout=5.5v, load stepping 0- > 8A, taking 1 μs, the output voltage drops down to 283mV using the buck converter in the ACOT mode of the present invention.

Fig. 13 shows a waveform comparison diagram of the buck converter in the present and inventive ACOT modes in an analog scenario corresponding to the maximum duty cycle limit.

Fig. 13 shows a comparison of the maximum duty cycle simulation results of a prior art buck converter in the ACOT mode of the present invention. Where the output voltage vout=5.54V, the load current iload=2a, and the input voltage VIN drops from 6.25V to 5.5V.

The blue waveform is the waveform of the buck converter (output voltage VOUT, switch node voltage VSW, inductor current IL) in the ACOT mode of the present invention. The pink waveform is the waveform of the buck converter (output voltage VOUT, switching node voltage VSW, inductor current IL) in the existing ACOT mode. In the simulation, the output voltage VOUT of the existing circuit starts to drop when the input voltage vin=6v. In the circuit of the present invention, when vin=5.48V, the on-time of the switch node SW is scalable, and the output voltage VOUT is still close to 5.42V (maximum duty cycle to 99%).

Fig. 14 shows a partial magnified view of waveforms of the buck converter in the present and inventive ACOT mode in the maximum duty cycle limited analog scenario shown in fig. 13. Fig. 14 shows the maximum duty cycle of the circuit of the present invention extended with respect to the existing circuit for 2 periods. In period 1, vin is still high enough to support the output, and the on-time of the integrated circuit is determined by the output voltage Vea of the main comparator. In period 2, the input voltage VIN is low and if the maximum on-time is set, the overall circuit on-time of the present invention is limited by the maximum on-time signal ton_max.

The blue waveform is the waveform (1-output voltage VOUT, 3-switch node voltage VSW, 4-inductor current IL) of the COT-mode buck converter of the present invention. The pink waveform is the waveform of the existing COT mode circuit (2-output voltage VOUT, 5-inductor current IL, 6-switch node voltage VSW). As can be easily seen in the partial amplification, in the circuit of the invention the on-time is continuously extended during "period 1" while the input voltage VIN is reduced. The on-time is reset only when the output voltage Vea of the main comparator is zero or the on-time reaches a maximum on-time. In "period 2", the on-time of the integrated circuit is limited by the maximum on-time. As previously mentioned, if the maximum on-time is not set (is infinite), the circuit of the present invention can enter a 100% duty cycle mode of operation such that the simulation result depends only on the relationship between the input voltage VIN, the output voltage VOUT and the load. But if the on-time is too long, other charge pump circuits are needed to maintain the supply of the high-side power transistor HS. Furthermore, another purpose of setting the maximum on-time is not to allow the integrated circuit to switch at audible frequencies. If a 100% duty cycle is desired, additional logic may be added to cause the circuit of the present invention to jump to a 100% duty cycle mode. For example, the PWM generation module may be configured such that if the feedback voltage FB is less than the reference voltage Vref (i.e., the output voltage vea=1 of the main comparator) when the maximum on-time is reached a predetermined number of times (e.g., 8 times), the voltage down converter in the COT mode of the present invention may be caused to jump to the 100% duty cycle mode, wherein the high-side power transistor can always be turned on and be turned off only when the feedback voltage (FB) is greater than or equal to the reference voltage (Vref) or when the current of the high-side power transistor reaches the maximum protection current, without any more depending on the maximum on-time.

Fig. 15 shows the experimental results of a silicon wafer, i.e. the actual load step response diagram of the buck converter in the ACOT mode of the present invention on a silicon wafer. As shown in fig. 15, the on-time of the high-side power transistor is enlarged as expected, the blue signal in the figure indicates the input voltage VIN, the yellow signal indicates the switch node voltage SW (the waveform of which is consistent with the high-side power transistor on-signal HSON), and the red signal indicates the load current ILOAD.

Fig. 16A to 16D show oscillograms of the buck converter in the ACOT mode of the present invention in a scene of maximum duty cycle, in which the input voltage VIN scans upward from 20V and the output voltage VOUT is set=20v. When the input voltage VIN is low, the on-time represented by the switch node SW is prolonged.

The foregoing description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and various modifications can be made to the above-described embodiment of the present invention. All simple, equivalent changes and modifications made in accordance with the claims and the specification of the present application fall within the scope of the patent claims. The present invention is not described in detail in the conventional art.

Claims

1. The buck converter in the COT mode is characterized by comprising a main comparator (Cp 1), a conduction time generation module for providing a conduction time signal (TON) of the COT mode, a delay module (DL 1), a conduction time expansion capability detection module (DET 1), an AND gate (AND 1) AND a PWM generation module (P1), wherein the main comparator (Cp 1) is used for comparing a feedback voltage (FB) AND a reference voltage (Vref), two input ends of the AND gate (AND 1) are respectively connected with a conduction time delay signal (TON_DL) AND a conduction time expansion detection signal (nExt _TON), AND the AND gate (AND 1) outputs an expansion conduction time signal (TON_EXT);

The delay module (DL 1) carries out fixed delay on the on-time signal (TON) to obtain the on-time delay signal (TON_DL), the on-time expansion capacity detection module (DET 1) is a D trigger, a clock end (CLK) of the D trigger is connected with the on-time signal (TON), a data port (D) is connected with a high level, a reset end (R) is connected with the output voltage (Vea) of the main comparator, and an inverted output end (QB) outputs the on-time expansion detection signal (nExt _TON);

the PWM generation module (P1) is configured to receive the extended on-time signal (TON_EXT) as a signal for turning off the high-side power tube (HS);

when the on-time signal (TON) is changed from 0 to 1, judging whether the feedback voltage (FB) is smaller than the reference voltage (Vref), if the feedback voltage (FB) is smaller than the reference voltage (Vref), skipping the off-time, so that the high-side power tube (HS) is continuously turned on until the feedback voltage (FB) is larger than or equal to the reference voltage (Vref), and turning off the high-side power tube (HS) of the buck converter at the moment.

2. The buck converter in the COT mode according to claim 1, wherein the PWM generation module (P1) is further configured to turn off the high-side power tube (HS) when a timing time from the high-side power tube on reaches a maximum on time.

3. The buck converter in the COT mode according to claim 1, wherein the fixed delay is 3ns-7ns.

4. The buck converter in the COT mode according to claim 1, wherein the output voltage (Vea) of the main comparator changes from 1 to 0 when the feedback voltage (FB) is greater than the reference voltage (Vref).

5. The buck converter in the COT mode according to claim 2, wherein the PWM generation module (P1) is further configured to cause the buck converter to enter a 100% duty cycle mode if the feedback voltage (FB) is less than the reference voltage (Vref) when the maximum on-time is reached, with a continuous preset number of times, wherein the high-side power tube is capable of always being turned on and is turned off only when the feedback voltage (FB) is greater than or equal to the reference voltage (Vref) or when the current of the high-side power tube reaches the maximum protection current.

6. A buck converter in the COT mode, comprising a main comparator (Cp 1), an on-time generating module for providing an on-time signal (TON) of the COT mode, a delay module (DL 1), an on-time expansion capability detecting module (DET 1), an AND gate (AND 1), AND a PWM generating module (P1), the main comparator (Cp 1) being configured to compare a feedback voltage (FB) with a reference voltage (Vref), two inputs of the AND gate (AND 1) being connected to an on-time delay signal (ton_dl) AND an on-time expansion detecting signal (nExt _ton), respectively, the AND gate (AND 1) outputting an expanded on-time signal (ton_ext);

the delay module (DL 1) carries out fixed delay on the on-time signal (TON) to obtain the on-time delay signal (TON_DL), the on-time expansion capacity detection module (DET 1) is a D trigger, a clock end (CLK) of the D trigger is connected with the on-time signal (TON), a data port (D) is connected with a high level, an inverted output end (QB) outputs the on-time expansion detection signal (nExt _TON), a reset end (R) is connected with an output signal (nEXT _RS) of a NOR gate (NOR) so as to be connected with an inverted signal of an output voltage (Vea) of a main comparator through the NOR gate (NOR), and a maximum current indication signal (IMAX) of a high-side power tube and a maximum on-time signal (TON_MAX);

7. The buck converter in the COT mode according to claim 6, wherein the high-side power tube maximum current indication signal (IMAX) changes from 0 to 1 when the current of the high-side power tube reaches a maximum protection current, the maximum on-time signal (ton_max) changes from 0 to 1 when a timing time from the high-side power tube on reaches a maximum on-time, the output voltage (Vea) of the main comparator changes from 1 to 0 when the feedback voltage (FB) is greater than the reference voltage (Vref);

The on-time expansion capability detection module (DET 1) resets when the output signal (nEXT _RS) of the NOR gate (NOR) is equal to 0, so that the on-time expansion detection signal (nExt _TON) becomes 1, and further the high-side power transistor (HS) of the buck converter is turned off.

8. The buck converter in the COT mode according to claim 6, wherein the PWM generation module (P1) is further configured to turn off the high-side power tube (HS) when a timing time from when the high-side power tube is turned on reaches a maximum on-time.

9. The buck converter in the COT mode according to claim 8, wherein the PWM generation module (P1) is further configured to cause the buck converter to enter a 100% duty cycle mode if the feedback voltage (FB) is less than the reference voltage (Vref) when the maximum on-time is reached, with the feedback voltage (FB) being permanently on and only turned off when the feedback voltage (FB) is greater than or equal to the reference voltage (Vref) or when the current of the high side power tube reaches the maximum protection current, for a continuous preset number of times.

10. The buck converter in the COT mode according to claim 6, wherein the fixed delay is 3ns-7ns.