CN119727383A

CN119727383A - Control circuit and control method for DC/DC converter

Info

Publication number: CN119727383A
Application number: CN202311279724.XA
Authority: CN
Inventors: 徐春华; 刘志国; 周志辉
Original assignee: Beijing Dashun Technology Co ltd
Current assignee: Beijing Dashun Technology Co ltd
Priority date: 2023-09-28
Filing date: 2023-09-28
Publication date: 2025-03-28

Abstract

The application discloses a control circuit and a control method for a direct current/direct current converter. The control circuit includes a compensation circuit that obtains a voltage compensation signal associated with an output voltage and a current compensation signal associated with an inductor current, that controls the voltage compensation signal to increase when the output voltage is less than a target voltage and to decrease when the output voltage is greater than the target voltage, that controls the current compensation signal to increase and decrease as a value indicative of the inductor current increases, and that generates a compensation reference signal based on a difference between the voltage compensation signal and the current compensation signal, and that generates a control signal based on the compensation reference signal that controls a switching circuit connected to the inductor to turn on or off to increase or decrease the inductor current. In this way, the dc/dc converter can respond relatively quickly to the sudden load change and improve the stability of the dc/dc converter.

Description

Control circuit and control method for DC/DC converter

Technical Field

The present invention relates to the field of converters, and in particular, to a dc/dc converter, and a control circuit and a control method for a dc converter.

Background

A dc/dc converter may generally refer to a characteristic of an energy storage element using capacitance, inductance, etc., and by performing a high-frequency on or off operation on a controllable switch (e.g., a metal oxide field effect transistor, MOSFET) using a control signal (e.g., a Pulse Width Modulation (PWM) signal), the energy storage element (e.g., an inductance) alternately stores electric energy and discharges electric energy to supply energy to a load. The power or voltage capability of its output is related to the duty cycle of the control signal. The dc/dc converter may be used for boost, buck, and buck-boost.

Fig. 1 illustrates a conventional controller 100 for controlling a dc/dc converter. As shown in fig. 1, the controller 100 includes an oscillator 102, a comparator 104, an Operational Transconductance Amplifier (OTA) 106, and a capacitor 108. The OTA 106 receives a predetermined voltage 116 and a feedback voltage 114 indicative of the output voltage of the dc/dc converter (or referred to as: load voltage) and provides a control current Icomp proportional to the difference between the predetermined voltage 116 and the feedback voltage 114. The output of OTA 156 is coupled to capacitor 108 such that control current Icomp can control reference voltage 112 on capacitor 108. The oscillator 102 provides an oscillating voltage 110 to the non-inverting input of the comparator 104. The reference voltage 112 on the capacitor 108 is provided to the inverting input of the comparator 104. The reference voltage 112 is in a range between a maximum level and a minimum level of the oscillating voltage 110. The comparator 104 compares the oscillating voltage 110 with the reference voltage 112 and outputs a PWM signal 118 according to the comparison result. For example, if the feedback voltage 114 is less than the predetermined voltage 116, the reference voltage 112 will increase and the duty cycle of the PWM signal 118 will decrease, so the output voltage of the dc/dc converter will decrease. If the feedback voltage 114 is less than the predetermined voltage 116, the reference voltage 112 will drop and the duty cycle of the PWM signal 118 will increase, and thus the output voltage will increase. Finally, the output voltage of the dc/dc converter may be adjusted to a desired level determined by the predetermined voltage 116.

The conventional controller 100 generates an oscillation signal having a fixed period through an oscillator. The structure of the oscillator 102 is generally complex, which increases the cost and power consumption of the entire controller 100. Further, the controller 100 responds only to changes in the load voltage when adjusting the duty cycle of the PWM signal 118. If the load current or the input voltage of the dc/dc converter suddenly changes, the load voltage may take a longer period of time to respond, thereby delaying the regulation of the PWM signal 118. Accordingly, the conventional controller 100 may not be able to rapidly and precisely control the load voltage (or output voltage).

Disclosure of Invention

Based on the above problems, the present invention proposes an improved control circuit for controlling a dc/dc converter. The DC/DC converter includes a switching circuit and an output inductor, the control circuit converting an input voltage of the DC/DC converter into an output voltage of the DC/DC converter by controlling on or off of the switching circuit to increase or decrease an inductor current flowing through the output inductor, the control circuit including a compensation circuit for obtaining a voltage compensation signal associated with the output voltage and a current compensation signal associated with the inductor current, for controlling the voltage compensation signal to increase when the output voltage is less than a target voltage and to decrease when the output voltage is greater than the target voltage, and for controlling the current compensation signal to increase and decrease with an increase in a value indicative of the inductor current, the compensation circuit further generating a compensation reference signal based on a difference between the voltage compensation signal and the current compensation signal, and a comparison circuit for generating a control signal for controlling on or off of the switching circuit based on the compensation reference signal.

The invention also proposes an improved control method of controlling a dc/dc converter, wherein the dc/dc converter comprises a switching circuit and an output inductance, and the control method comprises controlling the switching circuit to be turned on or off to increase or decrease an inductance current flowing through the output inductance, thereby converting an input voltage of the dc/dc converter into an output voltage of the dc/dc converter, obtaining a voltage compensation signal associated with the output voltage and a current compensation signal associated with the inductance current by a compensation circuit, controlling the voltage compensation signal to be increased when the output voltage is smaller than a target voltage and to be decreased when the output voltage is larger than the target voltage, controlling the current compensation signal to be increased and decreased with an increase in a value indicating the inductance current, generating a compensation reference signal based on a difference between the voltage compensation signal and the current compensation signal, and generating a control signal for controlling the switching circuit to be turned on or off based on the compensation reference signal by a comparison circuit.

Compared with the prior art, the direct current/direct current converter, the control circuit and the control method for controlling the direct current/direct current converter adopt a simpler circuit structure to generate PWM signals, and the duty ratio of the PWM signals can be adjusted based on the conditions of input current and output voltage when the load is suddenly changed, so that the direct current/direct current converter can respond to the sudden change of the load relatively quickly, and the stability of the direct current/direct current converter is improved.

Drawings

The objects, specific structural features and advantages of the present invention will be further understood from the following description in conjunction with some embodiments of the present invention and the accompanying drawings.

Fig. 1 shows an exemplary circuit diagram of a controller for a conventional dc/dc converter.

Fig. 2 shows an exemplary block diagram of a dc/dc converter according to an embodiment of the invention.

Fig. 3 shows an exemplary block diagram of a dc/dc converter according to an embodiment of the invention.

Fig. 4 shows an exemplary circuit diagram of a voltage-to-current conversion circuit according to one embodiment of the invention.

Fig. 5 shows an exemplary circuit diagram of a ramp signal generating circuit according to one embodiment of the present invention.

Fig. 6 shows an exemplary circuit diagram of a control signal generation circuit according to one embodiment of the invention.

Fig. 7 shows an exemplary waveform diagram of a portion of a signal generated by a control signal generation circuit in a step-down condition according to one embodiment of the present invention.

Fig. 8 shows an exemplary waveform diagram of a partial signal generated by the control signal generation circuit in the case of boosting according to one embodiment of the present invention.

Fig. 9 shows an exemplary circuit diagram of a control signal generation circuit according to one embodiment of the invention.

Fig. 10 shows an exemplary circuit diagram of a compensation circuit according to one embodiment of the invention.

Fig. 11 shows an exemplary waveform diagram of a portion of a signal generated by a control signal generation circuit in a step-down condition according to one embodiment of the present invention.

Fig. 12 shows a block diagram of an electronic device according to an embodiment of the invention.

Fig. 13 shows a flow chart of a method for controlling a dc/dc converter according to an embodiment of the invention.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail. While the invention has been illustrated and described with reference to these embodiments, it should be noted that the invention is not limited to only these embodiments. On the contrary, the invention is intended to cover all alternatives, modifications and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.

In addition, numerous specific details are set forth in the following description in order to provide a better illustration of the invention. It will be understood by those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail. The description is made in order to highlight the gist of the present invention.

Embodiments of the present invention provide an improved dc/dc converter. The dc/dc converter may convert the input voltage V _in to a stable output voltage V _out. In one embodiment, the dc/dc converter of the present invention may be used in a battery charging application, where the output voltage V _out is used as a system output voltage to power a load, and the output voltage V _out is used to charge a battery (not shown).

Fig. 2 shows an exemplary block diagram of a dc/dc converter 200 according to an embodiment of the invention. Referring to fig. 2, the dc/dc converter 200 includes an output circuit 220 and a control circuit 210 for controlling the output circuit 220. The output circuit 220 includes a switch circuit 221, an output inductance L _out, and an output capacitance C _out (or referred to as a filter capacitance C _out). The switch circuit 221 includes a switch Q1 and a switch Q2.

The dc/dc converter 200 shown in fig. 2 is implemented using a buck converter circuit configuration. Specifically, the switches Q1 and Q2 are coupled between the input voltage V _in and the ground, the common terminal of the switches Q1 and Q2 is coupled to one terminal of the output inductor L _out, the other terminal of the output inductor L _out is coupled to one terminal of the output capacitor C _out, the other terminal of the output capacitor C _out is coupled to the ground, and the common terminal of the output inductor L _out and the output capacitor C _out provides the output voltage V _out. An inductor current I _L flows through the output inductor L _out. Those skilled in the art will appreciate that in alternative embodiments, the dc/dc converter 200 may employ other switching circuit conversion configurations, such as a boost converter circuit configuration, a buck-boost converter circuit configuration, and the like. The invention is not limited in this regard.

In one embodiment, the control circuit 210 may generate one or more control signals (e.g., pulse Width Modulation (PWM) signals) for controlling the switches Q1 and Q2 to alternately close and open to increase or decrease the inductor current I _L flowing through the output inductor L _out, thereby enabling the output circuit 220 to convert the input voltage V _in to the output voltage V _out. Specifically, when switch Q1 is closed and switch Q2 is open, output inductance L _out in output circuit 220 is coupled with input voltage V _in through switch Q1. The input voltage V _in is greater than the output voltage V _out and the voltage value across the output inductance L _out is positive. At this time, the current flowing through the output inductor L _out gradually increases, which on the one hand supplies power to the load and on the other hand causes the output inductor L _out and the output capacitor C _out to store electromagnetic energy and electric energy. When switch Q1 is open and switch Q2 is closed, the voltage across output inductor L _out in output circuit 220 is negative. the electromagnetic energy stored in the output inductor L _out and the current flowing through the output inductor L _out gradually decrease, and the current continues to power the load. The output capacitor C _out may be used to stabilize the load voltage (e.g., output voltage V _out). In one embodiment, by controlling the duty cycle of the PWM signal, the control circuit 210 may control the time when the switch Q1 is closed (or the switch Q2 is open) (hereinafter referred to as T _on) and the time when the switch Q1 is open (or the switch Q2 is closed) (hereinafter referred to as T _off), thereby controlling the magnitude of the output voltage V _out. In one embodiment, the switches Q1 and Q2 are implemented with metal oxide semiconductor field effect transistors (MOSFETs, which may be referred to simply as MOS transistors). It should be appreciated that in other embodiments, the switches Q1 and Q2 may be implemented using other suitable electronic components, for example, the switches Q1 and/or Q2 may be implemented using diodes. The invention is not limited in this regard.

Fig. 3 shows an exemplary block diagram of a dc/dc converter 300 according to an embodiment of the invention. The dc/dc converter 300 includes an output circuit 320, a control circuit 310, and a driving circuit 330. Output circuit 320 may include output circuit 220 of fig. 2. The combination of control circuit 310 and drive circuit 330 may be one embodiment of control circuit 210 in fig. 2.

In one embodiment, control circuit 310 generates the PWM signal based on input voltage V _IN. The drive circuit 330 generates drive signals HDR and LDR to control (e.g., alternately turn on) the switches in the output circuit 320 according to the PWM signals. Thus, the output circuit 320 may generate the output voltage V _OUT that meets the load demand.

As shown in fig. 3, the control circuit 310 includes a voltage-current conversion circuit 312, a ramp signal generation circuit 313, and a control signal generation circuit 314. Depending on the practical application scenario, for example, when the input voltage V _in is relatively high, or when the highest allowable operating voltage of the control circuit 310 is relatively small, the control circuit 310 may further include a first voltage dividing circuit 311 (shown as a dashed box in fig. 3) coupled to the external terminal of the input voltage V _in, where the first voltage dividing circuit 311 is configured to scale the input voltage V _in by a preset voltage dividing ratio (hereinafter, the preset voltage dividing ratio is denoted as K1) to provide a suitable voltage for the operation of the subsequent element. For example, in one practical application of the present invention, the value of K1 may be set to 1/8. The control circuit 310 includes a first voltage divider circuit 311 (i.e., the input voltage V _in is scaled down by the preset ratio K1) as an example. For convenience of description, the scaled input voltage k1×v _in is also referred to as an input voltage.

As shown in fig. 3, the voltage-to-current conversion circuit 312 is coupled between the first voltage division circuit 311 and the ramp signal generation circuit 313 for converting the input voltage k1×v _in into a charging current I _CH, so that the charging current I _CH charges a capacitor C1 (shown in fig. 5) in the ramp signal generation circuit 313.

Fig. 4 illustrates an exemplary circuit diagram of voltage to current conversion circuit 312 in accordance with one embodiment of the present invention. Referring to fig. 4, the voltage-to-current conversion circuit 312 may include an operational amplifier OP1, a MOS transistor M2, a MOS transistor M3, and a resistor R1. The connection is shown in fig. 4. In the example shown in fig. 4, MOS transistors M1 and M2 are P-type MOS transistors, and MOS transistor M3 is an N-type MOS transistor. The input voltage k1×v _in is applied across the resistor R1 to generate a reference current I _ref, where I _ref＝K1×V_in/R₁,R₁ represents the resistance of the resistor R1. The reference current I _ref flows from the MOS transistor M1 to the resistor R1 through the MOS transistor M3. The MOS transistor M2 and the MOS transistor M1 form a current mirror structure to copy the reference current I _ref to generate a copy current I _CP (for example, I _CP＝K1×V_in/R₁). The replica current I _CP flows from the source of the MOS transistor M2 to the drain of the MOS transistor M2. The drain of the MOS transistor M2 is coupled to the capacitor C1 in the ramp signal generating circuit 313, so that the replica current I _CP can charge the capacitor C1. Thus, the replica current I _CP may also be referred to as the charge current I _CH. It can be seen that the above structure can make the magnitude of the charging current I _CH proportional to the magnitude of the input voltage V _in. Further, since the charging current I _CH is in a fixed ratio to the magnitude of the input voltage V _in, the capacitor C1 can be charged at a stable rate, so that the slope of the ramp signal generated by the ramp signal generating circuit 313 is a fixed value.

It should be appreciated that the circuit configuration shown in fig. 4 is only one example of the voltage-to-current conversion circuit 312, and that any suitable circuit configuration may be employed by those skilled in the art to implement the voltage-to-current conversion circuit 312 to convert the input voltage k1×v _in to the charging current I _CH.

Fig. 5 shows an exemplary circuit diagram of the ramp signal generating circuit 313 according to one embodiment of the present invention. In one embodiment of the present invention, please refer to fig. 5, the ramp signal generating circuit 313 includes a switch M4 (e.g., M4 is shown as a MOS transistor in fig. 5) and a capacitor C1. The capacitor C1 in the ramp signal generating circuit 313 is coupled to the voltage-current converting circuit 312. During the on period of switch M4, capacitor C1 discharges, and the voltage across capacitor C1 drops (e.g., to zero). During the off period of switch M4, charging current I _CH charges capacitor C1, and the voltage across capacitor C1 increases. In an embodiment of the present invention, the switch M4 is periodically turned on to periodically charge and discharge the capacitor C1, and the capacitor C1 generates the ramp signal V _ramp based on the periodic charge and discharge. Compared to the oscillator in the conventional controller 100, the present invention utilizes a periodically charged and discharged capacitor to generate an oscillating signal with a fixed period. This greatly reduces system complexity and system power consumption.

In one embodiment of the present invention, the switch M4 may be connected to a first PULSE signal generating circuit 501 (shown as a dashed box in fig. 5), the first PULSE signal generating circuit 501 periodically generating a PULSE signal PULSE1 based on the control signal PWM, the PULSE signal PULSE1 being used to periodically briefly turn on the switch M4 so that the capacitor C1 is periodically charged and discharged. The control signal generation circuit 314 is coupled to the ramp signal generation circuit 313 for receiving the ramp signal V _ramp from the ramp signal generation circuit 313 and generating the control signal PWM based on the ramp signal V _ramp. The control signal PWM has a period T. The specific details of how the control signal generation circuit 314 generates the control signal PWM based on the ramp signal will be described below in connection with fig. 6.

Fig. 6 shows an exemplary circuit diagram of control signal generation circuit 314A, according to one embodiment of the invention. Among them, the control signal generation circuit 314A is one embodiment of the above-described control signal generation circuit 314 shown in fig. 3 and 5. The control signal generation circuit 314A may be used in various types of dc/dc converters, including boost converters, buck converters, and buck-boost converters. Referring to fig. 6, the control signal generating circuit 314A includes a comparator COM1, a comparator COM2, a second pulse signal generating circuit 602A, AND gate AND latch 603A. The connection is shown in fig. 6. The control signal generation circuit 314A is configured to generate the control signal PWM based on the ramp signal V _ramp, the first voltage threshold V _TH1, and the second voltage threshold V _TH2.

As shown in fig. 6, the non-inverting input terminal of the comparator COM1 and the non-inverting input terminal of the comparator COM2 are both connected to the capacitor C1 in the ramp signal generating circuit 313 for receiving the ramp signal V _ramp, and the inverting input terminal of the comparator COM1 is connected to the voltage having the first voltage threshold V _TH1 and the inverting input terminal of the comparator COM2 is connected to the voltage having the second voltage threshold V _TH2. It should be understood that in practical designs, the ramp signal V _ramp may be input to the inverting input terminals of the comparator COM1 and the comparator COM2, the first voltage threshold V _TH1 and the second voltage threshold V _TH2 may be input to the non-inverting input terminals of the comparator COM1 and the comparator COM2, respectively, and the corresponding logic circuits may be designed for the requirements later. The invention is not limited in this regard. The comparator COM1 is configured to compare the ramp signal V _ramp with the first voltage threshold V _TH1 to generate a first comparison signal V _COMP1, and the comparator COM2 is configured to compare the ramp signal V _ramp with the second voltage threshold V _TH2 to generate a second comparison signal V _COMP2. The second pulse signal generating circuit 602A, AND gate AND latch 603A are configured to generate the control signal PWM based on the first comparison signal V _COMP1 AND the second comparison signal V _COMP2.

Referring back to fig. 3, the output of the control signal generation circuit 314A is coupled to the drive circuit 330 for PWM input of the control signal to the drive circuit 330. The driving circuit 330 generates complementary high and low driving signals HDR and LDR according to the control signal PWM. For example, in the case of buck, the high drive signal HDR is the same as or synchronous with the signal PWM, and the low drive signal LDR is opposite to the signal PWM. In the boost case, the high drive signal HDR is opposite to the signal PWM, and the low drive signal LDR is the same as the signal PWM. The high drive signal HDR and the low drive signal LDR are used to alternately turn on or off switching circuits in the output circuit 320, thereby enabling the output circuit 320 to convert the input voltage V _in to the output voltage V _out for provision to a load.

The term "on or off of the switching circuit" appearing herein will now be described taking the dc/dc converter 200 implemented with a buck converter circuit structure as shown in fig. 2 as an example. The switching circuit 221 in fig. 2 includes a switch Q1 and a switch Q2, the switching circuit 221 being defined as being on when the switch Q1 is closed and the switch Q2 is open, and the output inductance L _out being coupled with the input voltage V _in, and the switching circuit 221 being defined as being off when the switch Q1 is open and the switch Q2 is closed, and the output inductance L _out being coupled with the reference ground. The definition of on or off of the switching circuit in the dc/dc converter 200 implemented by the boost converter circuit structure is similar to that, and the disclosure is not repeated here.

The operation principle and operation of the control signal generation circuit 314A will be described in detail with reference to fig. 7 and 8.

Fig. 7 is an exemplary waveform diagram of a portion of signals generated by the control signal generation circuit 314A shown in fig. 6 in a step-down condition according to one embodiment of the present invention. Fig. 7 will be described in conjunction with fig. 2 to 6. The load may be classified into a light load and a heavy load according to the amount of power consumed by the load. In this embodiment, a heavy load will be described as an example.

First, the source of signal PULSE0 in fig. 6 and 7 is illustrated by a first input (e.g., an inverting input) of comparator COM0 (see fig. 6) receiving feedback voltage V _fb indicative of output voltage V _out and a second input (e.g., a non-inverting input) receiving lower voltage threshold V _lower. when the output voltage V _out is relatively high, or the highest allowable operating voltage of the control circuit 310 (or the control circuit 210) is relatively low, the feedback voltage V _fb representing the output voltage V _out received by the comparator COM0 may be the output voltage V _out reduced by the voltage dividing circuit. for example, the control circuit 310 (or the control circuit 210) may further include a second voltage dividing circuit (not shown) coupled to an external terminal of the output voltage V _out for reducing the output voltage V _out by a preset voltage dividing ratio K2 (e.g., k2=1/8). The comparator COM0 compares the feedback voltage V _fb with the lower voltage threshold V _lower and generates a signal PULSE0. The output voltage V _out has ripple, which causes the feedback voltage V _fb to fluctuate also within a small voltage range. When the feedback voltage V _fb drops to the lower voltage threshold V _lower, the signal PULSE0 transitions from a low level to a high level. Wherein the lower voltage threshold V _lower may represent a minimum value of the feedback voltage V _fb.

When reloaded, the load power consumption is large, resulting in the feedback voltage V _fb falling to the lower voltage threshold V _lower in a short time, thereby causing the signal PULSE0 to jump from low level to high level in a short time. This time is less than period T. I.e. reloading, the signal PULSE0 has been hopped from a low level to a high level before the voltage on the capacitor C1 reaches the second voltage threshold V _TH2. When the load is lightly loaded, the load power consumption is small, so that the feedback voltage V _fb can be reduced to the lower voltage threshold V _lower within a long time, and the signal PULSE0 can be further changed from a low level to a high level. This time is greater than period T. I.e. light load, the signal PULSE0 jumps from low to high level only for a period of time after the voltage on the capacitor C1 reaches the second voltage threshold V _TH2.

It can be seen that with this signal PULSE0, a heavy load time constant frequency can be achieved, while a light load time down-conversion is achieved. Because the power consumption of the load is small in light load, the current is not completely absorbed by the load, and a part of the current is absorbed and stored by the capacitor. Then, the down-conversion mode can be used to discharge the load by using the energy stored before the capacitor when the current flowing through the inductor is zero, so that the conversion efficiency is improved. In addition, the light load time constant frequency can be realized under the condition of not considering the conversion efficiency.

As shown in fig. 7, at time t ₀, the control signal PWM generates a rising edge, and the first PULSE signal generating circuit 501 in the ramp signal generating circuit 313 generates a PULSE signal PULSE1 according to the rising edge to briefly turn on the switch M4 in the ramp signal generating circuit 313. During the conduction of switch M4, the voltage across capacitor C1 (i.e., V _ramp) drops (e.g., to zero). Subsequently, the switch M4 is turned off, the charging current I _CH charges the capacitor C1, and the voltage on the capacitor C1 rises.

At time t ₁, the voltage on capacitor C1 reaches (or approximately reaches) the first voltage threshold V _TH1 and the comparator COM1 outputs a logic high. The second PULSE signal generating circuit 602A generates a PULSE signal PULSE2 according to the logic high, so that the reset terminal R of the latch 603A is briefly set to logic high. The control signal PWM output by the latch 603A generates a falling edge according to the latch's operating principle.

That is, the control signal PWM is logic high at time period t ₀～t₁. Thus, the high driving signal HDR is logic high for a period t ₀～t₁ and the low driving signal LDR is logic low for a period t ₀～t₁ to turn on the switching circuits in the output circuit 320. The on time of the switching circuit is T _on＝t₁-t₀＝C₁×V_TH1/I_CH (1).

At time t ₂, the voltage on capacitor C1 reaches (or approximately reaches) the second voltage threshold V _TH2, and comparator COM2 outputs a logic high, at which time signal PULSE0 is also logic high, causing the set terminal S of latch 603A to be briefly set to logic high. The control signal PWM output by latch 603A produces a rising edge according to the latch's operating principle. To this end, the control signal PWM starts to enter the next period, i.e., the period of the control signal PWM is t=t ₂-t₀＝C₁×V_TH2/I_CH (2).

The control signal PWM is at logic low for a period t ₁～t₂, so that the high drive signal HDR is at logic low for a period t ₁～t₂, and the low drive signal LDR is at logic high for a period t ₁～t₂, to turn off the switching circuits in the output circuit 320. The off time T _off＝t₂-t₁ of the switching circuit.

The duty cycle D of the on-time of the switching circuit can be expressed as d=t _on/T (3), and d=v _TH1/V_TH2 (4) can be obtained by combining equations (1) and (2). Thus, in one embodiment of the present invention, to achieve a relatively stable buck function of the dc/dc converter, e.g., d=v _out/V_in (5), the first voltage threshold V _TH1 in equation (4) may be set to kχv _out and the second voltage threshold V _TH2 to kχv _in. For example, K herein may be set to K1 in the foregoing. In this way, by using the control signal generating circuit 314A shown in fig. 6 and setting the appropriate first voltage threshold V _TH1 and the second voltage threshold V _TH2, a relatively stable step-down function of the dc/dc converter can be achieved. Furthermore, since the second voltage threshold V _TH2 is set to kχv _in, that is, the second voltage threshold V _TH2 is set to be proportional to the input voltage V _in, and since I _CH is also proportional to the input voltage V _in, in combination with equation (2), the period T can be made independent of both the input voltage V _in and the output voltage V _out, as a fixed value.

Fig. 8 shows an exemplary waveform diagram of a portion of a signal generated by the control signal generation circuit 314A in the case of boosting according to one embodiment of the present invention. Fig. 8 will be described in conjunction with fig. 2 to 6. In this embodiment, a heavy load will be described as an example. The signal PULSE0 is similar to that in fig. 7 and will not be described again.

At time t ₀, the control signal PWM generates a rising edge, and the first PULSE signal generating circuit 501 in the ramp signal generating circuit 313 generates a PULSE signal PULSE1 according to the rising edge to briefly turn on the switch M4. During the conduction of switch M4, the voltage across capacitor C1 (i.e., V _ramp) drops (e.g., zero). Subsequently, the switch M4 is turned off, the charging current I _CH charges the capacitor C1, and the voltage on the capacitor C1 rises.

That is, the control signal PWM is logic high for the period t ₀～t₁. Thus, the high driving signal HDR is logic low for the period t ₀～t₁ and the low driving signal LDR2 is logic high for the period t ₀～t₁ to turn on the switching circuits in the output circuit 320. The on-time T _on＝t₁-t₀＝C₁×V_TH1/I_CH (6) of the switching circuit.

At time t ₂, when the voltage on the capacitor C1 reaches (or approximately reaches) the second voltage threshold V _TH2, the comparator COM2 outputs a logic high, and the signal V _COMP0 is also logic high, so that the set terminal S of the latch 603A is briefly set to logic high. The control signal PWM output by latch 603A produces a rising edge according to the latch's operating principle. To this end, the control signal PWM starts to enter the next period, i.e., period t=t ₂-t₀＝C₁×V_TH2/I_CH (7) of the control signal PWM.

The control signal PWM is at logic low for a period of time t ₁～t₂. The high driving signal HDR is logic high for a period of time t ₁～t₂ and the low driving signal LDR is logic low for a period of time t ₁～t₂ to turn off the switching circuits in the output circuit 320. The off time T _off＝t₂-t₁ of the switching circuit.

Since d=t _on/T, combining equations (6) and (7) can result in d=v _TH1/V_TH2 (8). Thus, in one embodiment of the present invention, to achieve a relatively stable boost function of the DC/DC converter, for example, D= (V _out-V_in)/V_out (9), the first voltage threshold V _TH1 in equation (8) may be set to Kx (V _out-V_in), the second voltage threshold V _TH2 may be set to KXV _out. For example, K may be set to K1. as previously described, and a relatively stable boost function of the DC/DC converter may be achieved using the control signal generation circuit 314A shown in FIG. 6, and by setting the appropriate first voltage threshold V _TH1 and second voltage threshold V _TH2.

Similar to the step-down case described above, since the second voltage threshold V _TH2 is set to k×v _out, that is, the second voltage threshold V _TH2 is set to be proportional to the input voltage V _in, and since I _CH is also proportional to the input voltage V _in, the period T can be made independent of both the input voltage V _in and the output voltage V _out, as a fixed value, in conjunction with equation (7).

Therefore, the present invention proposes an improved control circuit (e.g. the control circuit 210 or the control circuit 310) for controlling the dc/dc converter 300, which is capable of generating corresponding Pulse Width Modulation (PWM) signals according to the input voltage and the output voltage of the dc/dc converter, so as to control the on/off of the switching circuit of the dc/dc converter, and has the advantages of fast dynamic response, natural transition of the light-load mode, and the like compared to the conventional controller.

In addition, in order to further improve the stability of the system, another embodiment of the present invention proposes a control circuit having both voltage and current feedback.

Fig. 9 shows an exemplary circuit diagram of the control signal generation circuit 314B according to another embodiment of the present invention. The control signal generating circuit 314B may be another embodiment of the control signal generating circuit 314. Referring to fig. 9, the control signal generating circuit 314B includes a comparing circuit 908 and a compensating circuit 904. The comparison circuit 908 includes a comparator COM1, a comparator COM2, a second pulse signal generation circuit 602B, AND gate AND a latch 603B. It can be seen that the control signal generation circuit 314B in fig. 9 and the control signal generation circuit 314A in fig. 6 have similar structures, except that the control signal generation circuit 314B further includes a compensation circuit 904, and the inverting input terminal of the comparator COM1 is operable to receive the voltage signal V _cmp-I_cmp. For the sake of brevity, portions of fig. 9 that are similar to fig. 6 will not be described again.

The compensation circuit 904 is configured to obtain a voltage compensation signal associated with the output voltage V _out and a current compensation signal associated with the input current (or inductor current) I _in, and to control the voltage compensation signal to increase when the output voltage V _out is less than the target voltage, to decrease when the output voltage V _out is greater than the target voltage, and to control the current compensation signal to increase, decrease, as the value indicative of the inductor current I _in increases. For example, the target voltage here represents a desired output voltage. For example, in the case of step-down, the target voltage is d×v _in, D <1. As described above, D represents the duty cycle of the on-time of the switching circuit in the dc/dc converter.

As shown in fig. 9, the compensation circuit 904 according to one embodiment of the present invention includes a current sampling circuit 905, a voltage error amplifying circuit 906, and a compensation reference signal generating circuit 907. The current sampling circuit 905 is configured to sample an input current (or an inductor current) I _in to obtain a current compensation signal I _cmp, the voltage error amplifying circuit 906 is configured to generate a voltage compensation signal V _cmp according to a reference voltage V _ref representing a target voltage and a feedback voltage V _fb representing an output voltage V _out, and the compensation reference signal generating circuit 907 is configured to receive the voltage compensation signal V _cmp and the current compensation signal I _cmp, and to perform a difference between the voltage compensation signal V _cmp and the current compensation signal I _cmp to generate a compensation reference signal V _cmp-I_cmp. Likewise, the reference voltage V _ref used to characterize the target voltage here may be a scaled target voltage, depending on the highest allowable operating voltage of the control circuit 310. For example, the reduction ratio of the reference voltage V _ref with respect to the target voltage is the same as the reduction ratio of the feedback voltage V _fb with respect to the output voltage V _out.

Fig. 10 illustrates an exemplary circuit diagram of compensation circuit 904 according to one embodiment of the invention. Fig. 10 will be described in conjunction with fig. 9. As shown in fig. 10, the error amplifying circuit 906 includes an error amplifier EA and an error compensation loop (e.g., including a capacitor C2). The connection is shown in fig. 10. The error amplifier EA has a first input (e.g., an inverting input), a second input (e.g., a non-inverting input), and an output. The error amplifier EA has a first input receiving a feedback voltage V _fb indicative of the output voltage V _out and a second input receiving a reference voltage V _ref indicative of the target voltage and generating an error amplified signal I _COMP at the output of the error amplifier EA based on the difference between the feedback voltage V _fb and the reference voltage V _ref. An error compensation loop (e.g., a capacitor C2) of the error amplifier EA is coupled between the output of the error amplifier EA and a reference ground such that the error amplification signal I _COMP can control the voltage on the capacitor C2. The error compensation loop of the error amplifier EA may be used to provide the compensation zero and pole of the error amplifier EA to enhance the stability of the system. It should be appreciated that the error compensation loop of the error amplifier EA may have other configurations, such as a two-pole, single-zero compensation network or a three-pole, two-zero compensation network, as the invention is not limited in this regard.

The error amplification circuit 906 regulates the voltage V _cmp (i.e., the voltage on the capacitor C2) by sinking and sinking current through the capacitor C2. For example, when the load of the dc/dc converter suddenly increases, the output voltage V _out decreases, the feedback voltage V _fb representing the output voltage V _out will be smaller than the reference voltage V _ref, and the error amplifier EA can output the control current I _COMP to charge the capacitor C2 to increase the voltage V _cmp. When the load of the dc/dc converter suddenly becomes smaller, the output voltage V _out increases, the feedback voltage V _fb, which characterizes the output voltage V _out, increases to be greater than the reference voltage V _ref, and the error amplifier EA can sink the control current I _COMP from the capacitor C2 to decrease the voltage V _cmp. according to an embodiment of the present invention, the voltage V _cmp reflects the deviation of the output voltage V _out from the target voltage and is fed back into the control signal generating circuit to compensate for the system stability problem due to the abrupt load change. Therefore, the voltage V _cmp is referred to as a voltage compensation signal in the present invention. details of how the voltage compensation signal V _cmp compensates for system stability will be described in detail below.

With continued reference to fig. 10, the current sampling circuit 905 includes a current sense amplifier CSA, current sense resistors Rsen, R2, R3, R4, and a MOS transistor M5, and the connection relationship is shown in fig. 10. In this embodiment, M5 is an N-type MOS transistor. The current sense resistor Rsen is coupled to the input dc voltage V _in and the output inductor L _out, respectively, at both ends thereof, for sensing the input current (or inductor current) I _in. The current sense amplifier CSA includes a first input (e.g., a non-inverting input), a second input (e.g., an inverting input), and an output, the first and second inputs of which are connected to both ends of a current sense resistor Rsen through resistors R2 and R3, respectively. The current sense amplifier CSA may comprise an ideal operational amplifier with its two inputs disconnected from the current and the two inputs shorted together so that the voltage across the current sense resistor Rsen is the same as the voltage across R2, thus resulting in a current I _R2＝R_sen×I_in/R₂ (10) flowing through R2. Where R _sen represents the resistance value of the current sense resistor Rsen, and R ₂ represents the resistance value of the resistor R2. Current I _R2 flows from R2 through MOS transistor M5 and shunts at the upper node of resistor R4. The resistor R4 is set to be large enough to lead the current which is shunted to R4 to be negligible, thereby leading to sampling current The ratio between R _sen and R2 (e.g., the ratio is denoted as K3 herein) is referred to as the current sampling coefficient in the present invention, then

According to an embodiment of the present invention, since the sampling current I _sam is proportional to the input current I _in, the magnitude of the input current I _in can be reflected and fed back into the control signal generating circuit to compensate for system stability problems due to abrupt load changes. Therefore, the sampling current I _sam is referred to as a current compensation signal I _cmp, i.eSpecifically, the current sampling coefficient K3 may be set according to a system stability condition caused by slope compensation in the current mode of the power switch:

In relation (12), M _c represents the slope of the ramp signal V _ramp, and M ₂ is the falling slope of the input current (or inductor current) I _in in the period of T _off. It is possible to further obtain:

In the relational expression (13), V _in denotes an input voltage, K1 denotes a voltage division ratio of the input voltage V _in, T denotes a period of turning on and off of the switching circuit (or a period of the control signal PWM), D denotes a duty ratio of an on time of the switching circuit, K3 denotes a current sampling coefficient, V _out denotes an output voltage, and L denotes a value of an output inductance.

By adjusting the sampling coefficient K3 (e.g., by setting the values of the current sense resistors Rsen and R2), the magnitude of the sampling current can be adjusted. For example, in one practical application of the present invention, in the case of voltage reduction, consider the worst case (e.g., the case where the voltage reduction capability of the dc/dc converter 300 is poor), taking d=0.9. Further, assuming that the partial pressure ratio k1=1/8, l=1uh, t=1.2 us, it is possible to obtainFor example, K3 may take on a value of 1/6.

It should be appreciated that the circuit diagram of current sampling circuit 905 in fig. 10 is provided as an example only, and that one skilled in the art may design any suitable circuit to sample the input current (or inductor current) I _in of dc/dc converter 300 and cause the sampled current I _sam＝K3×I_in.

Referring back to fig. 9, in one embodiment, the compensation reference signal generation circuit 907 receives the current compensation signal I _cmp associated with the input current I _IN obtained by the current sampling circuit 905 and the voltage compensation signal V _cmp associated with the output voltage V _IN obtained by the voltage error amplification circuit 906, and generates the compensation reference signal V _cmp-I_cmp from the signals I _cmp and V _cmp. For example, the compensation reference signal generation circuit 907 may include a subtraction circuit for differencing the voltage compensation signal V _cmp and the current compensation signal I _cmp to generate the compensation reference signal V _cmp-I_cmp.

Fig. 10 shows a specific circuit diagram of the compensation reference signal generation circuit 907 in one possible embodiment of the invention. It should be appreciated that the specific circuit diagram of the compensation reference signal generation circuit 907 in fig. 10 is shown by way of example only, and that one skilled in the art may design any suitable circuit to make the difference for the voltage compensation signal V _cmp and the current compensation signal I _cmp.

Fig. 11 illustrates an exemplary waveform diagram of a portion of signals generated by the control signal generation circuit 314B shown in fig. 9 in a step-down condition according to one embodiment of the present invention. Fig. 11 is described in conjunction with fig. 2-5 and fig. 9-10. In this embodiment, a heavy load will be described as an example. The signal PULSE0 is similar to that in fig. 7 and will not be described again.

At time t ₁, the voltage on capacitor C1 reaches (or approximately reaches) the value V _cmp-K3×I_in of the compensated reference signal, and comparator COM1 outputs a logic high. The second PULSE signal generating circuit 602B generates a PULSE signal PULSE2 according to the logic high, so that the reset terminal R of the latch 603B is briefly set to logic high. The control signal PWM output by latch 603B produces a falling edge according to the latch's operating principle.

That is, the control signal PWM is logic high for the period t ₀～t₁. The high driving signal HDR is logic high for a period of time t ₀～t₁ and the low driving signal LDR2 is logic low for a period of time t ₀～t₁ to turn on the switching circuits in the output circuit 320. The on-time T _on＝t₁-t₀＝C₁×(V_cmp-K3×I_in)/I_CH (14) of the switching circuit.

At time t ₂, the voltage on capacitor C1 reaches (or approximately reaches) a second voltage threshold V _TH2 (e.g., K1×V _in), and comparator COM2 outputs a logic high, at which time signal V _COMP0 is also logic high, causing the set terminal S of latch 603B to be briefly set to logic high. The control signal PWM output by latch 603B produces a rising edge according to the latch's operating principle. To this end, the control signal PWM starts to enter the next period, i.e., period t=t ₂-t₀＝C₁×(K1×V_in)/I_CH (15) of the control signal PWM.

Since d=t _on/T, in combination with equations (14) and (15), d= (V _cmp-K3×I_in)/(K1×V_in) (16) can be obtained. In the first period T shown in fig. 11 (e.g., T0 to T2), the dc/dc converter 300 is in a steady state (e.g., V _out is the output voltage at steady state), so the duty cycle D satisfies the relationship d=v _out/V_in with the input and output voltages. In combination with equation (16), V _cmp-K3×I_in can be automatically adjusted to k1×v _out by the compensation circuit.

Subsequently (e.g., at time t ₃ in the second cycle), the load suddenly increases, causing the output voltage V _out to suddenly decrease, and the feedback voltage V _fb received by the error amplifier EA is less than the reference voltage V _ref, causing the voltage compensation signal V _cmp to increase. Although the input current (or inductor current) I _in increases when the PWM signal is at a high level, the increase in k3×i _IN is small compared to the increase in V _CMP, so the value of V _cmp-K3×I_in increases.

At time T ₄, the voltage on capacitor C1 reaches (or approximately reaches) V _cmp-K3×I_in and the on time T _on＝t₄-t₂ of the switching circuit. Since the value of V _cmp-K3×I_in has been increased at this time compared to the previous cycle, so that T ₄-t₂>t₁-t₀, the on-time T _on of the switching circuit increases in the second cycle. Since the duty ratio d=t _on/T of the on time of the switching circuit and T is a fixed value, an increase in the duty ratio D can be achieved. According to the operating principle of the dc/dc converter 300, when D increases, the output voltage V _out increases. Finally, at time t ₇, the output voltage V _out is gradually increased to the desired level determined by the target voltage (or reference voltage V _ref), and the dc/dc converter 300 returns to the steady state again at t ₇, at which time the value of V _cmp-K3×I_in returns to the value of k1×v _out.

When the dc/dc converter is controlled using the control signal generating circuit 314A of fig. 6, if the load suddenly increases, the output voltage V _out suddenly decreases, so that the first voltage threshold V _TH1 (e.g., V _TH1＝K×V_OUT) decreases, and thus the duty ratio D of the PWM signal also decreases (e.g., see equation (4), d=v _TH1/V_TH2), and then the average value of the input current (or inductor current) I _in decreases, resulting in further decrease of the output voltage V _out. That is, when the load suddenly changes, the output voltage V _out of the dc/dc converter controlled by the control signal generating circuit 314A may be relatively unstable.

In contrast, when the dc/dc converter is controlled using the control signal generating circuit 314B of fig. 9, the input current I _in and the output voltage V _out can be fed back into the system as feedback signals, so that the dc/dc converter can relatively quickly respond to adjust the duty ratio of the PWM signal based on the conditions of the input current I _in and the output voltage V _out when the load abrupt causes the output voltage V _out to abrupt, thereby adjusting the output voltage V _out back to the steady state.

More specifically, in one embodiment, at the initial stage of each period T, since the PWM signal is at a high level, the input current (or inductor current) I _IN increases. Thus, when the load suddenly increases, the compensation reference signal V _CMP-K3×I_IN may increase or may decrease (not shown in fig. 10). For example, when the load suddenly increases, the compensation signal V _CMP increases, if the increase in the input current I _IN is small, the value of V _CMP-K3×I_IN increases, thereby further increasing the input current I _IN to meet the load demand as soon as possible, and if the increase in the input current I _IN is too large, the value of V _CMP-K3×I_IN may decrease, thereby decreasing the increase in the input current I _IN. thus, in one embodiment, control signal generation circuit 314B may adjust compensation signal V _CMP in response to a sudden load change (e.g., in response to a sudden change in output voltage V _OUT) to adjust compensation reference signal V _CMP-K3×I_IN to control output voltage V _OUT. In addition, the compensation reference signal V _CMP-K3×I_IN is also affected by the input current I _IN, which can be used to avoid the situation that the input current I _IN is excessively amplified too little or too much, and further improve the stability of controlling the output voltage V _OUT.

The operation principle and operation manner of the control signal generation circuit 314B shown in fig. 9 in the case of a step-down are described above in fig. 11 based on an exemplary waveform diagram of a partial signal. It should be understood that the same principle and mode of operation apply in the case of boosting. The present invention is not described in detail herein.

Fig. 12 shows a block diagram of an electronic device 1200 according to an embodiment of the invention. The electronic device 1200 includes a dc/dc converter 200 (or 300), a switch Q0, a battery 1204, and a load 1203. The connection relationship is shown in fig. 12. In one embodiment, the electronic device 1200 is a tablet computer. In one embodiment, the battery 1204 includes 4 single cells, and the voltage across the battery 1204 varies from 0V to full charge voltage (e.g., 19V).

The electronic device 1200 also includes an input port VIN. The voltage at the input port VIN is the input voltage V _in. The input voltage V _in＝V_DC-I_SR₀, where V _DC represents a dc voltage supplied from the adapter 1202, I _S represents a current flowing through a transmission line between the adapter 1202 and the electronic device 1200, and R ₀ represents a resistance value on the transmission line between the adapter 1202 and the electronic device 1200.

The output voltage V _out is used as a system output voltage to supply power to the load 1203, and the output voltage V _out is used to charge the battery 1204.

Fig. 13 shows a flow chart of a control method 1300 for controlling a dc/dc converter 300 (or 200) with a control circuit 310 (or 210) according to one embodiment of the invention. Fig. 13 will be described in conjunction with fig. 2-5 and fig. 9-11. The dc/dc converter 300 may employ a buck conversion circuit configuration, a boost conversion circuit configuration, a buck-boost conversion circuit configuration, or the like. The dc/dc converter 300 may include a switching circuit 221 and an output inductance L _out. The control circuit 310 may include a compensation circuit 904 and a comparison circuit 908. The control method 1300 may include:

Step 1310, converting the input voltage V _in of the dc/dc converter 300 into the output voltage V _out of the dc/dc converter 300 by controlling the switch circuit 221 to turn on or off to increase or decrease the inductor current I _in flowing through the output inductor L _out;

Step 1320, obtaining, by the compensation circuit 904, a voltage compensation signal V _cmp associated with the output voltage V _out and a current compensation signal I _cmp associated with the inductor current I _in;

Step 1330, the control voltage compensation signal V _cmp is increased when the output voltage V _out is less than the target voltage and decreased when the output voltage V _out is greater than the target voltage;

Step 1340, the control current compensation signal I _cmp increases and decreases with increasing value of the indication inductor current I _in;

Step 1350, generating a compensation reference signal based on the difference between the voltage compensation signal V _cmp and the current compensation signal I _cmp, and

In step 1360, a control signal for controlling on or off of the switching circuit 221 is generated by the control signal generating circuit 314 based on the compensation reference signal.

The DC/DC converter and the control circuit and the control method for controlling the DC/DC converter can generate corresponding Pulse Width Modulation (PWM) signals according to the input voltage and the output voltage of the DC/DC converter so as to control the on or off of a switching circuit of the DC/DC converter, so that the DC/DC converter can work normally and efficiently, and can adjust the duty ratio of the PWM signals based on the input current and the output voltage, thereby enabling the DC/DC converter to respond to the sudden change of a load relatively quickly and improving the stability of the DC/DC converter.

The foregoing detailed description and drawings are merely typical examples of the invention. It will be evident that various additions, modifications and substitutions may be made therein without departing from the spirit and scope of the invention as defined in the accompanying claims. It will be appreciated by those of skill in the art that the invention can be varied in form, construction, arrangement, proportions, materials, elements, components and otherwise, used in the practice of the invention, which are particularly adapted to specific environments and operative requirements without departing from the principles of the present invention. Accordingly, the embodiments disclosed herein are meant to be illustrative only and not limiting as to the scope of the invention which is to be given the full breadth of the appended claims and any and all legal equivalents thereof.

Claims

1. A control circuit for a dc/dc converter including a switching circuit and an output inductance, the control circuit converting an input voltage of the dc/dc converter into an output voltage of the dc/dc converter by controlling on or off of the switching circuit to increase or decrease an inductance current flowing through the output inductance, the control circuit comprising:

a compensation circuit for obtaining a voltage compensation signal associated with the output voltage and a current compensation signal associated with the inductor current, for controlling the voltage compensation signal to increase when the output voltage is less than a target voltage and decrease when the output voltage is greater than the target voltage, and for controlling the current compensation signal to increase and decrease with an increase in a value indicative of the inductor current, the compensation circuit further generating a compensation reference signal based on a difference between the voltage compensation signal and the current compensation signal, and

And a comparison circuit for generating a control signal for controlling on or off of the switching circuit based on the compensation reference signal.

2. The control circuit of claim 1, wherein the compensation circuit comprises:

the current sampling circuit is used for sampling the inductance current to acquire the current compensation signal;

a voltage error amplifying circuit for generating the voltage compensation signal based on a reference voltage indicative of the target voltage and a feedback voltage indicative of the output voltage, and

And the compensation reference signal generating circuit is used for receiving the voltage compensation signal and the current compensation signal and generating the compensation reference signal by making a difference between the voltage compensation signal and the current compensation signal.

3. The control circuit of claim 2, wherein the voltage error amplifying circuit comprises:

An error amplifier, wherein a first input of the error amplifier is configured to receive the reference voltage, a second input of the error amplifier is configured to receive the feedback voltage, and the error amplifier generates an error amplified signal at an output of the error amplifier based on the reference voltage and the feedback voltage, and

And the error compensation loop is used for providing a compensation zero point and a pole of the error amplifier.

4. A control circuit according to claim 3, wherein the error compensation loop comprises a first capacitor having a first terminal and a second terminal, wherein the first terminal is connected to the output terminal, the second terminal is connected to a reference ground, and the voltage compensation signal comprises a voltage on the first terminal.

5. The control circuit of claim 2, wherein the compensation reference signal generation circuit comprises a subtraction circuit.

6. The control circuit of claim 1 or 2, wherein the current compensation signal is proportional to the value indicative of the inductor current, and a ratio between the current compensation signal and the value satisfies the following relationship:

Wherein V _in represents the input voltage, T represents the period of turning on and off the switching circuit, D represents the ratio of the output voltage to the input voltage, K represents the ratio between the current compensation signal and the value, V _out represents the output voltage, and L represents the value of the output inductance.

7. The control circuit according to claim 1 or 2, further comprising a ramp signal generating circuit including a first switch and a second capacitor, wherein the first switch is configured to be periodically turned on to control the second capacitor to be periodically charged and discharged, the second capacitor is configured to generate a ramp signal based on the charging and the discharging, and wherein the comparing circuit is configured to generate the control signal based on the compensation reference signal and the ramp signal.

8. The control circuit of claim 7, wherein the ramp signal generating circuit further comprises a first pulse signal generating circuit for periodically generating a pulse signal based on the control signal, wherein the pulse signal is used to periodically turn on the first switch.

9. The control circuit of claim 7, wherein the comparison circuit comprises:

a first comparator for comparing the ramp signal on the second capacitor with the compensation reference signal to generate a first comparison signal;

a second comparator for comparing the ramp signal on the second capacitor with a periodic reference signal to generate a second comparison signal,

Wherein the comparison circuit generates the control signal based on the first comparison signal and the second comparison signal.

10. The control circuit of claim 9, wherein the periodic reference signal is proportional to the input voltage.

11. The control circuit of claim 9, wherein the comparison circuit further comprises:

A second pulse signal generating circuit including an input terminal and an output terminal, the input terminal of the second pulse signal generating circuit being connected to the output terminal of the first comparator and generating a second pulse signal at the output terminal of the second pulse signal generating circuit based on the first comparison signal, and

And the reset end of the latch is controlled by the second pulse signal, and the set end of the latch is controlled by the second comparison signal, wherein the latch is used for generating the control signal based on the first comparison signal and the second comparison signal.

12. A control method of controlling a dc/dc converter, wherein the dc/dc converter includes a switching circuit and an output inductance, and the control method includes:

Controlling the switching circuit to be turned on or off to increase or decrease an inductance current flowing through the output inductance, thereby converting an input voltage of the dc/dc converter into an output voltage of the dc/dc converter;

Obtaining, by a compensation circuit, a voltage compensation signal associated with the output voltage and a current compensation signal associated with the inductor current;

controlling the voltage compensation signal to increase when the output voltage is less than a target voltage and decrease when the output voltage is greater than the target voltage;

controlling the current compensation signal to increase and decrease with increasing value indicative of the inductor current;

generating a compensation reference signal based on a difference between the voltage compensation signal and the current compensation signal, and

A control signal for controlling on or off of the switching circuit is generated by a comparison circuit based on the compensation reference signal.

13. The control method according to claim 12, wherein the control method further comprises:

sampling the inductance current to obtain the current compensation signal;

Generating the voltage compensation signal from a reference voltage representative of the target voltage and a feedback voltage representative of the output voltage, and

The voltage compensation signal and the current compensation signal are differenced to generate the compensation reference signal.

14. The control method according to claim 13, wherein the control method further comprises:

Receiving the reference voltage with a first input of an error amplifier;

Receiving the feedback voltage with a second input of the error amplifier;

Generating an error amplified signal at an output of the error amplifier based on the reference voltage and the feedback voltage, and

The compensation zero and pole of the error amplifier are provided by an error compensation loop.

15. The control method of claim 14, wherein the error compensation loop comprises a first capacitor having a first terminal and a second terminal, wherein the first terminal is connected to the output terminal and the second terminal is connected to a reference ground, wherein the control method further comprises generating the voltage compensation signal on the first terminal.

16. The control method of claim 13, wherein differencing the voltage compensation signal and the current compensation signal comprises:

And utilizing a subtracting operation circuit to make a difference between the voltage compensation signal and the current compensation signal.

17. The control method according to claim 12 or 13, wherein the control method further comprises:

Controlling said current compensation signal in proportion to said value indicative of said inductor current, and

Controlling the ratio between the current compensation signal and the value to satisfy the following relationship:

18. The control method according to claim 12 or 13, wherein the control circuit further includes a first switch and a second capacitor, wherein the control method further includes:

Periodically turning on the first switch to control the second capacitor to charge and discharge periodically;

Generating a ramp signal using said charging and said discharging of said second capacitor, and

The control signal is generated based on the compensated reference signal and the ramp signal.

19. The control method according to claim 18, wherein the control method further comprises:

a pulse signal is periodically generated based on the control signal to periodically turn on the first switch.

20. The control method according to claim 18, wherein the control method further comprises:

comparing the ramp signal on the second capacitor with the compensation reference signal to generate a first comparison signal;

comparing the ramp signal on the second capacitor with a periodic reference signal to generate a second comparison signal, and

The control signal is generated based on the first comparison signal and the second comparison signal.

21. The control method of claim 20, wherein the periodic reference signal is proportional to the input voltage.