CN119670645A - FPGA-based circuit automatic generation method and system - Google Patents
FPGA-based circuit automatic generation method and system Download PDFInfo
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Abstract
本发明涉及电路自动化生成技术领域，一种基于FPGA的电路自动化生成方法及系统，包括：将电路设计需求输入所述模块生成模型，得到初始电路功能模块集，对初始模块特性参数集进行归一化处理，得到标准模块特性参数集，将标准模块特性参数集输入模块拼接模型，得到模块拼接电路，根据HDL文件进行仿真测试，得到仿真测试结果，判断仿真测试结果是否符合仿真测试标准，若不符合，则进行模型调优，若符合，则根据HDL文件进行性能测试，得到性能测试结果，判断性能测试结果是否符合性能测试标准，若不符合，则对模块拼接模型进行模型调优，若符合，则根据HDL文件构建FPGA配置文件。本发明可解决电路设计周期长、效率低下的问题。
The present invention relates to the technical field of automatic circuit generation, and is a method and system for automatic circuit generation based on FPGA, comprising: inputting circuit design requirements into the module generation model to obtain an initial circuit function module set, normalizing the initial module characteristic parameter set to obtain a standard module characteristic parameter set, inputting the standard module characteristic parameter set into a module splicing model to obtain a module splicing circuit, performing simulation test according to an HDL file to obtain a simulation test result, judging whether the simulation test result meets the simulation test standard, if not, performing model tuning, if yes, performing performance test according to the HDL file to obtain a performance test result, judging whether the performance test result meets the performance test standard, if not, performing model tuning on the module splicing model, if yes, constructing an FPGA configuration file according to the HDL file. The present invention can solve the problems of long circuit design cycle and low efficiency.
Description
Technical Field
The invention relates to the technical field of automatic circuit generation, in particular to an automatic circuit generation method and system based on an FPGA.
Background
The current FPGA (Field Programmable GATE ARRAY) tool and EDA (Electronic Design Automation) tool mainly rely on engineers to manually input design codes or perform logic construction through a graphical interface in terms of circuit design, the process needs the engineers to have deep understanding on the hardware architecture and HDL (Hardware Description Language ) of the FPGA, and when designing complex circuits, a great deal of time is often required to debug and optimize, resulting in long design cycle and low efficiency.
Disclosure of Invention
The invention provides an automatic circuit generation method and system based on an FPGA, and mainly aims to solve the problems of long circuit design period and low efficiency.
In order to achieve the above object, the present invention provides an automatic circuit generating method based on FPGA, including:
Receiving a circuit design requirement input by a user, wherein the circuit design requirement refers to a circuit function, a performance index and a design constraint, and receiving a module generation model selected by the user;
Inputting the circuit design requirement into the module generation model to obtain an initial circuit function module set;
Acquiring an initial module characteristic parameter set corresponding to the initial circuit function module set, and carrying out normalization processing on the initial module characteristic parameter set to obtain a standard module characteristic parameter set;
inputting the standard module characteristic parameter set into a module splicing model which is trained in advance to obtain a module splicing circuit;
Constructing an HDL file according to the module splicing circuit, and performing simulation test according to the HDL file to obtain a simulation test result;
Judging whether the simulation test result accords with a preset simulation test standard or not;
If the simulation test result does not accord with the simulation test standard, performing model tuning on the module generation model and the module splicing model, and returning to the step of inputting the circuit design requirement into the module generation model;
If the simulation test result meets the simulation test standard, performing performance test according to the HDL file to obtain a performance test result;
judging whether the performance test result accords with a preset performance test standard or not;
If the performance test result does not accord with the performance test standard, performing model tuning on the module splicing model, and returning to the step of inputting the standard module characteristic parameter set into the module splicing model which is finished training in advance;
If the performance test result meets the preset performance test standard, constructing an FPGA configuration file according to the HDL file to complete automatic circuit generation based on the FPGA
Optionally, the acquiring the initial module characteristic parameter set corresponding to the initial circuit function module set includes:
sequentially extracting initial circuit function modules from the initial circuit function module set to acquire communication protocols, data flow directions, topological structures and time sequence relations of the initial circuit function modules;
And taking the communication protocol, the data flow direction, the topological structure and the time sequence relationship as initial module characteristic parameters of the initial circuit functional module, and collecting the initial module characteristic parameters of each initial circuit functional module to obtain an initial module characteristic parameter set.
Optionally, the normalizing the initial module characteristic parameter set to obtain a standard module characteristic parameter set includes:
The communication protocol and the data flow of each initial module characteristic parameter in the initial module characteristic parameter set are unified in representation form, and a standard communication protocol and a standard data flow are obtained;
Quantifying the time sequence relation in the characteristic parameters of the initial module to obtain a standard time sequence relation;
And taking a standard communication protocol, a standard data flow direction, a standard time sequence relation and a topological structure corresponding to the initial module characteristic parameters as the standard module characteristic parameters, and collecting the characteristic parameters of each standard module to obtain a standard module characteristic parameter set.
Optionally, the training process of the module stitching model includes:
Acquiring a training circuit function module set and a training module characteristic parameter set corresponding to the training circuit function module set;
Normalizing the training module characteristic parameter set to obtain a normalized training module characteristic parameter set, wherein the normalized training module characteristic parameter set comprises a training communication protocol, a training data flow direction, a training topological structure and a training time sequence relation corresponding to each normalized training module characteristic parameter;
Modeling according to the training topological structure to obtain a module node relation diagram, wherein nodes in the module node relation diagram represent training circuit functional modules;
sequentially extracting module nodes from the module node relation diagram, acquiring performance parameters of a training circuit functional module corresponding to the module nodes, and extracting training communication protocols corresponding to the module nodes from the normalized training module characteristic parameter set;
Taking the performance parameters of the training circuit function module corresponding to the module node and the training communication protocol as the node characteristics of the module node;
extracting training data flow direction and training time sequence relation of a training function module corresponding to the module node from the normalized training module characteristic parameter set, and taking the training data flow direction and training time sequence relation as edge characteristics of the module node;
Constructing a GNN model according to the module node relation diagram, the node characteristics and the edge characteristics;
Performing model iteration on the GNN model by using preset global delay, power consumption and resource occupation to obtain an iterative GNN model;
Identifying model performance of the iterative GNN model using a pre-built EDA tool;
judging whether the model performance accords with preset splicing performance or not;
If the model performance does not accord with the splicing performance, returning to the step of carrying out model iteration on the GNN model by utilizing the preset global delay, power consumption and resource occupation;
and if the model performance accords with the splicing performance, obtaining a module splicing model.
Optionally, the performing a simulation test according to the HDL file to obtain a simulation test result includes:
loading the HDL file into a simulation environment and loading a test vector;
And acquiring a simulation response under the excitation of the test vector, and taking the simulation response as a simulation test result.
Optionally, before the model tuning is performed on the module generating model and the module splicing model, the method further includes:
Performing error analysis on the simulation test result to obtain an error analysis log and error related data;
And determining a to-be-tuned optimal model according to the error analysis log and the error related data, wherein the to-be-tuned optimal model is a module generation model or a module splicing model.
Optionally, the performing model tuning on the module stitching model includes:
Acquiring a performance test analysis report, wherein the performance test analysis report comprises a time sequence report, a power consumption report and a resource occupation report;
and performing model tuning on the module splicing model according to the performance test analysis report.
Optionally, the constructing an FPGA configuration file according to the HDL file includes:
Adding necessary comments to the HDL file to obtain a comment HDL file;
And constructing an FPGA configuration file according to the annotation HDL file.
Optionally, the module generating model is a convolutional neural network, wherein the convolutional neural network can input logic structure characteristics, input and output characteristics, performance characteristics, power consumption characteristics, delay time and resource utilization characteristics of an initial circuit functional module and can output a circuit structure of the initial circuit functional module, and the module generating model comprises a calculation type module generating model, a storage type module generating model, a control type module generating model, a communication type module generating model, an encryption type module generating model and a digital signal processing type module generating model.
In order to achieve the above object, the present invention further provides an automatic circuit generating system based on FPGA, including:
the circuit function module set generating module is used for receiving circuit design requirements input by a user, wherein the circuit design requirements refer to circuit functions, performance indexes and design constraints, and receiving a module generating model selected by the user;
The circuit function module set splicing module is used for acquiring an initial module characteristic parameter set corresponding to the initial circuit function module set, normalizing the initial module characteristic parameter set to obtain a standard module characteristic parameter set;
The module splicing circuit verification optimizing module is used for constructing an HDL file according to the module splicing circuit, carrying out simulation test according to the HDL file to obtain a simulation test result, judging whether the simulation test result meets a preset simulation test standard, carrying out model tuning on the module generating model and the module splicing model if the simulation test result does not meet the simulation test standard, returning to the step of inputting the circuit design requirement into the module generating model, carrying out performance test according to the HDL file if the simulation test result meets the simulation test standard to obtain a performance test result, judging whether the performance test result meets the preset performance test standard, carrying out model tuning on the module splicing model if the performance test result does not meet the performance test standard, and returning to the step of inputting the standard module characteristic parameter set into the module splicing model which is pre-trained;
And the FPGA configuration file generation module is used for constructing an FPGA configuration file according to the HDL file if the performance test result accords with a preset performance test standard.
In order to solve the above-mentioned problems, the present invention also provides an electronic apparatus including:
And a processor executing the instructions stored in the memory to implement the FPGA-based circuit automation generation method.
In order to solve the above problems, the present invention also provides a computer-readable storage medium having at least one instruction stored therein, the at least one instruction being executed by a processor in an electronic device to implement the above-described FPGA-based circuit automation generation method.
In order to solve the problems described in the background art, an initial circuit function module set is firstly generated, then the initial circuit function module set is spliced to obtain a module spliced circuit, finally the module spliced circuit is subjected to verification optimization, in the process of generating the initial circuit function module set, the circuit design requirements input by a user are required to be received, wherein the circuit design requirements refer to circuit functions, performance indexes and design constraints, at the moment, a module generation model selected by the user is required to be received, the circuit design requirements are input into the module generation model to obtain the initial circuit function module set, and since the initial module characteristic parameter set corresponding to the initial circuit function module set is required to be spliced according to the initial module characteristic parameter set, the initial module characteristic parameter set is required to be obtained, and then normalized to obtain a standard module characteristic parameter set, at the moment, the standard module characteristic parameter set is input into a module spliced model which is finished in advance, and after the module spliced circuit is obtained, the module spliced circuit is required to be verified and optimized, and therefore, if the simulation module is required to be matched with the HDL (high-performance) is generated, the simulation result is required to meet the test result, and if the simulation result meets the test result is obtained, the simulation result is judged to be the HDL, and if the simulation result meets the test result is generated, and the simulation result is not met, and performing performance test according to the HDL file to obtain a performance test result, after finishing the simulation test, performing the performance test, firstly judging whether the performance test result accords with a preset performance test standard, performing model tuning on the module splicing model if the performance test result does not accord with the performance test standard, inputting the standard module characteristic parameter set into the module splicing model which is finished in advance, and constructing an FPGA configuration file according to the HDL file if the performance test result accords with the preset performance test standard to finish automatic circuit generation based on the FPGA. Therefore, the invention can solve the problems of long circuit design period and low efficiency.
Drawings
FIG. 1 is a schematic flow chart of an automatic circuit generating method based on FPGA according to an embodiment of the present invention;
FIG. 2 is a functional block diagram of an FPGA-based circuit automation system according to an embodiment of the present invention;
Fig. 3 is a schematic structural diagram of an electronic device for implementing the automatic circuit generating method based on FPGA according to an embodiment of the present invention.
Reference numerals illustrate:
1. Electronic equipment 10, a processor 11, a memory 12 and a bus.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The embodiment of the application provides a circuit automatic generation method based on an FPGA. The execution subject of the FPGA-based circuit automation generation method includes, but is not limited to, at least one of a server, a terminal, and the like, which can be configured to execute the method provided by the embodiment of the present application. In other words, the automatic circuit generating method based on the FPGA may be performed by software or hardware installed in a terminal device or a server device, and the software may be a blockchain platform. The server side comprises, but is not limited to, a single server, a server cluster, a cloud server or a cloud server cluster and the like.
Referring to fig. 1, a flow chart of an automatic circuit generating method based on FPGA according to an embodiment of the present invention is shown. In this embodiment, the automatic circuit generating method based on FPGA includes:
S1, receiving a circuit design requirement input by a user, wherein the circuit design requirement refers to a circuit function, a performance index and a design constraint, and receiving a module generation model selected by the user.
It is understood that the circuit design requirements refer to the requirements of the FPGA circuit design, including intended circuit functions (e.g., specific algorithms, specific communication protocols, etc.), performance metrics (e.g., clock frequency, power consumption requirements, etc.), design constraints (e.g., chip resource limitations, pin assignments, etc.).
Further, the circuit design requirements may be entered via a Graphical User Interface (GUI) that includes a function selection menu, a performance parameter input box, and a design constraint setting area.
In detail, in the function selection menu, detailed circuit function module type options (such as calculation modules with different precision, storage modules with various capacities and access speeds, interface modules with various communication protocols, and the like) and customized function input boxes can be provided, and a user can generally select or input descriptions to specify the required circuit function module type and overall function requirements. In the performance parameter input boxes, the user is allowed to input the performance indexes such as clock frequency range, power consumption budget, signal delay requirement and the like, and the performance parameter input boxes can set reasonable default values and provide prompt information to help the user to input correctly. In the design constraint setting area, a user may specify constraints such as FPGA chip model number (so that the tool generates an appropriate design based on chip resource constraints), pin assignment requirements (e.g., a particular signal must be assigned to a particular pin), etc. When the circuit design requirement is received, whether the circuit design requirement is complete and clear needs to be judged, and if the circuit design requirement is incomplete and clear, a user is prompted to supplement the circuit design requirement.
In the embodiment of the invention, the module generation model is a convolutional neural network, wherein the convolutional neural network can input logic structure characteristics, input and output characteristics, performance characteristics, power consumption characteristics, delay time and resource utilization characteristics of an initial circuit function module and can output a circuit structure of the initial circuit function module, and the module generation model comprises a calculation type module generation model, a storage type module generation model, a control type module generation model, a communication type module generation model, an encryption type module generation model and a digital signal processing type module generation model.
Further, the training process of the module generating the model comprises:
The method comprises the steps of obtaining a training module characteristic parameter set, wherein the training module characteristic parameter set comprises training logic structure characteristics, training input and output characteristics, training performance characteristics, training power consumption characteristics, training delay time, training resource utilization characteristics and a training circuit structure;
Inputting the training logic structure characteristics, the training input and output characteristics, the training performance characteristics, the training power consumption characteristics, the training delay time and the training resource utilization characteristics into a pre-constructed original generation model to obtain an iterative circuit structure;
identifying iteration time sequence performance, iteration power consumption and iteration resource utilization rate of the iteration circuit structure;
recognizing training time sequence performance, training power consumption and training resource utilization rate of the training circuit structure;
calculating multi-objective loss function values of the iteration time sequence performance, the iteration power consumption and the iteration resource utilization rate, and the training time sequence performance, the training power consumption and the training resource utilization rate;
and according to the multi-objective loss function value, carrying out parameter adjustment on the original generation model by utilizing a pre-constructed gradient descent algorithm until the multi-objective loss function value accords with a preset loss function threshold value, and obtaining a module generation model.
The training logic structure feature, the training input/output feature, the training performance feature, the training power consumption feature, the training delay time, the training resource utilization feature and the training circuit structure refer to the logic structure feature, the input/output feature, the performance feature, the power consumption feature, the delay time, the resource utilization feature and the circuit structure for training respectively. The iterative circuit structure refers to a circuit structure output in a training process. The iterative time sequence performance, the iterative power consumption and the iterative resource utilization rate refer to the time sequence performance, the power consumption and the resource utilization rate of the iterative circuit structure respectively. The training time sequence performance, the training power consumption and the training resource utilization rate refer to the time sequence performance, the power consumption and the resource utilization rate of the training circuit structure respectively. The multi-objective loss function value refers to a performance parameter difference between the iterative circuit structure and the training circuit structure.
Further, the circuit structure is expressed in a hardware description language or a logic topological graph form and comprises information such as connection relation, resource allocation and time sequence information among initial circuit function modules. The training time sequence performance, the training power consumption, the training resource utilization rate, the iteration time sequence performance, the iteration power consumption and the iteration resource utilization rate can be monitored by using an EDA tool. Firstly, calculating errors of iteration time sequence performance and training time sequence performance, errors of iteration power consumption and training power consumption and errors of iteration resource utilization rate and training resource utilization rate, and then synthesizing the errors into a multi-objective loss function.
It can be appreciated that the parameter adjustment includes adjustment of parameters such as convolution kernel weights, bias terms, and the like, and the dynamic adjustment of the super-parameters can accelerate convergence of the original generated model.
S2, inputting the circuit design requirement into the module generation model to obtain an initial circuit function module set.
It is understood that the initial set of circuit function modules refers to a set of circuit function modules that meet the circuit design requirements. The module generation model can generate corresponding circuit function module design schemes according to circuit design requirements input by a user, and each circuit function module design scheme meets circuit functions, performance indexes and design constraints in the circuit design requirements. For example, when a high-speed computing module is generated, a module generating model generates a design module with proper operation capability, power consumption and time delay requirements, and the design module comprises a logic gate model selection mode and a logic gate connection mode.
S3, acquiring an initial module characteristic parameter set corresponding to the initial circuit function module set, and carrying out normalization processing on the initial module characteristic parameter set to obtain a standard module characteristic parameter set.
It is understood that the initial module characteristic parameter set refers to a characteristic parameter set of each initial circuit function module. The normalization process refers to converting the initial set of module characteristic parameters into a unified standardized representation. The standard module characteristic parameter set indicates an standardized initial module characteristic parameter set.
In the embodiment of the present invention, the obtaining the initial module characteristic parameter set corresponding to the initial circuit function module set includes:
sequentially extracting initial circuit function modules from the initial circuit function module set to acquire communication protocols, data flow directions, topological structures and time sequence relations of the initial circuit function modules;
And taking the communication protocol, the data flow direction, the topological structure and the time sequence relationship as initial module characteristic parameters of the initial circuit functional module, and collecting the initial module characteristic parameters of each initial circuit functional module to obtain an initial module characteristic parameter set.
Further, the communication protocol refers to a data transmission protocol between the initial circuit function modules, such as UART, SPI or custom protocol. The data flow refers to a data flow path between the initial circuit functional modules, and comprises an input-output relationship and a multi-module cascade relationship. The topological structure refers to a global topological relation diagram of the initial circuit functional modules and is used for describing the connection mode and the dependency relation among the initial circuit functional modules. The timing relationship refers to timing dependencies between functional blocks of the initial circuit, such as a clock synchronization mechanism for data transfer across blocks.
In the embodiment of the present invention, the normalizing the initial module characteristic parameter set to obtain a standard module characteristic parameter set includes:
The communication protocol and the data flow of each initial module characteristic parameter in the initial module characteristic parameter set are unified in representation form, and a standard communication protocol and a standard data flow are obtained;
Quantifying the time sequence relation in the characteristic parameters of the initial module to obtain a standard time sequence relation;
And taking a standard communication protocol, a standard data flow direction, a standard time sequence relation and a topological structure corresponding to the initial module characteristic parameters as the standard module characteristic parameters, and collecting the characteristic parameters of each standard module to obtain a standard module characteristic parameter set.
S4, inputting the standard module characteristic parameter set into a module splicing model which is trained in advance, and obtaining a module splicing circuit.
Further, the module splicing model refers to a model for splicing the initial circuit function module set according to the standard module characteristic parameter set. The module splicing model can connect the generated initial circuit function module set according to the learned optimal splicing rule to form a complete FPGA circuit design, and the generated FPGA circuit design is output in a standard hardware description language (such as Verilog or VHDL) or a specific FPGA configuration file format. The module splicing circuit is a splicing circuit obtained after the module splicing model splices the initial circuit function module set.
In the embodiment of the invention, the training process of the module splicing model comprises the following steps:
Acquiring a training circuit function module set and a training module characteristic parameter set corresponding to the training circuit function module set;
Normalizing the training module characteristic parameter set to obtain a normalized training module characteristic parameter set, wherein the normalized training module characteristic parameter set comprises a training communication protocol, a training data flow direction, a training topological structure and a training time sequence relation corresponding to each normalized training module characteristic parameter;
Modeling according to the training topological structure to obtain a module node relation diagram, wherein nodes in the module node relation diagram represent training circuit functional modules;
sequentially extracting module nodes from the module node relation diagram, acquiring performance parameters of a training circuit functional module corresponding to the module nodes, and extracting training communication protocols corresponding to the module nodes from the normalized training module characteristic parameter set;
Taking the performance parameters of the training circuit function module corresponding to the module node and the training communication protocol as the node characteristics of the module node;
extracting training data flow direction and training time sequence relation of a training function module corresponding to the module node from the normalized training module characteristic parameter set, and taking the training data flow direction and training time sequence relation as edge characteristics of the module node;
Constructing a GNN model according to the module node relation diagram, the node characteristics and the edge characteristics;
Performing model iteration on the GNN model by using preset global delay, power consumption and resource occupation to obtain an iterative GNN model;
Identifying model performance of the iterative GNN model using a pre-built EDA tool;
judging whether the model performance accords with preset splicing performance or not;
If the model performance does not accord with the splicing performance, returning to the step of carrying out model iteration on the GNN model by utilizing the preset global delay, power consumption and resource occupation;
and if the model performance accords with the splicing performance, obtaining a module splicing model.
It can be understood that the training circuit function module set refers to a circuit function module for training the module splicing model, and the training module characteristic parameter set refers to a characteristic parameter set of each training circuit function module. The training communication protocol, the training data flow direction, the training topological structure and the training time sequence relation refer to the communication protocol, the data flow direction, the topological structure and the time sequence relation of the training circuit functional module respectively. The module node relation graph refers to a node relation graph representing a training topology. The performance parameter may be a delay and a power consumption of the training circuit function module. The GNN model refers to a graph neural network model, is a deep learning model and is specially used for processing graph structure data, an optimal circuit splicing mode is learned by minimizing a loss function (such as a loss function based on the performance of a spliced circuit), and meanwhile, a verification set can be used for adjusting GNN model parameters, so that the generalization capability of the GNN model for module splicing under different circuit design scenes is improved. The splice performance refers to global delay, power consumption and resource occupation expected by the GNN model.
S5, constructing an HDL file according to the module splicing circuit, and performing simulation test according to the HDL file to obtain a simulation test result.
It can be appreciated that the HDL (Hardware Description Language) files refer to files describing the structure, function and behavior of the module splicing circuit, and the design and verification of the electronic system can be more efficiently and accurately performed through the HDL files.
Further, the module splicing circuit outputs through a standardized Hardware Description Language (HDL), simultaneously generates an FPGA configuration file, and then verifies and optimizes by using a simulation tool and a performance analysis tool to finally generate a complete FPGA design and verification report meeting the requirements.
In the embodiment of the present invention, the performing a simulation test according to the HDL file to obtain a simulation test result includes:
loading the HDL file into a simulation environment and loading a test vector;
And acquiring a simulation response under the excitation of the test vector, and taking the simulation response as a simulation test result.
It is understood that the simulation response refers to output signals and state changes of the module splicing circuit under the excitation of the test vector, such as output digital signals, output analog signals, timing information, error and warning information, and the like.
S6, judging whether the simulation test result meets a preset simulation test standard.
It can be understood that the simulation test standard refers to a preset simulation response standard of the module splicing circuit.
And if the simulation test result does not accord with the simulation test standard, executing S7, and performing model tuning on the module generation model and the module splicing model.
In the embodiment of the present invention, before the model tuning is performed on the module generating model and the module splicing model, the method further includes:
Performing error analysis on the simulation test result to obtain an error analysis log and error related data;
And determining a to-be-tuned optimal model according to the error analysis log and the error related data, wherein the to-be-tuned optimal model is a module generation model or a module splicing model.
It is understood that the error analysis log refers to a detailed document that records errors, anomalies, or unexpected behaviors found in simulation test results, such as a manifestation of the errors, a point in time when the errors occur, a possible type of error, an error occurrence location, a cause of the error occurrence, an error repair suggestion, and so on. The error related data refers to data and information directly related to errors in the simulation test process, such as simulation test data, signal waveform diagrams, resource use condition data, time sequence analysis reports and the like. And determining whether the module generation model needs to be continuously tuned or the module splicing model needs to be continuously tuned by analyzing the error analysis log and the error related data.
And returning to the step of inputting the circuit design requirements into the module generation model.
It can be appreciated that when tuning of the module generation model and the module splicing model is completed, the module generation model needs to be reused to generate an initial circuit function module set and the module splicing model needs to be utilized to generate a module splicing circuit.
And if the simulation test result meets the simulation test standard, executing S8, and performing performance test according to the HDL file to obtain a performance test result.
It can be understood that the performance test result includes a time sequence test result, a power consumption test result and a resource occupation test result of the module splicing circuit.
And S9, judging whether the performance test result meets a preset performance test standard or not.
It should be appreciated that the performance test criteria refer to the timing, power consumption, and resource occupancy criteria set for the module stitching circuit. The integrated tool provided by the FPGA manufacturer can be utilized to carry out integrated analysis on the module splicing circuit to obtain performance data such as time sequence information, power consumption information and the like of the module splicing circuit, and if the performance requirements input by a user are not met, an optimization algorithm (such as a layout and wiring optimization algorithm, a logic optimization algorithm and the like) is adopted to adjust the circuit design. For example, by adjusting the number of logic gate stages on critical paths in a circuit to improve timing performance or by optimizing the use of memory cells to reduce power consumption, etc., the optimization process may be iterated until the circuit design meets all performance metrics and design constraints.
And if the performance test result does not accord with the performance test standard, executing S10, performing model tuning on the module splicing model, and returning to the step of inputting the standard module characteristic parameter set into the module splicing model which is finished training in advance.
Further, when the performance test result does not meet the performance test standard, the module splicing model can be directly optimized, and the standard module characteristic parameter set is directly returned to the step of inputting the standard module characteristic parameter set into the module splicing model which is trained in advance.
In the embodiment of the present invention, the performing model tuning on the module splicing model includes:
Acquiring a performance test analysis report, wherein the performance test analysis report comprises a time sequence report, a power consumption report and a resource occupation report;
and performing model tuning on the module splicing model according to the performance test analysis report.
It can be understood that the module splicing model can be iteratively optimized by taking the time sequence report, the power consumption report and the resource occupation report as the optimization investigation dimension.
And if the performance test result meets the preset performance test standard, executing S11, and constructing an FPGA configuration file according to the HDL file to complete automatic generation of the circuit based on the FPGA.
In the embodiment of the present invention, the constructing an FPGA configuration file according to the HDL file includes:
Adding necessary comments to the HDL file to obtain a comment HDL file;
And constructing an FPGA configuration file according to the annotation HDL file.
In order to solve the problems described in the background art, an initial circuit function module set is firstly generated, then the initial circuit function module set is spliced to obtain a module spliced circuit, finally the module spliced circuit is subjected to verification optimization, in the process of generating the initial circuit function module set, the circuit design requirements input by a user are required to be received, wherein the circuit design requirements refer to circuit functions, performance indexes and design constraints, at the moment, a module generation model selected by the user is required to be received, the circuit design requirements are input into the module generation model to obtain the initial circuit function module set, and since the initial module characteristic parameter set corresponding to the initial circuit function module set is required to be spliced according to the initial module characteristic parameter set, the initial module characteristic parameter set is required to be obtained, and then normalized to obtain a standard module characteristic parameter set, at the moment, the standard module characteristic parameter set is input into a module spliced model which is finished in advance, and after the module spliced circuit is obtained, the module spliced circuit is required to be verified and optimized, and therefore, if the simulation module is required to be matched with the HDL (high-performance) is generated, the simulation result is required to meet the test result, and if the simulation result meets the test result is obtained, the simulation result is judged to be the HDL, and if the simulation result meets the test result is generated, and the simulation result is not met, and performing performance test according to the HDL file to obtain a performance test result, after finishing the simulation test, performing the performance test, firstly judging whether the performance test result accords with a preset performance test standard, performing model tuning on the module splicing model if the performance test result does not accord with the performance test standard, inputting the standard module characteristic parameter set into the module splicing model which is finished in advance, and constructing an FPGA configuration file according to the HDL file if the performance test result accords with the preset performance test standard to finish automatic circuit generation based on the FPGA. Therefore, the invention can solve the problems of long circuit design period and low efficiency.
Fig. 2 is a functional block diagram of an FPGA-based circuit automation system according to an embodiment of the present invention.
The FPGA-based circuit automation generation system 100 of the present invention may be installed in an electronic device. Depending on the functions implemented, the FPGA-based circuit automation generation system 100 may include a circuit function module set generation module 101, a circuit function module set stitching module 102, a module stitching circuit verification optimization module 103, and an FPGA configuration file generation module 104. The module of the invention, which may also be referred to as a unit, refers to a series of computer program segments, which are stored in the memory of the electronic device, capable of being executed by the processor of the electronic device and of performing a fixed function.
The circuit function module set generating module 101 is configured to receive a circuit design requirement input by a user, where the circuit design requirement refers to a circuit function, a performance index and a design constraint, and receive a module generating model selected by the user;
The circuit function module set splicing module 102 is configured to obtain an initial module characteristic parameter set corresponding to the initial circuit function module set, normalize the initial module characteristic parameter set to obtain a standard module characteristic parameter set, input the standard module characteristic parameter set into a module splicing model which is trained in advance, and obtain a module splicing circuit;
The module splicing circuit verification optimizing module 103 is used for constructing an HDL file according to the module splicing circuit, carrying out simulation test according to the HDL file to obtain a simulation test result, judging whether the simulation test result meets a preset simulation test standard, carrying out model tuning on the module generating model and the module splicing model if the simulation test result does not meet the simulation test standard, returning to the step of inputting the circuit design requirement into the module generating model, carrying out performance test according to the HDL file if the simulation test result meets the simulation test standard to obtain a performance test result, judging whether the performance test result meets the preset performance test standard, carrying out model tuning on the module splicing model if the performance test result does not meet the performance test standard, and returning to the step of inputting the standard module characteristic parameter set into the module splicing model which is trained in advance;
the FPGA configuration file generating module 104 is configured to construct an FPGA configuration file according to the HDL file if the performance test result meets a preset performance test standard.
In detail, the modules in the FPGA-based circuit automation generating system 100 in the embodiment of the present invention use the same technical means as the FPGA-based circuit automation generating method described in fig. 1, and can generate the same technical effects, which are not described herein.
Fig. 3 is a schematic structural diagram of an electronic device for implementing an automatic circuit generating method based on FPGA according to an embodiment of the present invention.
The electronic device 1 may comprise a processor 10, a memory 11 and a bus 12, and may further comprise a computer program stored in the memory 11 and executable on the processor 10, such as an FPGA-based circuit automation generation method program.
The memory 11 includes at least one type of readable storage medium, including flash memory, a mobile hard disk, a multimedia card, a card memory (e.g., SD or DX memory, etc.), a magnetic memory, a magnetic disk, an optical disk, etc. The memory 11 may in some embodiments be an internal storage unit of the electronic device 1, such as a removable hard disk of the electronic device 1. The memory 11 may in other embodiments also be an external storage device of the electronic device 1, such as a plug-in mobile hard disk, a smart memory card (SMART MEDIA CARD, SMC), a Secure Digital (SD) card, a flash memory card (FLASH CARD) or the like, which are provided on the electronic device 1. Further, the memory 11 further comprises an internal storage unit of the electronic device 1, and also comprises an external storage device. The memory 11 may be used not only for storing application software installed in the electronic device 1 and various types of data, such as codes of an automatic circuit generating method program based on FPGA, but also for temporarily storing data that has been output or is to be output.
The processor 10 may be comprised of integrated circuits in some embodiments, for example, a single packaged integrated circuit, or may be comprised of multiple integrated circuits packaged with the same or different functions, including one or more central processing units (Central Processing unit, CPU), microprocessors, digital processing chips, graphics processors, combinations of various control chips, and the like. The processor 10 is a Control Unit (Control Unit) of the electronic device, connects respective components of the entire electronic device using various interfaces and lines, executes or executes programs or modules (for example, FPGA-based circuit automation generation method programs, etc.) stored in the memory 11, and invokes data stored in the memory 11 to perform various functions of the electronic device 1 and process the data.
The bus 12 may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, among others. The bus 12 may be divided into an address bus, a data bus, a control bus, etc. The bus 12 is arranged to enable a connection communication between the memory 11 and at least one processor 10 etc.
Fig. 3 shows only an electronic device with components, it being understood by a person skilled in the art that the structure shown in fig. 3 does not constitute a limitation of the electronic device 1, and may comprise fewer or more components than shown, or may combine certain components, or may be arranged in different components.
For example, although not shown, the electronic device 1 may further include a power source (such as a battery) for supplying power to each component, and preferably, the power source may be logically connected to the at least one processor 10 through a power management device, so that functions of charge management, discharge management, power consumption management, and the like are implemented through the power management device. The power supply may also include one or more of any of a direct current or alternating current power supply, recharging device, power failure detection circuit, power converter or inverter, power status indicator, etc. The electronic device 1 may further include various sensors, bluetooth modules, wi-Fi modules, etc., which will not be described herein.
Further, the electronic device 1 may also comprise a network interface, optionally the network interface may comprise a wired interface and/or a wireless interface (e.g. WI-FI interface, bluetooth interface, etc.), typically used for establishing a communication connection between the electronic device 1 and other electronic devices.
The electronic device 1 may optionally further comprise a user interface, which may be a Display, an input unit, such as a Keyboard (Keyboard), or a standard wired interface, a wireless interface. Alternatively, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, an OLED (Organic Light-Emitting Diode) touch, or the like. The display may also be referred to as a display screen or display unit, as appropriate, for displaying information processed in the electronic device 1 and for displaying a visual user interface.
The FPGA-based circuit automation generation method program stored in the memory 11 of the electronic device 1 is a combination of a plurality of instructions, which when executed in the processor 10, can implement:
Receiving a circuit design requirement input by a user, wherein the circuit design requirement refers to a circuit function, a performance index and a design constraint, and receiving a module generation model selected by the user;
Inputting the circuit design requirement into the module generation model to obtain an initial circuit function module set;
Acquiring an initial module characteristic parameter set corresponding to the initial circuit function module set, and carrying out normalization processing on the initial module characteristic parameter set to obtain a standard module characteristic parameter set;
inputting the standard module characteristic parameter set into a module splicing model which is trained in advance to obtain a module splicing circuit;
Constructing an HDL file according to the module splicing circuit, and performing simulation test according to the HDL file to obtain a simulation test result;
Judging whether the simulation test result accords with a preset simulation test standard or not;
If the simulation test result does not accord with the simulation test standard, performing model tuning on the module generation model and the module splicing model, and returning to the step of inputting the circuit design requirement into the module generation model;
If the simulation test result meets the simulation test standard, performing performance test according to the HDL file to obtain a performance test result;
judging whether the performance test result accords with a preset performance test standard or not;
If the performance test result does not accord with the performance test standard, performing model tuning on the module splicing model, and returning to the step of inputting the standard module characteristic parameter set into the module splicing model which is finished training in advance;
If the performance test result meets the preset performance test standard, constructing an FPGA configuration file according to the HDL file, and completing automatic circuit generation based on the FPGA.
Specifically, the specific implementation method of the above instructions by the processor 10 may refer to descriptions of related steps in the corresponding embodiments of fig. 1 to 3, which are not repeated herein.
Further, the modules/units integrated in the electronic device 1 may be stored in a computer readable storage medium if implemented in the form of software functional units and sold or used as separate products. The computer readable storage medium may be volatile or nonvolatile. For example, the computer readable medium may include any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM).
The present invention also provides a computer readable storage medium storing a computer program which, when executed by a processor of an electronic device, can implement:
Receiving a circuit design requirement input by a user, wherein the circuit design requirement refers to a circuit function, a performance index and a design constraint, and receiving a module generation model selected by the user;
Inputting the circuit design requirement into the module generation model to obtain an initial circuit function module set;
Acquiring an initial module characteristic parameter set corresponding to the initial circuit function module set, and carrying out normalization processing on the initial module characteristic parameter set to obtain a standard module characteristic parameter set;
inputting the standard module characteristic parameter set into a module splicing model which is trained in advance to obtain a module splicing circuit;
Constructing an HDL file according to the module splicing circuit, and performing simulation test according to the HDL file to obtain a simulation test result;
Judging whether the simulation test result accords with a preset simulation test standard or not;
If the simulation test result does not accord with the simulation test standard, performing model tuning on the module generation model and the module splicing model, and returning to the step of inputting the circuit design requirement into the module generation model;
If the simulation test result meets the simulation test standard, performing performance test according to the HDL file to obtain a performance test result;
judging whether the performance test result accords with a preset performance test standard or not;
If the performance test result does not accord with the performance test standard, performing model tuning on the module splicing model, and returning to the step of inputting the standard module characteristic parameter set into the module splicing model which is finished training in advance;
If the performance test result meets the preset performance test standard, constructing an FPGA configuration file according to the HDL file, and completing automatic circuit generation based on the FPGA.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus, system and method may be implemented in other manners. For example, the system embodiments described above are merely illustrative, and there may be additional divisions of a practical implementation.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units can be realized in a form of hardware or a form of hardware and a form of software functional modules.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.
Finally, it should be noted that the above-mentioned embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications and equivalents may be made to the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention.
Claims (10)
1. An automatic circuit generation method based on an FPGA, which is characterized by comprising the following steps:
Receiving a circuit design requirement input by a user, wherein the circuit design requirement refers to a circuit function, a performance index and a design constraint, and receiving a module generation model selected by the user;
Inputting the circuit design requirement into the module generation model to obtain an initial circuit function module set;
Acquiring an initial module characteristic parameter set corresponding to the initial circuit function module set, and carrying out normalization processing on the initial module characteristic parameter set to obtain a standard module characteristic parameter set;
inputting the standard module characteristic parameter set into a module splicing model which is trained in advance to obtain a module splicing circuit;
Constructing an HDL file according to the module splicing circuit, and performing simulation test according to the HDL file to obtain a simulation test result;
Judging whether the simulation test result accords with a preset simulation test standard or not;
If the simulation test result does not accord with the simulation test standard, performing model tuning on the module generation model and the module splicing model, and returning to the step of inputting the circuit design requirement into the module generation model;
If the simulation test result meets the simulation test standard, performing performance test according to the HDL file to obtain a performance test result;
judging whether the performance test result accords with a preset performance test standard or not;
If the performance test result does not accord with the performance test standard, performing model tuning on the module splicing model, and returning to the step of inputting the standard module characteristic parameter set into the module splicing model which is finished training in advance;
If the performance test result meets the preset performance test standard, constructing an FPGA configuration file according to the HDL file, and completing automatic circuit generation based on the FPGA.
2. The method for automatically generating a circuit based on an FPGA of claim 1, wherein the obtaining the initial module characteristic parameter set corresponding to the initial circuit function module set includes:
sequentially extracting initial circuit function modules from the initial circuit function module set to acquire communication protocols, data flow directions, topological structures and time sequence relations of the initial circuit function modules;
And taking the communication protocol, the data flow direction, the topological structure and the time sequence relationship as initial module characteristic parameters of the initial circuit functional module, and collecting the initial module characteristic parameters of each initial circuit functional module to obtain an initial module characteristic parameter set.
3. The automatic circuit generating method based on FPGA of claim 2, wherein normalizing the initial module characteristic parameter set to obtain a standard module characteristic parameter set includes:
The communication protocol and the data flow of each initial module characteristic parameter in the initial module characteristic parameter set are unified in representation form, and a standard communication protocol and a standard data flow are obtained;
Quantifying the time sequence relation in the characteristic parameters of the initial module to obtain a standard time sequence relation;
And taking a standard communication protocol, a standard data flow direction, a standard time sequence relation and a topological structure corresponding to the initial module characteristic parameters as the standard module characteristic parameters, and collecting the characteristic parameters of each standard module to obtain a standard module characteristic parameter set.
4. The automatic circuit generating method based on the FPGA of claim 1, wherein the training process of the module splicing model comprises:
Acquiring a training circuit function module set and a training module characteristic parameter set corresponding to the training circuit function module set;
Normalizing the training module characteristic parameter set to obtain a normalized training module characteristic parameter set, wherein the normalized training module characteristic parameter set comprises a training communication protocol, a training data flow direction, a training topological structure and a training time sequence relation corresponding to each normalized training module characteristic parameter;
Modeling according to the training topological structure to obtain a module node relation diagram, wherein nodes in the module node relation diagram represent training circuit functional modules;
sequentially extracting module nodes from the module node relation diagram, acquiring performance parameters of a training circuit functional module corresponding to the module nodes, and extracting training communication protocols corresponding to the module nodes from the normalized training module characteristic parameter set;
Taking the performance parameters of the training circuit function module corresponding to the module node and the training communication protocol as the node characteristics of the module node;
extracting training data flow direction and training time sequence relation of a training function module corresponding to the module node from the normalized training module characteristic parameter set, and taking the training data flow direction and training time sequence relation as edge characteristics of the module node;
Constructing a GNN model according to the module node relation diagram, the node characteristics and the edge characteristics;
Performing model iteration on the GNN model by using preset global delay, power consumption and resource occupation to obtain an iterative GNN model;
Identifying model performance of the iterative GNN model using a pre-built EDA tool;
judging whether the model performance accords with preset splicing performance or not;
If the model performance does not accord with the splicing performance, returning to the step of carrying out model iteration on the GNN model by utilizing the preset global delay, power consumption and resource occupation;
and if the model performance accords with the splicing performance, obtaining a module splicing model.
5. The automatic circuit generating method based on the FPGA of claim 1, wherein the performing the simulation test according to the HDL file to obtain a simulation test result includes:
loading the HDL file into a simulation environment and loading a test vector;
And acquiring a simulation response under the excitation of the test vector, and taking the simulation response as a simulation test result.
6. The method for automatically generating a circuit based on an FPGA of claim 5, wherein before the model tuning is performed on the module generating model and the module splicing model, the method further comprises:
Performing error analysis on the simulation test result to obtain an error analysis log and error related data;
And determining a to-be-tuned optimal model according to the error analysis log and the error related data, wherein the to-be-tuned optimal model is a module generation model or a module splicing model.
7. The automatic circuit generating method based on FPGA of claim 6, wherein said model tuning the module splicing model comprises:
Acquiring a performance test analysis report, wherein the performance test analysis report comprises a time sequence report, a power consumption report and a resource occupation report;
and performing model tuning on the module splicing model according to the performance test analysis report.
8. The method for automatically generating an FPGA-based circuit according to claim 7, wherein said constructing an FPGA configuration file from said HDL file comprises:
Adding necessary comments to the HDL file to obtain a comment HDL file;
And constructing an FPGA configuration file according to the annotation HDL file.
9. The method for automatically generating a circuit based on an FPGA according to claim 8, wherein the module generating model is a convolutional neural network, wherein the convolutional neural network can input logic structure characteristics, input/output characteristics, performance characteristics, power consumption characteristics, delay time and resource utilization characteristics of an initial circuit function module and can output a circuit structure of the initial circuit function module, and the module generating model comprises a calculation type module generating model, a storage type module generating model, a control type module generating model, a communication type module generating model, an encryption type module generating model and a digital signal processing type module generating model.
10. An FPGA-based circuit automation generation system, the system comprising:
the circuit function module set generating module is used for receiving circuit design requirements input by a user, wherein the circuit design requirements refer to circuit functions, performance indexes and design constraints, and receiving a module generating model selected by the user;
The circuit function module set splicing module is used for acquiring an initial module characteristic parameter set corresponding to the initial circuit function module set, normalizing the initial module characteristic parameter set to obtain a standard module characteristic parameter set;
The module splicing circuit verification optimizing module is used for constructing an HDL file according to the module splicing circuit, carrying out simulation test according to the HDL file to obtain a simulation test result, judging whether the simulation test result meets a preset simulation test standard, carrying out model tuning on the module generating model and the module splicing model if the simulation test result does not meet the simulation test standard, returning to the step of inputting the circuit design requirement into the module generating model, carrying out performance test according to the HDL file if the simulation test result meets the simulation test standard to obtain a performance test result, judging whether the performance test result meets the preset performance test standard, carrying out model tuning on the module splicing model if the performance test result does not meet the performance test standard, and returning to the step of inputting the standard module characteristic parameter set into the module splicing model which is pre-trained;
And the FPGA configuration file generation module is used for constructing an FPGA configuration file according to the HDL file if the performance test result accords with a preset performance test standard.
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