CN119675653A - Method for eliminating burrs generated by asynchronous reset, FIFO circuit, chip and electronic device - Google Patents

Abstract

The present application provides a method for eliminating burrs generated by asynchronous reset, a FIFO circuit, a chip and an electronic device. The method includes determining a period selection signal based on the burr duration that needs to be shielded for the reset burr of the asynchronous FIFO reset signal; delaying the asynchronous FIFO reset signal through a register to obtain a delayed FIFO reset signal; a first multiplexer selectively outputs the delayed FIFO reset signal based on the shielding selection signal to obtain a first output signal and a second output signal; determining a transient signal based on the generation mechanism of the first output signal and the asynchronous FIFO output signal; determining a way of performing a first AND logic operation on the second output signal and/or the asynchronous FIFO reset signal based on the shielding selection signal to obtain a first AND logic output signal; a second multiplexer selectively outputs the first AND logic output signal based on the shielding selection signal to obtain a shielding signal; and performing a second AND logic operation on the shielding signal and the transient signal to obtain a burr-free output signal.

Description

Method for eliminating burrs generated by asynchronous reset, FIFO circuit, chip and electronic equipment

Technical Field

The present application relates to the field of signal processing technologies, and in particular, to a method for eliminating burrs generated by asynchronous reset, a FIFO circuit, a chip, and an electronic device.

Background

Reset signals are an essential component of existing chips, and reset can change the chip circuitry from an unknown state to a known, deterministic state. Asynchronous reset does not need to insert extra logic like synchronous reset, reduces the consumption of resources, and becomes a widely used reset design in digital circuit design. Asynchronous reset may also pose a potential risk because no clock is required and the clock has no fixed phase relationship. For example, in a typical asynchronous FIFO (FIRST IN FIRST Out) design, to maximize FIFO performance, an empty signal (null signal) and a Full signal (Full signal) are typically used as output signals (valid signal) outputs, and the empty signal and Full signal are generated by FIFO read-write pointer comparison, which is a combinational logic design. If the FIFO depth is deep, the read-write pointer is typically a multi-bit signal. When asynchronous reset occurs, because the placement position, path delay and possible combination logic delay of each bit of read-write pointer register are different, the time for reaching the comparison logic of the FIFO empty signal and the full signal is sequential, competition and risk phenomena can occur, and the valid signal is further caused to generate burr risk. If the burr is picked up by the downstream module it is likely to cause the path to hang up.

Disclosure of Invention

The embodiment of the application aims to provide a method for eliminating burrs generated by asynchronous reset, a FIFO circuit, a chip and electronic equipment, and the method is used for solving the problem that output signals generate burrs caused by asynchronous reset signals in the asynchronous FIFO circuit.

The embodiment of the application adopts the following technical scheme that the method for eliminating burrs generated by asynchronous reset is applied to an asynchronous FIFO circuit and comprises the following steps:

determining a period selection signal based on a glitch duration for which a reset glitch of the asynchronous FIFO reset signal is to be masked;

Based on the period selection signal, carrying out delay processing on the asynchronous FIFO reset signal through a register to obtain a delay FIFO reset signal corresponding to the current period selection signal;

The first multiplexer selects and outputs the delay FIFO reset signal based on the shielding selection signal to obtain a first output signal and a second output signal;

Determining a transient signal of the asynchronous FIFO based on the first output signal and a generation mechanism of the asynchronous FIFO output signal;

Determining a mode of performing a first AND logic operation on the second output signal and/or the asynchronous FIFO reset signal based on the mask selection signal to obtain a first AND logic output signal;

The second multiplexer selects and outputs the first and logic output signals based on the shielding selection signal to obtain a shielding signal;

And performing a second AND logic operation on the shielding signal and the transient signal to obtain a burr-free output signal of the asynchronous FIFO.

In some embodiments, delaying the asynchronous FIFO reset signal by a register based on the period select signal comprises:

determining a number of required registers based on the period selection signal, wherein the number of registers is the same as the value of the period selection signal;

And carrying out delay processing on the asynchronous FIFO reset signal through the determined number of the registers.

In some embodiments, the first multiplexer selectively outputs the delay FIFO reset signal based on the mask select signal to obtain a first output signal and a second output signal, comprising:

When the reset burr of the asynchronous FIFO reset signal is a rising edge reset burr, determining the shielding selection signal as a first shielding selection signal;

Selecting and outputting a delay FIFO reset signal based on the first shielding selection signal to obtain a third output signal and a fourth output signal, wherein the third output signal is one of the first output signals, and the fourth output signal is one of the second output signals;

When the reset burr of the asynchronous FIFO reset signal is a falling edge reset burr, determining the shielding selection signal as a second shielding selection signal;

And selectively outputting a delay FIFO reset signal based on the second shielding selection signal to obtain a fifth output signal and a sixth output signal, wherein the fifth output signal is one of the first output signals, and the sixth output signal is one of the second output signals.

In some embodiments, determining a manner of performing a first and logic operation on the second output signal and/or the asynchronous FIFO reset signal based on the mask select signal, resulting in a first and logic output signal, comprises:

performing a first operation based on the first mask select signal, the first operation comprising:

performing AND logic operation on the fourth output signal and the asynchronous FIFO reset signal to obtain a first position shielding signal;

performing a second operation based on the second mask select signal, the second operation comprising:

Determining the asynchronous FIFO reset signal as a second position mask signal;

Performing a third operation if the mask select signal is a third mask select signal, wherein the third mask select signal includes the first mask select signal and the second mask select signal;

The third operation includes performing an AND logic operation on the first location mask signal and the asynchronous FIFO reset signal to obtain a third location mask signal.

In some embodiments, the second multiplexer selectively outputs the first and logic output signals based on the mask select signal to obtain a mask signal, including:

a second multiplexer determining the first position mask signal as the mask signal based on the first mask select signal;

A second multiplexer determining the second position mask signal as the mask signal based on the second mask select signal;

the second multiplexer determines the third position mask signal as the mask signal based on the third mask select signal.

In some embodiments, determining the transient signal of the asynchronous FIFO based on the first output signal and a generation mechanism of the asynchronous FIFO output signal comprises:

determining a transient signal of the asynchronous FIFO based on the first output signal and a comparison result of the asynchronous FIFO read pointer and the write pointer;

Wherein the read pointer and the write pointer are pointers after a read-write clock domain crossing has been performed.

In some embodiments, the method further comprises:

the cycle select signal and the manner in which the first and logic operations are performed on the second output signal and/or the asynchronous FIFO reset signal are configured before the asynchronous FIFO reset signal is issued.

The embodiment of the application also provides a FIFO circuit, comprising:

The register is used for receiving the asynchronous FIFO reset signal and the clock signal and respectively outputting delay FIFO reset signals subjected to delay processing;

a first multiplexer connected to each of the registers, respectively, for receiving a period selection signal, a mask selection signal, and an asynchronous FIFO reset signal or a delay FIFO reset signal subjected to delay processing, and outputting a first output signal and a second output signal;

A first AND logic operation unit connected to the first multiplexer for receiving the second output signal and the asynchronous FIFO reset signal and outputting a first AND logic output signal;

An asynchronous FIFO connected to the first multiplexer for receiving the first output signal and outputting a transient signal;

a second multiplexer connected to the first and logic operation part for receiving the first and logic output signal and the mask selection signal and outputting a mask signal;

and the second AND logic gate is respectively connected with the asynchronous FIFO and the second multiplexer, and performs AND logic operation on the transient signal and the shielding signal to obtain a burr-free output signal of the asynchronous FIFO.

The embodiment of the application also provides a chip, and the method of any one of the embodiments is adopted to eliminate the reset burr of the asynchronous reset signal.

The embodiment of the application also provides electronic equipment comprising the chip described in the embodiment.

The embodiment of the application has the beneficial effects that:

And delaying the asynchronous FIFO reset signal through a register to obtain a delay FIFO reset signal with stable state. The first multiplexer selects and outputs the first output signal and the second output signal based on the shielding selection signal, the asynchronous FIFO outputs the transient signal of the asynchronous FIFO based on the first output signal and the generation mechanism of the output signal, the second output signal and/or the asynchronous FIFO reset signal are subjected to the first and logic operation mode to obtain the first and logic output signal, the second multiplexer selects and outputs the first and logic output signal based on the shielding selection signal to obtain the shielding signal, and then performs the AND logic operation on the shielding signal and the transient signal to obtain the burr-free output signal, and the stability and accuracy of the output signal of the asynchronous FIFO circuit are ensured.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a schematic diagram of asynchronous reset FIFO glitch causing;

FIG. 2 is a schematic diagram of an asynchronous FIFO circuit according to the present application;

FIG. 3 is a flow chart of a method of eliminating glitches generated by an asynchronous reset of the present application;

FIG. 4 is a flow chart illustrating one embodiment of the step S20 of FIG. 3 according to the present application;

FIG. 5 is a flow chart illustrating one embodiment of the step S30 of FIG. 3 according to the present application;

FIG. 6 is a schematic diagram of the application for eliminating glitches caused by the reset rising edge of an asynchronous FIFO;

FIG. 7 is a schematic diagram of the application for eliminating glitches caused by asynchronous FIFO reset falling edges;

Fig. 8 is a flowchart of one embodiment of step S50 in fig. 3.

Detailed Description

Various aspects and features of the present application are described herein with reference to the accompanying drawings.

It should be understood that various modifications may be made to the embodiments of the application herein. Therefore, the above description should not be taken as limiting, but merely as exemplification of the embodiments. Other modifications within the scope and spirit of the application will occur to persons of ordinary skill in the art.

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the application and, together with a general description of the application given above, and the detailed description of the embodiments given below, serve to explain the principles of the application.

These and other characteristics of the application will become apparent from the following description of a preferred form of embodiment, given as a non-limiting example, with reference to the accompanying drawings.

It is also to be understood that, although the application has been described with reference to some specific examples, those skilled in the art can certainly realize many other equivalent forms of the application.

The above and other aspects, features and advantages of the present application will become more apparent in light of the following detailed description when taken in conjunction with the accompanying drawings.

Specific embodiments of the application will be described hereinafter with reference to the accompanying drawings, in which, however, it is to be understood that the embodiments so applied are merely examples of the application, which may be practiced in various ways. Well-known and/or repeated functions and constructions are not described in detail to avoid obscuring the application in unnecessary or unnecessary detail. Therefore, specific structural and functional details disclosed herein are not intended to be limiting, but merely as a basis for the claims and as a representative basis for teaching one skilled in the art to variously employ the present application in virtually any appropriately detailed structure.

The specification may use the word "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," which may each refer to one or more of the same or different embodiments in accordance with the application.

The embodiment of the application provides a method for eliminating burrs generated by asynchronous reset, which is applied to circuit design of burrs caused by asynchronous reset, such as an asynchronous FIFO reset circuit. Asynchronous FIFO design refers to implementing a FIFO buffer with two independent clock domains in a digital IC (INTEGRATED CIRCUIT: integrated circuit) design. The FIFO is characterized in that the read-write operation is controlled by two different clock signals (clk_a and clk_b in fig. 2) which are independent of each other, and clk_a and clk_b represent one clock signal respectively. I.e. the write operation is controlled by one clock signal (write clock) and the read operation is controlled by another clock signal (read clock). The write pointer points to the next data unit to be written and the read pointer points to the current data unit to be read. At reset, the read-write-pointer usually points to the first data unit (numbered 0). A full signal is issued by the status circuit of the FIFO when the FIFO is full to prevent further write operations and prevent data overflow. And a null signal is sent out by a state circuit of the FIFO when the FIFO is null so as to prevent further reading operation and prevent invalid data from being read. The empty-full signal is generated by comparing the read-write pointers. Vld_in in fig. 2 is a data valid input indication signal of the asynchronous FIFO circuit for indicating the data validity of the input FIFO. Due to the asynchronous reset, the output signal vld_pre may generate a glitch, which would affect the next stage circuit design if not processed. Asynchronous FIFOs may be used in scenarios where data is to be transferred across clock domains, for example, multiple clock domains may be included in a system where data is to be exchanged between the clock domains.

In connection with FIG. 1, the principle of asynchronous resetting of FIFOs to cause glitches is generally described as follows, in which the valid signal output is determined by the FIFO empty and full signals in order to maximize the FIFO performance. Typically, the depth of the FIFO is not 1 in order to buffer the data, so the read-write pointer is a multi-bit signal. In an ideal case, when the reset signal is asserted, the read-write pointers jump at the same instant, i.e. the delay times in the figure are the same. In actual situations, the fan-out of each register of the chip is different under the influence of various factors such as temperature, layout wiring, gray code decoding and the like, time delay (delay) in the diagram is respectively of a size, and the time from the comparison of the combination logic is sequential, so that the read-write pointer has a transient state when a reset signal comes. In the asynchronous reset FIFO design, the Valid indication signal (Valid) outputted to the next circuit design is generated by the combination logic comparison of the read pointer and the write pointer, and the competition and hazard phenomenon exists in the combination logic circuit design, thereby causing the Valid signal to generate burrs.

To solve the above problems, referring to fig. 2 and 3, a method for eliminating burrs generated by asynchronous reset according to an embodiment of the present application includes:

s10, determining a period selection signal based on the burr time length required to be shielded.

Illustratively, the period select signal is determined based on the glitch duration for which the reset glitch of the asynchronous FIFO reset signal (async_rst signal) needs to be masked. For example, if the glitch is within one clock cycle, the period select signal is 0, and if the glitch is likely to occur in multiple clock cycles, for example, there is a glitch in both clock cycles, the period select signal may be set to 1. Of course, it is understood that the period selection signal may be other values, depending on the duration of the glitch. The burr time length can be estimated through gate level simulation and cross-clock domain analysis.

And S20, carrying out delay processing on the asynchronous FIFO reset signal through a register based on the period selection signal to obtain a delay FIFO reset signal corresponding to the current period selection signal.

Illustratively, with continued reference to the above embodiment, in the case where the period selection signal is 1, the asynchronous FIFO reset signal may be delayed by a register (DFF) to obtain a delayed FIFO reset signal corresponding to the period selection signal being 1. In the case where the period selection signal is 0, the asynchronous FIFO reset signal may be determined to be a delayed FIFO reset signal corresponding to the period selection signal being 0 without performing delay processing on the asynchronous FIFO reset signal through the register. I.e. the delay FIFO reset signal does not have to be register delay processed.

The number of the registers can be reasonably set according to the period selection signals, and the asynchronous FIFO reset signals can be delayed through a plurality of registers according to the needs.

S30, the first multiplexer selects and outputs the delay FIFO reset signal based on the shielding selection signal to obtain a first output signal and a second output signal.

Illustratively, the first multiplexer (MUX 1) selectively outputs the delayed FIFO reset signal based on the mask select signal (mask_select) to obtain a first output signal (rst_vld) and a second output signal (mask_nxt) corresponding to the current delayed FIFO reset signal, the second output signal being the output signal delayed by the register.

Inevitably, due to the existence of the register, the asynchronous reset signal is delayed by a few clock cycles compared with the previous one, and in order to improve the reset response speed and increase the reset efficiency, a shielding selection signal is designed. The mask select signal is used to select a glitch caused by a rising edge, a falling edge, or a double edge of the mask asynchronous reset signal. Therefore, if it is determined that a certain asynchronous reset edge does not cause burrs, the device can be set to be unshielded, the delayed reset effect is consistent with an initially input asynchronous reset signal, the influence of the device on reset is reduced, and the reset efficiency is improved.

The first output signal is used as one of the input signals of the asynchronous FIFO, and the second output signal is used for subsequent operation according to the mask selection signal.

S40, determining a transient signal of the asynchronous FIFO based on the first output signal and a generation mechanism of the asynchronous FIFO output signal.

Illustratively, the asynchronous FIFO outputs a transient signal (vld_pre) of the asynchronous FIFO according to a generation mechanism of the asynchronous FIFO output signal after receiving the first output signal. Here, the generation mechanism of the asynchronous FIFO output signal includes that the asynchronous FIFO generates the output signal based on the comparison result of the read pointer and the write pointer. Here, the generation of the transient signal of the asynchronous FIFO also takes into account the first output signal. The transient signal of the asynchronous FIFO is output as a transient output signal, and is not output as a valid signal of the asynchronous FIFO circuit.

S50, determining a mode of performing first AND logic operation on the second output signal and/or the asynchronous FIFO reset signal based on the shielding selection signal to obtain a first AND logic output signal.

Illustratively, the second output signal and/or the asynchronous FIFO reset signal is processed differently when the mask select signal is used to mask edge glitches of different asynchronous reset signals. Therefore, it is necessary to determine the manner of performing the first and logic operation on the second output signal and/or the asynchronous FIFO reset signal based on the mask select signal, thereby obtaining the first and logic output signal. The resulting first and logic output signals are also different for different mask select signals.

S60, the second multiplexer selects and outputs the first and logic output signals based on the shielding selection signal to obtain a shielding signal.

Illustratively, the first and logic output signals are used as one input signal of a second multiplexer (MUX 2), which can selectively output the first and logic output signals based on a mask select signal, resulting in a mask signal (mask signal) that serves as a glitch mask signal for the vld_pre signal.

And S70, performing a second AND logic operation on the shielding signal and the transient signal to obtain a burr-free output signal of the asynchronous FIFO.

Illustratively, the mask signal and the vld_pre signal are further output through a second and logic to mask the glitches of the vld_pre signal through the mask signal, ultimately generating a clean, glitch-free output signal (vld_out signal) of the asynchronous FIFO.

According to the embodiment of the application, the asynchronous FIFO reset signal is delayed through the register, so that the delayed FIFO reset signal with stable state is obtained. The first multiplexer selects and outputs the first output signal and the second output signal based on the shielding selection signal, the asynchronous FIFO outputs the transient signal of the asynchronous FIFO based on the first output signal and the generation mechanism of the output signal, the second output signal and/or the asynchronous FIFO reset signal are subjected to the first and logic operation mode to obtain the first and logic output signal, the second multiplexer selects and outputs the first and logic output signal based on the shielding selection signal to obtain the shielding signal, and then performs the AND logic operation on the shielding signal and the transient signal to obtain the burr-free output signal, and the stability and accuracy of the output signal of the asynchronous FIFO circuit are ensured.

In some embodiments, in conjunction with fig. 4, delaying the asynchronous FIFO reset signal by a register based on the period select signal includes:

S21, determining the number of required registers based on the period selection signal, wherein the number of registers is the same as the value of the period selection signal.

For example, in the case where the period selection signal is 0, the asynchronous FIFO reset signal may not be delayed by the register, and the number of registers may be 0. In the case where the period selection signal is 1, the number of registers may be 1, and the asynchronous FIFO reset signal may be delayed by one register. The registers are used for delaying the asynchronous FIFO reset signal by a certain clock period, and then transmitting the first output signal through the first multiplexer, wherein a plurality of registers select a plurality of clock shielding valid signal time lengths. The valid burr generation time length can also be estimated through gate level simulation and cross-clock domain analysis according to the needs, and the number of registers is further added to increase the valid shielding time length.

The present application is exemplified using a typical asynchronous FIFO (Async FIFO) design to generate glitches, and designs suitable for use with the present application include, but are not limited to, asynchronous FIFO circuit designs.

S22, carrying out delay processing on the asynchronous FIFO reset signal through the determined number of the registers.

For example, in the case where the required registers are one, the asynchronous FIFO reset signal may be delayed by one clock cycle by one register, and in the case where the required registers are plural, the asynchronous FIFO reset signal may be delayed by plural clock cycles by plural registers.

In some embodiments, in conjunction with fig. 5, the first multiplexer selectively outputs the delayed FIFO reset signal based on the mask select signal to obtain a first output signal and a second output signal, comprising:

S31, when the reset burr of the asynchronous FIFO reset signal is the rising edge reset burr, the mask selection signal is determined to be the first mask selection signal.

S32, selectively outputting a delay FIFO reset signal based on the first shielding selection signal to obtain a third output signal and a fourth output signal, wherein the third output signal is one of the first output signals, and the fourth output signal is one of the second output signals.

For example, in conjunction with fig. 2 and 6, in an actual chip, there may be a case where a register value changes at the time of reset release, and if the register is also used as a combinational logic fan-out or other case, there may be an asynchronous reset release generation glitch problem as well, that is, an asynchronous reset rising edge causes a glitch, and the glitch is eliminated timing chart is shown in fig. 6. In order to improve the reset efficiency, when mask_select is the mask rising edge reset burr, the async_rst signal is input into the first multiplexer through the path 1 connected with the first multiplexer and is output as the third output signal of the first multiplexer, namely, the third output signal (i.e. the rst_vld signal in fig. 2 and 6) which is output after being selected by the first multiplexer is the async_rst signal which does not pass through register delay, so as to not influence the reset falling edge and reduce the influence of the application on the reset action time. The mask_nxt signal is a fourth output signal delayed by a register, and in the timing diagram shown in fig. 6, cycle_select is set to 1, that is, the valid mask period is 1 clock edge, so the mask_nxt signal is a signal output from the async_rst signal after passing through a first stage register and then the first multiplexer (MUX 1). The async_rst signal and the mask_nxt are output as a mask_pos signal after AND logic operation through a first AND gate (& 1), and are selected as a mask signal through MUX 2 to be used as a burr shielding signal of the vld_pre signal. The mask signal and the vld_pre signal are further output after the second AND logic operation, and finally a clean and burr-free vld_out signal is generated.

S33, when the reset burr of the asynchronous FIFO reset signal is the falling edge reset burr, the mask selection signal is determined to be a second mask selection signal.

And S34, selectively outputting a delay FIFO reset signal based on the second shielding selection signal to obtain a fifth output signal and a sixth output signal, wherein the fifth output signal is one of the first output signals, and the sixth output signal is one of the second output signals.

For example, in conjunction with fig. 2 and fig. 7, when the mask_select is to mask the falling edge reset burr, the cycle_select signal is configured to be 2, and the cycle_select signal is used to select the 2-stage register to delay the async_rst signal by two clock cycle edges, so as to obtain the reset signal rst_vld actually used for reset, and simultaneously, the asynchronous FIFO reset signals can be synchronized in two stages, so that the unexpected problem of crossing clock domains is avoided, and the reset stability is increased. The delayed signal is input to the first multiplexer via path 3 between the register and the first multiplexer in fig. 2 and output as the fifth output signal of the first multiplexer, i.e. the rst_vld signal in fig. 2 and 7, which is used as a signal for an actual asynchronous reset.

In some embodiments, in combination with fig. 8, determining a manner of performing a first and logic operation on the second output signal and/or the asynchronous FIFO reset signal based on the mask select signal, resulting in a first and logic output signal, comprises:

s51, performing a first operation based on the first mask selection signal, where the first operation includes:

And performing AND logic operation on the fourth output signal and the asynchronous FIFO reset signal to obtain a first position shielding signal.

For example, when mask_select is a mask rising edge reset burr, as shown in fig. 2 and 6, a mask period is selected by the cycle_select signal as needed, the async_rst signal delayed by the register is output as a fourth output signal (mask_nxt signal in fig. 2), and the mask_nxt signal and the original async_rst signal are output as a first position mask signal (mask_pos signal) by the first and gate.

S52, performing a second operation based on the second mask selection signal, where the second operation includes:

the asynchronous FIFO reset signal is determined to be the second position mask signal.

Illustratively, in conjunction with fig. 2 and 7, when mask_select is a mask falling edge reset glitch, the async_rst signal is used as the mask_pre signal, and the mask_pre signal is used as a second position mask signal (mask_ nge signal in fig. 2) to be selected by the second multiplexer and then used as a mask signal (mask signal in fig. 2) for masking the glitch generated by the reset falling edge resulting in vld_pre.

And S53, performing a third operation when the shielding selection signal is a third shielding selection signal, wherein the third shielding selection signal comprises the first shielding selection signal and the second shielding selection signal.

The third operation includes performing an AND logic operation on the first location mask signal and the asynchronous FIFO reset signal to obtain a third location mask signal.

For example, when the dual-edge reset glitch (rising edge reset glitch and falling edge reset glitch) needs to be masked, the signal of the original async_rst signal after the delay of the register is taken as the rst_vld signal, and the mask_pre and the mask_pos signals need to be taken as mask signals by performing AND logic operation through a second AND gate (& 2), so that the glitch possibly caused by the dual edges of the asynchronous FIFO reset signal can be more stably masked.

In some embodiments, the second multiplexer selectively outputs the first and logic output signals based on the mask select signal to obtain a mask signal, including:

The second multiplexer determines the first position mask signal as the mask signal based on the first mask select signal.

A second multiplexer determines the second position mask signal as the mask signal based on the second mask select signal.

The second multiplexer determines the third position mask signal as the mask signal based on the third mask select signal.

That is, the second multiplexer (MUX 2) is configured to use, as a mask signal, different position mask signal outputs in the case of different mask selection signals, for masking the glitch generated by vld_pre.

In some embodiments, determining the transient signal of the asynchronous FIFO based on the first output signal and a generation mechanism of the asynchronous FIFO output signal comprises:

The transient signal of the asynchronous FIFO is determined based on the first output signal and the result of the comparison of the asynchronous FIFO read pointer (rd_ptr) and the write pointer (wr_ptr). Wherein the read pointer and the write pointer are pointers after a read-write clock domain crossing has been performed.

For example, in the asynchronous FIFO, in conjunction with fig. 2, 6 and 7, the value of the temporary read-write pointer cannot be determined when reset, there is a high probability that a non-0 value exists, and in general, the reset value of the write pointer (wr_ptr) and the read pointer (rd_ptr) is 0, and due to the influence of various factors such as temperature, layout routing, gray code decoding, etc., a transient will be generated, and when the read pointer and the write pointer are inconsistent, a transient vld_pre signal, i.e., a glitch, will be generated. When the mask_select is used for shielding the falling edge reset burr, the async_rst signal is used as a mask_ nge signal, the mask signal is selected as a mask signal through the MUX 2, the mask signal and the vld_pre signal are further output through a second AND logic (third AND gate & 3), and finally, the burr generated by the vld_pre signal is shielded, and a burr-free vld_out signal is generated.

The application only aims at the problem of the output burr of the combinational logic caused by asynchronous reset, and the problem of asynchronous reset and synchronous release of the register of the sequential logic is not considered.

In some embodiments, the method further comprises:

The cycle select signal and the manner in which the first and logic operations are performed on the second output signal and/or the asynchronous FIFO reset signal are configured before the asynchronous FIFO reset signal is issued. The present application provides various ways and time intervals for removing the glitches, and the configuration of the glitch removal method and the corresponding circuit structure needs to be completed before the asynchronous reset is initiated.

The embodiment of the application also provides a FIFO circuit, comprising:

and the register is used for receiving the asynchronous FIFO reset signal and the clock signal and respectively outputting delay FIFO reset signals subjected to delay processing.

And the first multiplexer is respectively connected with each register and is used for receiving a period selection signal, a shielding selection signal and an asynchronous FIFO reset signal or a delay FIFO reset signal subjected to delay processing and outputting a first output signal and a second output signal.

And the first AND logic operation part is connected with the first multiplexer and is used for receiving the second output signal and the asynchronous FIFO reset signal and outputting a first AND logic output signal.

In connection with fig. 2, the first and logic operation means comprises a first and logic gate &1 and a second and logic gate &2.

An asynchronous FIFO coupled to the first multiplexer for receiving the first output signal and outputting a transient signal.

And a second multiplexer connected to the first AND logic operation part for receiving the first AND logic output signal and the mask selection signal and outputting a mask signal.

And the second AND logic gate is respectively connected with the asynchronous FIFO and the second multiplexer, and performs AND logic operation on the transient signal and the shielding signal to obtain a burr-free output signal of the asynchronous FIFO. In connection with fig. 2, the second and logic gate is the and logic gate &3 in the figure.

The embodiment of the application also provides a chip, and the method of any one of the embodiments is adopted to eliminate the reset burr of the asynchronous reset signal.

The embodiment of the application also provides electronic equipment comprising the chip described in the embodiment.

The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the disclosure referred to in the present application is not limited to the specific combinations of technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the spirit of the disclosure. Such as the above-mentioned features and the technical features disclosed in the present application (but not limited to) having similar functions are replaced with each other.

Moreover, although operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order. In certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the application. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are example forms of implementing the claims.

While various embodiments of the present application have been described in detail, the present application is not limited to these specific embodiments, and various modifications and embodiments can be made by those skilled in the art on the basis of the inventive concept, and these modifications and modifications should be included in the scope of the claimed application.

Claims (10)

1. A method for eliminating glitches generated by an asynchronous reset, applied to an asynchronous FIFO circuit, said method comprising:

determining a period selection signal based on a glitch duration for which a reset glitch of the asynchronous FIFO reset signal is to be masked;

Based on the period selection signal, carrying out delay processing on the asynchronous FIFO reset signal through a register to obtain a delay FIFO reset signal corresponding to the current period selection signal;

The first multiplexer selects and outputs the delay FIFO reset signal based on the shielding selection signal to obtain a first output signal and a second output signal;

Determining a transient signal of the asynchronous FIFO based on the first output signal and a generation mechanism of the asynchronous FIFO output signal;

Determining a mode of performing a first AND logic operation on the second output signal and/or the asynchronous FIFO reset signal based on the mask selection signal to obtain a first AND logic output signal;

The second multiplexer selects and outputs the first and logic output signals based on the shielding selection signal to obtain a shielding signal;

And performing a second AND logic operation on the shielding signal and the transient signal to obtain a burr-free output signal of the asynchronous FIFO.

2. The method of claim 1, wherein delaying the asynchronous FIFO reset signal by a register based on the period select signal comprises:

determining a number of required registers based on the period selection signal, wherein the number of registers is the same as the value of the period selection signal;

And carrying out delay processing on the asynchronous FIFO reset signal through the determined number of the registers.

3. The method of claim 2, wherein the first multiplexer selectively outputting the delayed FIFO reset signal based on the mask select signal to obtain the first output signal and the second output signal, comprising:

When the reset burr of the asynchronous FIFO reset signal is a rising edge reset burr, determining the shielding selection signal as a first shielding selection signal;

Selecting and outputting a delay FIFO reset signal based on the first shielding selection signal to obtain a third output signal and a fourth output signal, wherein the third output signal is one of the first output signals, and the fourth output signal is one of the second output signals;

When the reset burr of the asynchronous FIFO reset signal is a falling edge reset burr, determining the shielding selection signal as a second shielding selection signal;

And selectively outputting a delay FIFO reset signal based on the second shielding selection signal to obtain a fifth output signal and a sixth output signal, wherein the fifth output signal is one of the first output signals, and the sixth output signal is one of the second output signals.

4. A method according to claim 3, wherein determining the manner in which the first and logic operations are performed on the second output signal and/or the asynchronous FIFO reset signal based on the mask select signal results in a first and logic output signal, comprising:

performing a first operation based on the first mask select signal, the first operation comprising:

performing AND logic operation on the fourth output signal and the asynchronous FIFO reset signal to obtain a first position shielding signal;

performing a second operation based on the second mask select signal, the second operation comprising:

Determining the asynchronous FIFO reset signal as a second position mask signal;

Performing a third operation if the mask select signal is a third mask select signal, wherein the third mask select signal includes the first mask select signal and the second mask select signal;

The third operation includes performing an AND logic operation on the first location mask signal and the asynchronous FIFO reset signal to obtain a third location mask signal.

5. The method of claim 4, wherein the second multiplexer selectively outputting the first and logic output signals based on the mask select signal to obtain a mask signal, comprising:

a second multiplexer determining the first position mask signal as the mask signal based on the first mask select signal;

A second multiplexer determining the second position mask signal as the mask signal based on the second mask select signal;

the second multiplexer determines the third position mask signal as the mask signal based on the third mask select signal.

6. The method of claim 1, wherein determining the transient signal of the asynchronous FIFO based on the first output signal and a generation mechanism of the asynchronous FIFO output signal comprises:

determining a transient signal of the asynchronous FIFO based on the first output signal and a comparison result of the asynchronous FIFO read pointer and the write pointer;

Wherein the read pointer and the write pointer are pointers after a read-write clock domain crossing has been performed.

7. The method according to claim 1, wherein the method further comprises:

the cycle select signal and the manner in which the first and logic operations are performed on the second output signal and/or the asynchronous FIFO reset signal are configured before the asynchronous FIFO reset signal is issued.

8. A FIFO circuit, comprising:

The register is used for receiving the asynchronous FIFO reset signal and the clock signal and respectively outputting delay FIFO reset signals subjected to delay processing;

a first multiplexer connected to each of the registers, respectively, for receiving a period selection signal, a mask selection signal, and an asynchronous FIFO reset signal or a delay FIFO reset signal subjected to delay processing, and outputting a first output signal and a second output signal;

A first AND logic operation unit connected to the first multiplexer for receiving the second output signal and the asynchronous FIFO reset signal and outputting a first AND logic output signal;

An asynchronous FIFO connected to the first multiplexer for receiving the first output signal and outputting a transient signal;

a second multiplexer connected to the first and logic operation part for receiving the first and logic output signal and the mask selection signal and outputting a mask signal;

and the second AND logic gate is respectively connected with the asynchronous FIFO and the second multiplexer, and performs AND logic operation on the transient signal and the shielding signal to obtain a burr-free output signal of the asynchronous FIFO.

9. A chip, characterized in that the elimination of the reset glitch of the asynchronous reset signal is performed by the method according to any one of claims 1 to 7.

10. An electronic device comprising the chip of claim 9.