CN119652420B

CN119652420B - Low-complexity real-time nonlinear compensation method for short-distance optical fiber link system

Info

Publication number: CN119652420B
Application number: CN202411668952.0A
Authority: CN
Inventors: 余建军; 孙新达; 王凯辉
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2024-11-21
Filing date: 2024-11-21
Publication date: 2025-10-17
Anticipated expiration: 2044-11-21
Also published as: CN119652420A

Abstract

The present invention belongs to the field of optical fiber communication technology, and specifically relates to a low-complexity, real-time nonlinear compensation method for short-distance optical fiber link systems. The present invention uses the Volterra algorithm to implement nonlinear damage compensation. The algorithm is considered as a filter that adaptively updates taps and is divided into a linear term finite impulse response filter calculation module, a nonlinear term finite impulse response filter calculation module, an error calculation module, and a tap coefficient update module. Low-complexity processing of nonlinear compensation is further achieved through pruning and non-uniform quantization. The present invention solves the problem of nonlinear distortion caused by devices and transmission in intensity modulation direct detection systems, and is simpler to implement, with greatly reduced complexity, thereby saving more power consumption. The method has been verified on an FPGA development board, providing a basis for the hardware implementation of nonlinear compensation and laying a foundation for the further development of future optical fiber communication systems.

Description

Low-complexity real-time nonlinear compensation method for short-distance optical fiber link system

Technical Field

The invention belongs to the technical field of optical fiber communication, and particularly relates to a low-complexity real-time nonlinear compensation method.

Background

As society moves into new information age, global network traffic explodes, which presents a significant challenge to existing communication networks. Therefore, achieving large-capacity data transmission under limited bandwidth has become an important task for the communication industry. In recent studies, it has been shown that an intensity modulated direct detection (IM/DD) system plays an important role in supporting high-speed signaling.

In general, the optical link has serious influence on high-rate signal transmission due to bandwidth limitation, nonlinearity and the like, and nonlinear distortion caused by devices and transmission exists in an IM/DD system. However, the compensation for nonlinear loss is usually quite complex in calculation, and the problem of excessive calculation is needed to be solved in order to realize the deployment of real-time nonlinear compensation due to limited hardware resources. The low complexity nonlinear real-time compensation technique, if implemented successfully, can play a key role in future communications.

Disclosure of Invention

The invention aims to provide a low-complexity real-time nonlinear compensation method which can be realized on a hardware platform and is used for directly detecting a single-carrier pulse amplitude modulation signal in a short-distance optical fiber link system by intensity modulation so as to solve the nonlinear distortion problem caused by devices and transmission.

The invention provides a real-time nonlinear compensation method for a short-distance optical fiber link system, which specifically comprises two parts of nonlinear damage compensation and complexity reduction processing, and is described as follows:

and (1) nonlinear damage compensation:

The invention adopts a nonlinear compensation algorithm to realize nonlinear damage compensation, the nonlinear compensation algorithm is specifically a Woltay algorithm (Gu Kejun, lei Lei, iris, etc. the Volterra hybrid equalizer design and research [ J ] optical communication research, 2024, (03) 40-48.DOI: 10.13756/j.gtxyj.2024.230077) based on a memory polynomial, and the algorithm can be regarded as a filter for adaptively updating taps. The algorithm is divided into a linear term finite impulse response filter calculation module, a nonlinear term finite impulse response filter calculation module, an error calculation module and a tap coefficient updating module. Wherein:

The sum of the outputs of the linear term finite impulse response filter and the nonlinear term finite impulse response filter is a complete output linear part and nonlinear part, and the two calculation expressions are as follows:

Wherein w _l1 (k) and w _l1,l2 (k) represent tap coefficients corresponding to the linear portion and the nonlinear portion, respectively, and N ₁ and N ₂ represent memory lengths of the linear portion and the nonlinear portion. The parameter k represents the current point in time, and in discrete signal processing k is a discrete time index representing the current sampling instant. The left side y (k) of the formula is the output signal at the current time. x (k) represents the input signal, and l ₁,l₂ represents the time delay index of the input signal x (k). x (k-l ₁) represents the value of the forward delay l ₁ of the input signal at the current instant k. Similarly, x (k-l ₂) represents the value of the forward delay l ₂.

The error calculation module is provided with a decision device which is realized through a conditional decision statement, specifically sets three threshold values of 0.5,0 and 0.5, makes a decision, and decides an output signal to-0.75 and 0.25,0.25,0.75 levels. And (3) performing difference between the sum of the outputs of the two filters and a standard constellation point output by a decision device to obtain an error, wherein the calculation expression is as follows:

e(k)=d(k)-y(k) , (2)

d (k) is a standard constellation point output by the decision device, y (k) is output signals of the two filters, and e (k) is an error.

The tap coefficient updating module is used for updating the tap value required by the finite impulse response filter calculating module, the required input is provided with the output of the filter and the error calculated by the error calculating module, and the calculating expression is as follows:

w(k+1)=w(k)+μe(k)x^*(k) , (3)

w (k) refers to the coefficient before update, w (k+1) refers to the coefficient after update, μ is the iteration step, e (k) is the error calculated by the error module, and x (k) is the input signal.

The volterra algorithm is implemented by a hardware description language and deployed in a field programmable gate array development board, and the hardware platform is arranged in an intensity modulation direct detection communication system and is used for processing signals received by a receiving end in real time. The receiving end converts the received pulse amplitude modulation signal into a digital sequence through an analog-to-digital converter (ADC), then the digital sequence is sent into a field programmable gate array development board, the digital sequence is distributed into a digital signal processing module arranged in the field programmable gate array development board, the linear term finite impulse response filter calculation module and the nonlinear term finite impulse response filter calculation module are used for calculating the linear term and the corresponding tap coefficient of an input signal, generating the nonlinear term of the input signal and calculating the nonlinear term and the corresponding tap coefficient, and calculating errors and updating the corresponding tap coefficients of the linear term and the nonlinear term in an error calculation module and a tap coefficient updating module. The specific calculation and update processes are implemented by referring to the above formulas (1), (2) and (3).

After the Walter algorithm adopted in the invention is realized on the field programmable gate array platform, the Walter algorithm can be equivalent to an equalizer with self-adaptive updating tap and nonlinear compensation capability, the first operation after the equalizer starts working adopts an initially set tap value, and the tap coefficient is updated based on the minimum mean square error along with the progress of calculation until the tap coefficient converges, so that an ideal nonlinear compensation effect is achieved;

and (II) complexity reduction processing:

The difficulty in realizing real-time nonlinear compensation on a hardware platform mainly comes from the fact that excessive multiplication calculation brings great computational complexity, and aiming at the problem, the complexity is reduced by adopting pruning and nonuniform quantization methods.

In a short-distance optical link system, by sorting the converged tap coefficients, we find that the tap coefficient portions corresponding to the linear terms are exponentially distributed, and the tap weights at the same positions of different power points are relatively stable, so that the tap at part of positions is quantized in a non-uniform quantization manner, and the multiplier consumed by updating the tap at the position can be saved. The scheme is well suited for deployment in the linear part of the algorithm. On a field programmable gate array development board, by taking a non-uniform quantization of the two-based exponent, the multiplier consumed by multiplying the input signal with the taps can also be saved, since in hardware description language (Verilog) the multiplication of the two exponents can be achieved by an arithmetic shift. The quantization formula is as follows:

b is the number of quantization bits, and the greater the number of quantization bits, the higher the accuracy. Q _u is the quantization level.

By observing the tap coefficient parts corresponding to the nonlinear parts in a sorting way, we find that the tap coefficient parts are sparsely distributed, the tap weights of most positions are very small, the influence on the final result is very small, and therefore a threshold value T can be found, and the value takes balance of performance and resources into consideration, and the multiplication consumed by tap updating and multiplying the nonlinear terms by the taps is saved by setting the weight less than the threshold value to zero. The scheme is very suitable for being deployed in a nonlinear part of the algorithm, and the pruning formula is as follows:

W_Nonlinear(k)＝0,if |W_Nonlinear(k)|<T , (5)

Wherein W _Nonlinear is the tap coefficient corresponding to the nonlinear part, and T is the pruning threshold value. The threshold value cannot be too large, otherwise excessive performance is lost, and if too small, the released resources are too small. By setting a smaller initial value for T, then simulating, judging the performance loss through the error rate, if the performance loss is acceptable, increasing the T value, and carrying out iterative updating until an acceptable balance point is found, namely the performance loss is not too much, and the released resources are objective.

The invention can greatly reduce complexity and save power consumption while providing nonlinear damage compensation capability, and provides basis for nonlinear compensation to be realized on hardware.

Drawings

Fig. 1 is a short-range optical link real-time communication system architecture utilizing the present invention.

Reference numeral 1 is a short-distance optical link communication system transmitting end, which comprises a DAC, 2 is a system optical fiber link, 3 is a system receiving end, which comprises an ADC, 4 is a hardware platform for deploying a real-time DSP algorithm, an FPGA development board can be adopted, 5 is a linear compensation algorithm, 6, 7 and 8 are processes of the invention, wherein 6 is a nonlinear compensation algorithm, 7 and 8 are complexity reduction schemes deployed in 6 respectively, 7 is a non-uniform quantization scheme, and 8 is a pruning scheme.

Detailed Description

The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings.

The low-complexity real-time nonlinear compensation method for the short-distance optical fiber link system provided by the invention has the advantage of experimental verification. Successful deployment on field programmable gate array development boards verifies the performance of the low complexity real-time nonlinear compensation algorithm. And successful transmission of the 25km single mode fiber of 29.4912Gbit/s PAM4 signal is completed. According to the illustration in fig. 1, three parts are specifically included, "nonlinear compensation", "nonuniform quantization", and "pruning:

(1) "nonlinear compensation" section:

When the pulse amplitude modulation signal is transmitted in the transmitting end 1, the pulse amplitude modulation signal reaches the receiving end 3 through the transmission of the optical fiber link 2, the received pulse amplitude modulation signal is converted into a digital sequence in the receiving end through an analog-to-digital converter (ADC), then the digital sequence is sent into a hardware platform, the digital sequence is distributed into a parallel digital signal processing module according to the length of a filter, and the calculation of the linear term and the corresponding tap coefficient of the input signal, the generation of the nonlinear term and the calculation of the nonlinear term and the corresponding tap coefficient of the input signal, the calculation of the output error and the update of the corresponding tap coefficients of the linear term and the nonlinear term are carried out in the digital signal processing module. The calculation process and the coefficient update process are as shown in the above formulas (1) (2) (3). N ₁ and N ₂ represent the memory lengths of the linear and nonlinear portions, and through simulation verification, N ₁ is selected to be 15 and N ₂ is selected to be 5. The coefficient updating of the linear part and the coefficient updating of the nonlinear part are separately carried out, namely two different iteration compensations are needed, through simulation verification, the iteration step value required by the corresponding tap updating of the linear part is selected to be 2 ^-7, the iteration step value required by the corresponding tap updating of the nonlinear part is selected to be 2 ^-11, the advantage of selection is that the use of multiplication can be saved, and in the hardware description language, the multiplication of the index of two can be realized through arithmetic shift, so that the use of the valuable resource of the multiplier is reduced.

(2) "Non-uniform quantization" section:

In a short-distance optical link system, by sorting the converged tap coefficients, we find that the tap coefficient portions corresponding to the linear terms are exponentially distributed, and the tap weights at the same positions of different power points are relatively stable, so that the tap at part of positions is quantized in a non-uniform quantization manner, and the multiplier consumed by updating the tap at the position can be saved. On FPGA platforms, by taking non-uniform quantization of the two-based exponents, the multiplier consumed by multiplying the input signal with the taps can also be saved, since in hardware description languages the multiplication of the two exponents can be achieved by an arithmetic shift. The quantization formula is shown as formula (4) above. Through simulation verification, the selected quantization bit number b is 4, namely Q _u has 16 quantization levels, and the precision is enough. By non-uniformly quantizing the taps of the partially linear portion, i.e., by setting the partial taps to a fixed value corresponding to the quantization interval, no further updating is performed. The performance degradation is acceptable while resources are released.

(3) The "pruning" section:

in a short-distance optical link system, by sorting the converged tap coefficients, we find that the tap coefficients corresponding to the nonlinear terms are sparsely distributed, and tap weights at most positions are very small, which has very little influence on the final result, so that a threshold value T can be found, which takes performance and resource balance into consideration, and by setting weights smaller than the threshold value to zero, tap updating and multiplication consumed by multiplying the nonlinear terms by taps are saved. The pruning formula is shown in formula (5) above. The pruning threshold value T is selected through simulation, a small initial value of 0.0001 is set for the T value, a tap smaller than the value after convergence is set to be 0, and the tap is not updated and participates in calculation. And judging the loss condition of the performance through the error rate of the output signal, and then continuously increasing the T value until an equilibrium threshold value is found. The final threshold is set to 0.002.

In the experiment, the low-complexity nonlinear compensation algorithm is successfully deployed on a programmable gate array platform, and successful transmission of a 25km single-mode fiber of 29.4912Gbit/s PAM4 signals is completed. And comparing and verifying with an algorithm without the low-complexity scheme. Experimental results show that the power consumption of the low-complexity nonlinear compensation algorithm is reduced by 26.2%, the use of a multiplier is reduced by 75.3%, the performance is reduced acceptably, and the nonlinear compensation capability is still reserved.

The invention realizes a low-complexity nonlinear compensation technology suitable for hardware platform deployment by utilizing a non-uniform quantization and pruning scheme, and effectively solves the problem of difficult realization caused by overhigh nonlinear compensation calculation complexity. The nonlinear compensation technology reduces redundant calculation and replaces multiplication by arithmetic shift, so that hardware is very friendly to realize, complexity is greatly reduced, and power consumption is reduced. The technology is successfully verified in a transmission experiment of a 25km single mode fiber of 29.4912Gbit/s PAM4 signal, and can be applied to a receiver module in the future, thereby bringing better receiving capacity and performance.

Claims

1. A real-time nonlinear compensation method for a short-distance optical fiber link system, characterized in that a nonlinear compensation algorithm is used to achieve nonlinear damage compensation, wherein the nonlinear compensation algorithm is specifically the Volterra algorithm. The algorithm is regarded as a filter that adaptively updates taps and is divided into a linear term finite impulse response filter calculation module, a nonlinear term finite impulse response filter calculation module, an error calculation module, and a tap coefficient update module.

The sum of the outputs of the linear finite impulse response filter and the nonlinear finite impulse response filter is a complete output linear part and nonlinear part. The calculation expressions of the two calculation modules are as follows:

Where w _l1 (k) and w _l1,l2 (k) represent the tap coefficients corresponding to the linear part and the nonlinear part respectively, N ₁ and N ₂ represent the memory lengths of the linear part and the nonlinear part respectively, the parameter k represents the current time point, y(k) is the output signal at the current moment, x(k) represents the input signal, l ₁ ,l ₂ represent the time delay index of the input signal x(k); x(kl ₁ ) represents the value of the input signal at the current moment k delayed by l ₁ ; similarly, x(kl ₂ ) represents the value delayed by l ₂ ;

The error calculation module is equipped with a decision maker, and the specific decision is implemented by a conditional decision statement, wherein three threshold values of 0.5, 0, and -0.5 are set for decision making, and the output signal is decided to four levels of -0.75, -0.25, 0.25, and 0.75; the sum of the outputs of the above two filters is subtracted from the standard constellation point output by the decision maker to obtain the error, and the calculation formula is as follows:

e(k)＝d(k)-y(k) , (2)

d(k) is the standard constellation point output by the decision maker, y(k) is the output signal of the two filters mentioned above, and e(k) is the error;

The tap coefficient update module is used to update the tap values required in the finite impulse response filter calculation module. The required inputs are the filter output and the error calculated by the error calculation module. The calculation expression is as follows:

w(k+1)＝w(k)+μe(k)x ^* (k) , (3)

w(k) refers to the coefficient before update, w(k+1) refers to the coefficient after update, μ is the iteration step size, e(k) is the error calculated by the error module, and x(k) is the input signal;

The Volterra algorithm is implemented using a hardware description language and deployed in a field programmable gate array (FPGA) development board. The FPGA development board is arranged as a hardware platform in an intensity modulation direct detection communication system for real-time processing of signals received by a receiving end. The receiving end converts the received pulse amplitude modulation signal into a digital sequence through an analog-to-digital converter (ADC). The digital sequence is then sent to the FPGA development board. By allocating the digital sequence to the digital signal processing module deployed on the FPGA development board, the linear term of the input signal and the corresponding tap coefficient are calculated, the nonlinear term of the input signal is generated, and the nonlinear term and the corresponding tap coefficient are calculated in the linear term finite impulse response filter calculation module and the nonlinear term finite impulse response filter calculation module. The error is calculated in the error calculation module and the tap coefficient update module, and the tap coefficients corresponding to the linear term and the nonlinear term are updated. For the specific calculation and update process, please refer to the above formulas (1), (2), and (3).

When implemented on a field-programmable gate array (FPGA) platform, the Volterra algorithm can be equated to an equalizer with adaptive tap updates and nonlinear compensation capabilities. The equalizer's first operation uses the initially set tap values. As the calculation proceeds, the tap coefficients are updated based on the minimum mean square error (MMSE) until convergence is achieved, achieving ideal nonlinear compensation.

It also includes complexity reduction processing, as follows:

In short-distance optical link systems, the tap coefficients corresponding to the linear terms are exponentially distributed, and the tap weights at the same location at different power points are relatively stable. Therefore, non-uniform quantization is used to quantize the taps at some locations to save the multipliers consumed by updating the taps at these locations. Therefore, on the field programmable gate array development board, non-uniform quantization based on the exponential of two is adopted. In the hardware description language, arithmetic shifts can be used to implement the multiplication of the exponential of two. The quantization formula is as follows:

b is the number of quantization bits. The larger the number of quantization bits, the higher the accuracy. _Qu is the quantization level.

Since the tap coefficients corresponding to the nonlinear part are sparsely distributed, the tap weights at most positions are very small, which has a very small impact on the final result. Therefore, a threshold value T can be found. This value takes into account the balance between performance and resources. By setting the weights smaller than the threshold value to zero for pruning, the multiplication consumed by tap updates and multiplication of nonlinear terms with taps can be saved. The pruning formula is as follows:

W _Nonlinear (k)＝0,if |W _Nonlinear (k)|<T, (5)

W _Nonlinear is the tap coefficient corresponding to the nonlinear part, and T is the pruning threshold. The threshold cannot be too large, otherwise there will be excessive performance loss. If it is too small, too few resources will be released. By setting a small initial value for T and then performing simulation, the performance loss is judged by the bit error rate. If the performance loss is acceptable, the T value is increased and iterative updates are performed until an acceptable balance is found, that is, the performance loss is not too excessive and the resources released are reasonable.