CN119630006A - Trench p-type gallium oxide junction barrier Schottky diode and preparation method thereof - Google Patents
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Abstract
本发明公开了一种沟槽p型氧化镓结型势垒肖特基二极管及其制备方法，主要解决现有氧化镓肖特基二极管导通电阻和反向漏电流较高、耐压能力和抗浪涌能力较差的问题。其自下而上包括阴极欧姆金属层(1)、n型重掺杂氧化镓衬底(2)、n型轻掺杂氧化镓漂移层(3)和阳极肖特基金属层(4)，其中n型轻掺杂氧化镓漂移层上表面向下设有多个沟槽(5)，以改变器件表面电场；每个沟槽的下方注有p型氧化镓区域(6)，其与n型轻掺杂氧化镓漂移层形成氧化镓同质pn结；每个沟槽内沉积有高k介质层(7)。本发明降低了漏电流，提高了器件的反向击穿电压，减小了导通电阻，提升了抗浪涌能力，可用于功率电子设备。
The present invention discloses a trench p-type gallium oxide junction barrier Schottky diode and a preparation method thereof, which mainly solves the problems of high on-resistance and reverse leakage current, poor withstand voltage and surge resistance of existing gallium oxide Schottky diodes. From bottom to top, it includes a cathode ohmic metal layer (1), an n-type heavily doped gallium oxide substrate (2), an n-type lightly doped gallium oxide drift layer (3) and an anode Schottky metal layer (4), wherein the upper surface of the n-type lightly doped gallium oxide drift layer is provided with a plurality of trenches (5) downwardly to change the surface electric field of the device; a p-type gallium oxide region (6) is injected below each trench, which forms a gallium oxide homogeneous pn junction with the n-type lightly doped gallium oxide drift layer; a high-k dielectric layer (7) is deposited in each trench. The present invention reduces leakage current, improves the reverse breakdown voltage of the device, reduces on-resistance, improves surge resistance, and can be used in power electronic devices.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a trench p-type gallium oxide junction barrier Schottky diode which can be used for power electronic equipment.
Background
In the category of wide bandgap semiconductors, ga 2O3 is significantly better than GaN and SiC by virtue of its bandgap of 4.8eV, breakdown field strength limit of 8MV/cm, and BFOM up to 3400. These characteristics make Ga 2O3 exhibit extremely important research value and broad market application potential in modern power electronics applications where higher power densities and lower energy consumption are sought.
In order to reduce the reverse leakage current of the Ga 2O3 schottky diode, one current strategy is to adopt a fin structure design, disperse the electric field of the schottky contact interface by means of the field plate effect, and ensure that the electric field is uniformly distributed along the field plate. In the forward on state, current is first conducted through the fin epitaxial structure and then flows into the device interior, ultimately reaching the cathode. Although this structure can achieve withstand voltage and forward conduction performance to some extent, it is accompanied by some significant drawbacks. First, the quality and thickness of the insulating medium used in the field plate need to be strictly controlled, because poor quality or improper thickness may cause the electric field to be excessively concentrated somewhere, thereby affecting the reliability and lifetime of the device. Secondly, in the forward conduction process, because the width of the fin structure is limited, the conduction path of the current cannot be effectively expanded when the current passes through the fin epitaxy, and the on-resistance of the device can be increased. Thirdly, since the Ga 2O3 schottky diode lacks conductivity modulation capability, the device is easily damaged in the face of high surge current, thereby limiting its wide application in power circuits. Thus, to overcome these challenges, there is a continuing need to develop Ga 2O3 schottky diodes with lower on-resistance, higher withstand voltage capability, and stronger surge resistance capability.
Patent document CN202310938602.0 discloses a schottky diode based on p-type Ga 2O3 and a preparation method thereof, which comprises the steps of growing GaN on a gallium oxide groove, and preparing a p-type gallium oxide layer by high-temperature oxidation of GaN to form a homogeneous pn junction so as to improve the withstand voltage of the device and increase the power figure of merit of the device. The quality, doping uniformity and interface flatness of the crystal grown by the process are difficult to ensure, new defects and impurities can be introduced in the preparation process, the process steps are complex, and the performance of the pn junction is highly uncertain.
Patent document WOJP18035645 discloses a "schottky barrier diode" which reduces the dielectric breakdown probability by selectively amplifying the trench width, thereby increasing the bottom radius of curvature of the trench. The device prepared by the method can lead to the increase of forward on-resistance and reverse leakage current although the breakdown performance is improved. Meanwhile, the wide groove structure can increase the thermal resistance of the device, and the reliability and the service life of the device in a high-temperature environment are affected.
Disclosure of Invention
Aiming at overcoming the defects of the prior art, the invention provides a groove p-type gallium oxide junction barrier Schottky diode and a preparation method thereof, so as to improve the performance of a homogeneous pn junction of the gallium oxide Schottky diode and reduce the on-resistance and reverse leakage current of the device.
In order to achieve the above purpose, the technical scheme of the invention comprises the following steps:
1. The utility model provides a slot p type gallium oxide junction type barrier schottky diode, includes negative pole ohmic metal layer, n type heavily doped gallium oxide substrate, n type lightly doped gallium oxide drift layer and positive pole schottky metal layer, its characterized in that:
the n-type lightly doped gallium oxide drift layer is internally provided with a plurality of grooves at the upper part thereof so as to change the surface electric field of the device and improve the reverse breakdown voltage;
a p-type gallium oxide region is injected below each groove and forms a gallium oxide homogeneous pn junction with the n-type lightly doped gallium oxide drift layer;
a high-k dielectric layer is deposited in each groove so as to improve the voltage-resistant capability of the device, reduce leakage current and improve switching speed.
Further, the depth of the grooves is 1-1.5 μm, the width is 5-6 μm, and the interval between the grooves is 2-3 μm.
Further, the P-type gallium oxide region, which is implanted by P 3+ or Ni 3+, has a doping concentration of 2×10 18cm-3～2×1020cm-3.
Further, the material of the high-k dielectric layer is Al 2O3 or HfO 2, and the thickness of the high-k dielectric layer is 20 nm-40 nm.
The cathode ohmic metal layer is made of Ti/Au, the thickness of the first layer of Ti is 20 nm-40 nm, the thickness of the second layer of Au metal is 100 nm-200 nm, and the thickness of the n-type heavily doped gallium oxide substrate is 600 mu m-700 mu m and the doping concentration is about 5 multiplied by 10 18cm-3～1×1019cm-3.
The n-type lightly doped gallium oxide drift layer is 10-20 mu m in thickness and 1X 10 12cm-3～5×1012cm-3 in doping concentration, the anode Schottky metal layer is covered on the n-type lightly doped gallium oxide drift layer and is made of a Ni/Au metal layer, the thickness of the first layer of Ni is 40-60 nm, and the thickness of the second layer of Au is 100-200 nm.
2. The preparation method of the groove p-type gallium oxide junction barrier Schottky diode is characterized by comprising the following steps of:
1) Sequentially placing the n-type heavily doped gallium oxide substrate (2) in acetone, isopropanol and piranha solution for cleaning;
2) Growing an n-type lightly doped gallium oxide drift layer (3) on the processed n-type heavily doped gallium oxide substrate (2) by adopting an HVPE technology;
3) Etching a plurality of grooves (5) on the n-type lightly doped gallium oxide drift layer (3) by adopting an ICP etching technology;
4) Ion implantation is carried out below the groove (5), and then a p-type gallium oxide region (6) is formed through rapid thermal annealing;
5) Depositing a cathode ohmic metal layer (1) on the bottom surface of an n-type heavily doped gallium oxide substrate (2), and performing high-temperature annealing to form ohmic contact;
6) Depositing a high-k dielectric layer (7) on the surface of the sample piece after the step 5) is completed by adopting an atomic layer deposition technology;
7) Removing the high-k dielectric layer (7) at the top of the fin by adopting an RIE etching technology, and exposing a Schottky contact area on the lower n-type lightly doped gallium oxide drift layer (3);
8) And (3) growing an anode Schottky metal layer (4) on the surface of the sample piece after the step (7) is completed, and forming Schottky contact with a Schottky contact area on the n-type lightly doped gallium oxide drift layer (3) to complete device preparation.
Compared with the prior art, the invention has the following advantages:
Firstly, the p-type gallium oxide region is prepared in the n-type lightly doped gallium oxide drift layer by utilizing an ion implantation technology, so that the quantity and depth of doped ions can be accurately controlled, and the p-type gallium oxide region with specific hole concentration is formed in the n-type lightly doped gallium oxide drift layer, so that the requirements of different device performances are met;
secondly, the surface of the n-type lightly doped gallium oxide drift layer is provided with the grooves, so that the electric field on the surface of the device can be changed, and the reverse breakdown voltage can be improved;
thirdly, the p-type gallium oxide region is injected below the groove of the groove-type gallium oxide Schottky diode groove, so that a gallium oxide homogeneous pn junction can be formed with the n-type lightly doped gallium oxide drift layer, the device has better depletion characteristic, namely, reverse leakage can be effectively inhibited, the voltage-withstanding capability of the device is improved, the conductivity of the drift region can be regulated, the on-state voltage drop is reduced, and an additional current channel is formed, so that the surge impact-resisting capability is remarkably improved;
Fourth, the invention can optimize the longitudinal electric field distribution of the device, further improve the reverse breakdown voltage, reduce the leakage current, improve the thermal stability of the device and meet the requirements of higher performance and reliability of gallium oxide devices because the high-k dielectric layer is deposited in the groove.
Drawings
Fig. 1 is a schematic structure of a junction barrier schottky diode according to the present invention.
Fig. 2 is a schematic flow chart of the fabrication of the junction barrier schottky diode according to the present invention.
Detailed Description
Specific examples of the present invention will be described in detail below with reference to the accompanying drawings, wherein the experimental methods described in the following examples, unless otherwise specified, are conventional, and wherein the reagents and materials, unless otherwise specified, are commercially available.
Referring to fig. 1, the junction barrier schottky diode of the present example includes a cathode ohmic metal layer 1, an n-type heavily doped gallium oxide substrate 2, an n-type lightly doped gallium oxide drift layer 3, an anode schottky metal layer 4, a trench 5, a p-type gallium oxide region 6, a high-k dielectric layer 7, wherein:
The thickness of the n-type heavily doped gallium oxide substrate 2 is 600-700 mu m, and the doping concentration is about 5 multiplied by 10 18cm-3～1×1019cm-3.
The cathode ohmic metal layer 1 is positioned at the bottom of the n-type heavily doped gallium oxide substrate 2, and is made of Ti/Au materials, wherein the thickness of the first layer of Ti is 20-30 nm, and the thickness of the second layer of Au metal is 150-200 nm.
The n-type lightly doped gallium oxide drift layer 3 is positioned above the n-type heavily doped gallium oxide substrate 2, and has a thickness of 10-20 μm and a doping concentration of 1×10 12cm-3～5×1012cm-3.
The width of the groove 5 is 5-6 mu m, the interval of the groove is 2-3 mu m, and the depth of the groove is 1-1.5 mu m recessed downwards from the upper surface of the n-type lightly doped gallium oxide drift layer 3, so that the electric field on the surface of the device is changed, and the reverse breakdown voltage is improved.
The P-type gallium oxide region 6 is obtained by injecting P 3+ or Ni 3+, has a doping concentration of 2×10 18cm-3～2×1020cm-3, is positioned inside the n-type lightly doped gallium oxide drift layer 3 below the trench 5, and forms a gallium oxide homojunction with the n-type lightly doped gallium oxide drift layer 3.
The high-k dielectric layer 7 is deposited on the inner wall and the bottom of the groove 5, is made of Al 2O3 or HfO 2, and has a thickness of 20-40 nm, and is used for improving the voltage resistance of the device, reducing leakage current and improving the switching speed.
The anode Schottky metal layer 4 is covered on the upper surface of the n-type lightly doped gallium oxide drift layer 3 and the high-k dielectric layer 7 in the groove, the material is a Ni/Au metal layer, the thickness of the first layer Ni is 40-60 nm, and the thickness of the second layer Au is 150-200 nm.
Referring to fig. 2, three embodiments of fabricating a junction barrier schottky diode are presented.
In example 1, a junction barrier schottky diode having a depth of 1 μm, a width of 6 μm, a plurality of trenches 5 with a trench pitch of 3 μm, hfO 2 dielectric layers grown on the bottom and side walls of the trenches 5, and P 3+ ion gallium oxide region implanted into the n-type lightly doped gallium oxide drift layer 3 under the trenches 5 was prepared in the upper portion of the n-type lightly doped gallium oxide drift layer 3 on the n-type heavily doped gallium oxide substrate 2.
Step 1, cleaning the n-type heavily doped gallium oxide substrate, as shown in fig. 2 (a).
1.1 Selecting an n-type heavily doped gallium oxide substrate 2 with the thickness of 600 mu m and the doping concentration of 5 multiplied by 10 18cm-3, and sequentially placing the substrate in acetone, isopropanol and piranha solution for ultrasonic cleaning for 15 minutes;
1.2 Using nitrogen to blow dry for standby.
Step 2, an n-type lightly doped gallium oxide drift layer is grown on the substrate, as shown in fig. 2 (b).
And (3) growing an n-type lightly doped gallium oxide drift layer 3 with the thickness of 10 mu m and the doping concentration of 1 multiplied by 10 12cm-3 on the cleaned n-type heavily doped gallium oxide substrate 2 by adopting an HVPE process under the process condition that GaCl and O 2 are used as precursors, siCl 4 is used as a doping agent and the growth temperature is 850 ℃.
Step 3, etching the trench, as shown in fig. 2 (d).
4.1 Spin-coating photoresist on the n-type lightly doped gallium oxide drift layer 3;
4.2 Exposing the n-type lightly doped gallium oxide drift layer 3 subjected to photoresist spin coating by using a corresponding mask plate to form a pattern;
4.3 Using a photoresist remover to remove photoresist on the exposed sample piece for 5min under the condition of power of 200W so as to remove residual photoresist above the pattern;
4.4 Using mixed gas of BCl 3 and Ar as etching medium, and etching down on the n-type lightly doped gallium oxide drift layer 3 by plasma etching method to form a plurality of grooves 5 with depth of 1 μm and width of 6 μm and groove spacing of 3 μm.
Step 4, ion implantation forms p-type gallium oxide regions, as shown in fig. 2 (e).
5.1 P 3+ cations are implanted in the n-type lightly doped gallium oxide drift layer 3 under each trench 5 at a dose of 2 x 10 15ions/cm-2 and an implantation energy of 100keV;
5.2 The sample after ion implantation is annealed in a nitrogen gas environment at a high temperature of 1000 ℃ for 1min to form a p-type gallium oxide region 6 with a doping concentration of about 2 x 10 20cm-3.
And 5, forming ohmic contact as shown in fig. 2 (c).
3.1 Using electron beam evaporation to grow a Ti/Au cathode ohmic metal layer 1 below the n-type heavily doped gallium oxide substrate 2, wherein the thickness of the first layer Ti is 20nm, and the thickness of the second layer Au is 100nm;
3.2 Placing the sample with the Ti/Au cathode ohmic metal layer in a nitrogen gas environment, and annealing for 1min at a high temperature of 550 ℃ to form ohmic contact between the n-type heavily doped gallium oxide substrate and the Ti/Au cathode ohmic metal layer.
Step 6, growing a high-k dielectric layer, as shown in fig. 2 (f).
And (3) growing a 20nmHfO 2 dielectric layer 7 on the surface of the sample piece after the step (5) by using an atomic layer deposition method under the process conditions of taking tetradiethylaminohafnium and water as precursors, wherein the flow rate of the tetradiethylaminohafnium is 50sccm, the reaction pressure is 50Pa, and the reaction temperature is 250 ℃.
Step 7, etching the dielectric layer, as shown in fig. 2 (g).
And etching the HfO 2 dielectric layer at the top of the fin between the grooves by using a radio frequency power of 300W and a pressure of 20mTorr in the environment of BCl 3 and Ar by adopting an RIE etching technology, so that the Schottky contact area on the lower n-type lightly doped gallium oxide drift layer 3 is exposed by an opening of the HfO 2 dielectric layer.
Step 8, forming schottky contacts, as shown in fig. 2 (h).
And (3) growing a Ni/Au anode Schottky metal layer 4 on the upper surface of the n-type lightly doped gallium oxide drift layer 3 and the HfO 2 dielectric layer 7 in the groove by using electron beam evaporation, wherein the thickness of the first layer of Ni is 40nm, the thickness of the second layer of Au is 150nm, stripping and cleaning, and forming Schottky contact between the n-type lightly doped gallium oxide drift layer 3 and the Ni/Au anode Schottky metal layer 4 to finish device preparation.
In example 2, a junction barrier schottky diode having a depth of 1.2 μm, a width of 5 μm, a trench pitch of 2 μm, a plurality of trenches 5, a HfO 2 dielectric layer grown on the bottom and side walls of the trenches 5, and a Ni 3+ ion gallium oxide region implanted into the n-type lightly doped gallium oxide drift layer 3 under the trenches 5 was fabricated in the upper portion of the n-type lightly doped gallium oxide drift layer 3 on the n-type heavily doped gallium oxide substrate 2.
And step one, cleaning the n-type heavily doped gallium oxide substrate.
An n-type heavily doped gallium oxide substrate 2 with the thickness of 700 mu m and the doping concentration of about 1 multiplied by 10 19cm-3 is selected, sequentially placed in acetone, isopropanol and piranha solution for ultrasonic cleaning for 15 minutes, and dried by nitrogen for standby.
Step two, growing an n-type lightly doped gallium oxide drift layer on the substrate, as shown in fig. 2 (b)
The n-type lightly doped gallium oxide drift layer 3 with the thickness of 15 mu m and the doping concentration of 2 multiplied by 10 12cm-3 is grown on the cleaned n-type heavily doped gallium oxide substrate 2 by adopting an HVPE process under the process conditions that GaCl and O 2 are used as precursors and SiCl 4 is used as a doping agent and the growth temperature is 1000 ℃.
And thirdly, etching the groove.
Firstly, spin coating photoresist on an n-type lightly doped gallium oxide drift layer 3, and exposing the n-type lightly doped gallium oxide drift layer 3 subjected to spin coating photoresist by using a corresponding mask plate to form a pattern;
Then, photoresist is removed from the exposed sample piece by using a photoresist remover under the condition of power of 250W for 4min to remove residual photoresist above the pattern, and then, a mixed gas of BCl 3 and Ar is used as an etching medium to etch downwards on the n-type lightly doped gallium oxide drift layer 3 by using a plasma etching method to form a plurality of grooves 5 with depth of 1.2 mu m, width of 5 mu m and groove spacing of 2 mu m.
And step four, ion implantation is carried out to form a p-type gallium oxide region.
Ni 3+ cations are implanted into the n-type lightly doped gallium oxide drift layer 3 below each trench 5, the implantation dosage is 2 multiplied by 10 15ions/cm-2, the implantation energy is 500keV, and the sample piece subjected to ion implantation is placed in a nitrogen gas environment and annealed at a high temperature of 1200 ℃ for 1min to form a p-type gallium oxide region 6, wherein the doping concentration is about 2 multiplied by 10 18cm-3. .
Step five, ohmic contact is formed
A Ti/Au cathode ohmic metal layer 1 having a thickness of 40nm/200nm was grown under the n-type heavily doped gallium oxide substrate 2 using electron beam evaporation, and the sample was annealed at a high temperature of 550 ℃ for 1min in a nitrogen atmosphere to form ohmic contact between the n-type heavily doped gallium oxide substrate 2 and the Ti/Au cathode ohmic metal layer 1.
And step six, growing a high-k dielectric layer.
And (3) setting a process condition that trimethylaluminum and water are used as precursors, the trimethylaluminum flow is 50sccm, the reaction air pressure is 100Pa, the reaction temperature is 250 ℃, and growing a 40nm HfO 2 dielectric layer on the surface of the sample piece after the step (5) is completed by utilizing an atomic layer deposition method.
And step seven, etching the dielectric layer.
And setting radio frequency power of 350W, pressure of 25mTorr and gas environment of BCl 3 and Ar, and etching a dielectric layer on the top of the fin between each two grooves by adopting an RIE etching technology to enable a Schottky contact area on the lower n-type lightly doped gallium oxide drift layer 3 to be exposed by an HfO 2 dielectric layer opening.
And step eight, forming a Schottky contact.
And (3) growing a 50nm/150nm Ni/Au anode Schottky metal layer 4 on the upper surface of the n-type lightly doped gallium oxide drift layer 3 and the HfO 2 dielectric layer 7 in the groove by using electron beam evaporation, stripping and cleaning, and forming Schottky contact between the n-type lightly doped gallium oxide drift layer 3 and the Ni/Au anode Schottky metal layer 4 to finish device preparation.
In example 3, a junction barrier schottky diode having a depth of 1.2 μm, a width of 5 μm, a trench pitch of 2 μm, a plurality of trenches 5, an Al 2O3 dielectric layer grown on the bottom and side walls of the trenches 5, and a P 3+ ion gallium oxide region implanted into the n-type lightly doped gallium oxide drift layer 3 under the trenches 5 was fabricated in the upper portion of the n-type lightly doped gallium oxide drift layer 3 on the n-type heavily doped gallium oxide substrate 2.
And step A, cleaning the n-type heavily doped gallium oxide substrate.
A1 An n-type heavily doped gallium oxide substrate 2 with the thickness of 650 mu m and the doping concentration of 6.5 multiplied by 10 18cm-3 is selected and sequentially placed in acetone, isopropanol and piranha solution for ultrasonic cleaning for 15 minutes;
A2 Using nitrogen to blow dry for standby.
Step B, growing an n-type lightly doped gallium oxide drift layer on the substrate, as shown in FIG. 2 (B)
And (3) growing an n-type lightly doped gallium oxide drift layer 3 with the thickness of 20 mu m and the doping concentration of 5 multiplied by 10 12cm-3 on the cleaned n-type heavily doped gallium oxide substrate 2 by adopting an HVPE process.
The growth process conditions are that GaCl and O 2 are used as precursors, siCl 4 is used as a doping agent, and the growth temperature is 1100 ℃.
And C, etching the groove.
D1 Spin-coating photoresist on the n-type lightly doped gallium oxide drift layer 3, and exposing the n-type lightly doped gallium oxide drift layer 3 subjected to spin-coating photoresist by using a corresponding mask plate to form a pattern;
d2 Using a photoresist remover to remove photoresist on the exposed sample piece for 3min under the condition of power of 300W so as to remove residual photoresist above the pattern;
D3 Placing the photoresist-removed sample in a mixed gas of BCl 3 and Ar, and etching downwards on the n-type lightly doped gallium oxide drift layer 3 by using a plasma etching method to form a plurality of grooves 5 with the depth of 1.5 mu m, the width of 6 mu m and the groove spacing of 2 mu m.
And D, ion implantation to form a p-type gallium oxide region.
E1 P 3+ cations are implanted in the n-type lightly doped gallium oxide drift layer 3 under each trench 5 at a dose of 2.5 x 10 13ions/cm-2 and an implantation energy of 40keV;
E2 The sample after ion implantation is annealed in a nitrogen gas environment at a high temperature of 1000 ℃ for 1min to form a p-type gallium oxide region 6 with a doping concentration of about 2 x 10 19cm-3. .
Step E, forming ohmic contact
C1 Using electron beam evaporation to grow a Ti/Au cathodic ohmic metal layer 1 under an n-type heavily doped gallium oxide substrate 2, wherein the first layer Ti has a thickness of 30nm and the second layer Au has a thickness of 150nm;
C2 A sample piece with the Ti/Au cathode ohmic metal layer is placed in a nitrogen gas environment and annealed at a high temperature of 550 ℃ for 1min to form ohmic contact between the n-type heavily doped gallium oxide substrate 2 and the Ti/Au cathode ohmic metal layer 1.
And F, growing a high-k dielectric layer.
And (5) growing a 30nmAl 2O3 dielectric layer on the surface of the sample piece after the step (5) is completed by utilizing an atomic layer deposition method.
The atomic layer deposition process conditions are that trimethylaluminum and water are used as precursors, the trimethylaluminum flow is 80sccm, the reaction air pressure is 120Pa, and the reaction temperature is 300 ℃.
And G, etching the dielectric layer.
And etching the dielectric layer at the top of the fin between the grooves by using a RIE etching technology under the conditions of BCl 3 and Ar and using 400W radio frequency power and 30mTorr pressure, so that the Al 2O3 dielectric layer exposes a Schottky contact area on the lower n-type lightly doped gallium oxide drift layer 3.
And step H, forming a Schottky contact.
H1 And (3) growing a Ni/Au anode Schottky metal layer 4 on the upper surface of the n-type lightly doped gallium oxide drift layer 3 and the Al 2O3 dielectric layer 7 in the groove by using electron beam evaporation, wherein the thickness of the first layer Ni is 60nm, the thickness of the second layer Au is 200nm, stripping and cleaning, and forming Schottky contact between the n-type lightly doped gallium oxide drift layer 3 and the Ni/Au anode Schottky metal layer 4 to finish device preparation.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that, for those skilled in the art, several variations and modifications may be made without departing from the concept of the present invention, for example, P 3+ cations and Ni 3+ cations may be used for ion implantation in addition to the specific embodiment, any parameters within the range of the process condition parameters of ion implantation may be used in addition to the specific embodiment, the dielectric layer may deposit other high-k dielectrics as the dielectric layer in addition to HfO 2,Al2O3 used in the specific embodiment, any parameters within the range of the process parameters of depositing the dielectric layer may be used in addition to the specific embodiment, and the size of the trench may be modified according to the actual requirements in addition to the specific embodiment etching parameters, but these modifications based on the concept of the present invention are all within the scope of the present invention.
Claims (10)
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