CN119620819A - Current compensation circuit, logarithmic detector and chip - Google Patents
Current compensation circuit, logarithmic detector and chip Download PDFInfo
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- CN119620819A CN119620819A CN202510151792.0A CN202510151792A CN119620819A CN 119620819 A CN119620819 A CN 119620819A CN 202510151792 A CN202510151792 A CN 202510151792A CN 119620819 A CN119620819 A CN 119620819A
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
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Abstract
本公开实施例公开了一种电流补偿电路、对数检波器和芯片。该电流补偿电路包括：电流镜，包括第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管分别包括第一端、第二端和控制端，所述电流镜被配置为将流过所述第一晶体管第一端的第一电流镜像到所述第二晶体管的第一端，所述第二晶体管的第一端输出补偿电流；电阻模块，连接所述第一晶体管的第一端，所述电阻模块的电阻值和所述第一晶体管第一端的第一电压用于确定所述第一电流的大小；熔丝模块，连接所述电阻模块和/或所述第一晶体管的第一端，用于基于熔断状态输出第一控制信号，所述第一控制信号用于校准所述电阻模块的电阻值大小和/或所述第一电压的大小。
The embodiments of the present disclosure disclose a current compensation circuit, a logarithmic detector and a chip. The current compensation circuit includes: a current mirror, including a first transistor and a second transistor, the first transistor and the second transistor respectively including a first end, a second end and a control end, the current mirror is configured to mirror the first current flowing through the first end of the first transistor to the first end of the second transistor, and the first end of the second transistor outputs a compensation current; a resistance module, connected to the first end of the first transistor, the resistance value of the resistance module and the first voltage of the first end of the first transistor are used to determine the magnitude of the first current; a fuse module, connected to the resistance module and/or the first end of the first transistor, for outputting a first control signal based on a blown state, the first control signal is used to calibrate the resistance value of the resistance module and/or the magnitude of the first voltage.
Description
Technical Field
Embodiments of the present disclosure relate to the field of electronic devices, and to, but are not limited to, a current compensation circuit, logarithmic detector, and chip.
Background
Common detectors or signal processors often require precision calibration, such as detectors, ring oscillators, amplifiers, etc., because of process angle mismatch and process variation, and detection or processing errors.
Taking a logarithmic detector as an example, which is commonly used to measure and detect the amplitude of a signal, has the property of converting the input signal into an output voltage or current proportional to the logarithm of the input signal. The logarithmic detector is mainly used for equipment such as radars, satellite communication, microwave point-to-point communication, test instruments, radio frequency spectrum monitoring and the like, and is suitable for application scenes such as signal intensity indication, broadband spectrum detection, fault detection, automatic gain control and the like.
Different logarithmic detectors influence the performance of the logarithmic detectors due to process angle mismatch and process deviation, so that logarithmic curves of the different logarithmic detectors are different, and the intercept of the logarithmic curves is caused to have deviation, wherein the logarithmic curves are curves of output voltage and input power.
The deviation of devices such as logarithmic detectors can be adjusted by means of current correction to compensate for the performance differences of the different devices themselves, so how to implement current calibration is one of the problems to be considered in the art.
Disclosure of Invention
In view of the foregoing, embodiments of the present disclosure provide a current compensation circuit, logarithmic detector, and chip for outputting an adjustable current.
In one aspect, embodiments of the present disclosure provide a current compensation circuit, comprising:
a current mirror comprising a first transistor and a second transistor, the first transistor and the second transistor each comprising a first terminal, a second terminal, and a control terminal, the current mirror configured to mirror a first current flowing through the first terminal of the first transistor to the first terminal of the second transistor, the first terminal of the second transistor outputting a compensation current;
The resistor module is connected with the first end of the first transistor, and the resistance value of the resistor module and the first voltage of the first end of the first transistor are used for determining the magnitude of the first current;
And the fuse wire module is connected with the resistor module and/or the first end of the first transistor and is used for outputting a first control signal based on the fusing state, and the first control signal is used for calibrating the resistance value of the resistor module and/or the first voltage.
According to the current compensation circuit, the fuse module is a programmable memory, data is stored based on the fusing state of an internal fuse, the internal fuse is fused based on the magnitude of compensation current to be output, and a first control signal is output by the fuse module according to the fusing state and used for calibrating the resistance value of the resistance module and/or the magnitude of the first voltage. The resistance value of the resistance module and the first voltage of the first end of the first transistor are used for determining the magnitude of the first current, so that the magnitude of the first voltage of the first end of the first transistor of the current mirror and/or the resistance value of the resistance module can be adjusted through the fuse module through adjustment, and the magnitude of the first current is adjusted, the compensation current is the copy of the first current, the compensation current changes along with the first current, and therefore the magnitude of the compensation current can be adjusted through a first control signal output by the fuse module, accurate calibration of the magnitude of the compensation current is achieved, and the calibration precision and the calibration efficiency are improved.
When the fuse module is connected with the resistor module and the first end of the first transistor at the same time, the first control signal is used for calibrating the resistance value of the resistor module and the first voltage, so that the adjustment of at least two dimensions such as the first voltage, the resistance value of the resistor module and the like can be realized through the fuse module, the multistage adjustment of the output compensation current of the current compensation circuit can be realized, and the precision of the compensation current is further improved.
In some embodiments, the resistance module includes one or more variable resistance units and one or more resistor array units connected in series, where the resistance value can be adjusted by the variable resistance units or the resistor array units, that is, the resistance value has two-stage adjustment, and the current compensation circuit can realize three-stage adjustment together with the adjustment of the first voltage value, so as to realize accurate calibration of the compensation current, which is beneficial to improving calibration precision and calibration efficiency.
In addition, the current output circuit is applied to the logarithmic detection component to calibrate the logarithmic detector, the logarithmic curve intercept of the logarithmic detector can be calibrated by debugging the current output circuit, abnormal deviation of the logarithmic curve intercept caused by process pin mismatch, process deviation and the like of different logarithmic detector products is effectively reduced, and therefore the detection precision of the logarithmic detection component is improved, and the product yield is improved.
Drawings
FIG. 1 is a block diagram of a logarithmic detector in an embodiment of the disclosure;
FIG. 2 is a block diagram of a circuit configuration for calibrating the intercept of a logarithmic detector in an embodiment of the disclosure;
FIG. 3 is a schematic diagram of a current compensation circuit according to an embodiment of the disclosure;
FIG. 4 is a schematic diagram of another current compensation circuit provided by an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a current compensation circuit and one of the resistor modules according to an embodiment of the disclosure;
FIG. 6 is a schematic diagram of a resistance characteristic curve of a MOS transistor according to an embodiment of the disclosure;
Fig. 7A and 7B are schematic diagrams of two resistor array units in the current compensation circuit according to the embodiment of the disclosure;
FIG. 8 is a schematic diagram of a current compensation circuit and a voltage follower thereof according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a voltage switching module in a current compensation circuit according to an embodiment of the disclosure;
FIG. 10 is a schematic diagram of a fuse module in a current compensation circuit according to an embodiment of the disclosure;
FIG. 11 is a schematic diagram of yet another current compensation circuit provided by an embodiment of the present disclosure;
FIG. 12 is a flow chart of a method for calibrating a logarithmic detector according to an embodiment of the disclosure;
fig. 13 is a block diagram of a chip according to an embodiment of the disclosure.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. In the presently disclosed embodiments, the terms "first," "second," "third," "fourth," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", "a third" and a fourth "may explicitly or implicitly include one or more such feature.
It should be understood that in the description of the embodiments of the present disclosure, unless explicitly stated and limited otherwise, the terms "connected" and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected, directly connected, indirectly connected through an intermediary, or communicating between two elements.
The terms involved in the embodiments of the present disclosure are explained as follows:
Logarithmic detector-the amplitude of the signal to be measured and detected, the output dc signal (e.g. voltage signal) of which is proportional to the logarithm of the voltage amplitude of the input signal.
Logarithmic curve, which is the curve of the change of the logarithmic detector along with the change of the input signal and the output DC voltage signal. The abscissa of the logarithmic curve is the signal power of the input radio frequency signal, which may be in milliwatt decibels (dBm), for example. The ordinate of the logarithmic curve is the DC voltage of the output signal, which may be in volts (V) or millivolts (mV).
Intercept of logarithmic curve: voltage value corresponding to the intersection of logarithmic curve and ordinate axis. The intercept of the logarithmic curve can also be understood as the output offset of the logarithmic detector.
Logarithmic amplifier-amplifier with input and output in logarithmic amplification relationship.
Efuse burn-in Efuse is a fuse-based device, and belongs to one-time programmable memories. The one-time change of the circuit is usually achieved by blowing or shorting a device by means of a large current.
Process Corner (Process Corner) refers to the case of different Process variations and parameter variations that are considered in designing and manufacturing the chip. On a wafer, it is impossible that the average drift velocity of carriers of each chip is the same, and the characteristics of different chips are different with different voltages and temperatures. The different Process characteristics are classified into PVT (Process Voltage, temperature) characteristics and the like. The process characteristics are also divided into different process limits, called process corners. There may be some variation in the logarithmic performance of the detector chip at different process angles.
The logarithmic detector is based on the working principle of a logarithmic amplifier, and is used for amplifying an input signal after taking the logarithm, and then carrying out anti-logarithmic operation on the amplified signal to finally obtain a direct current output signal. Since it performs a logarithmic operation and an anti-logarithmic operation, the input signal of the logarithmic detector and the dc output signal are in a linear relationship. The logarithmic detector is mainly used for equipment such as radars, satellite communication, microwave point-to-point communication, test instruments, radio frequency spectrum monitoring and the like, and is suitable for application scenes such as signal intensity indication, broadband spectrum detection, fault detection, automatic gain control and the like. The logarithmic detector has good application prospect and research significance.
Fig. 1 is a block diagram of a logarithmic detector for implementing logarithmic detection. As shown in fig. 1, the logarithmic detector 100 is composed of a plurality of modules, including a radio frequency logarithmic amplifier 110, a current operation module 120, an output module 130, and a feedback module 140. After the detected radio frequency signal RF is input, the detected radio frequency signal RF is logarithmically amplified by the radio frequency logarithmic amplifier 110 and outputs a current I corresponding to the amplitude, the current operation module 120 performs an addition operation or a subtraction operation on the input current and outputs a current, and the output module 130 converts the current into a direct current voltage (DC) and outputs the direct current. The logarithmic detector may further include a feedback module 140, an input end of the feedback module 140 is connected to an output end of the output module 130, an output end of the feedback module 140 is connected to an input end of the current operation module 120, and the feedback module 140 converts the voltage output by the DC into current and outputs the current to the current operation module 120. The feedback loop formed by the feedback module 140 is beneficial to realizing stable direct-current voltage output. In some cases, an anti-logarithmic circuit is further included between the rf logarithmic amplifier 110 and the current operation module 120, and the anti-logarithmic circuit may perform an anti-logarithmic operation on the current I by using an exponential characteristic of a diode or a transistor. The inverse logarithmically calculated current I is linearly related to the radio frequency signal RF.
In some embodiments, the input of the feedback module 140 may not be connected to the output of the output module 130, but rather provide a fixed voltage to the input of the feedback module 140. However, the circuit shown in fig. 1 cannot calibrate the intercept of the logarithmic curve, and if the intercept of the logarithmic curve is not calibrated, the logarithmic curve of the logarithmic detector may be scattered to a certain extent in different batches of wafers or different wafer areas, thereby affecting the screening of good products.
It can be understood that the logarithmic detector amplifies the input radio frequency signal by the logarithmic amplifier and outputs a current corresponding to the amplitude, and the magnitude of the output current corresponds to the signal to be detected (i.e. the amplitude of the input radio frequency signal) one by one. Taking the logarithmic detector with the logarithmic detector shown in fig. 1 as a negative slope logarithmic curve as an example, assuming that the logarithmic curve slope of the logarithmic detector is 20mV/dBm, the power of the signal to be detected is-20 dBm, the current I flowing into the current operation module is 0.6mA, the DC voltage output by the output module 130 is 0.8V, and the output voltages of chips in different batches are 0.7V-0.9V due to the dispersion of the process, which may be caused by the deviation of the logarithmic amplifier caused by the process, so that the current I flowing into the current operation module 120 has the deviation, for example, the current I flowing into the current operation module 120 of chips in different batches is 0.5 mA-0.7 mA. Thus, for the same rf input signal, there is a difference between the detected values of 0.2V/(20 mV/dBm) =10dbm, so that the intercept error of logarithmic curves detected by different batch detectors is large.
The disclosed embodiments provide a scheme that can be used to calibrate the intercept of a logarithmic detector, as shown in fig. 2, by outputting a compensation current I0 using a current compensation circuit 200, which is provided to a current operation module 120 of the logarithmic detector 100. The current compensation circuit 200 includes a fuse module for fixing a value of the compensation current I0. Specifically, in the calibration stage before use, the required compensation current I0 is determined according to the value of the DC output voltage, then the fuse module in the current compensation circuit 200 is programmed according to the required compensation current I0, so as to ensure that the current compensation circuit 200 can output the compensation current I0 with proper magnitude, and in operation, the first control signal output by the fuse module in the current compensation circuit 200 can make the control current compensation circuit 200 output the proper compensation current I0, thereby effectively compensating the intercept error of the logarithmic detector logarithmic curve caused by batch difference.
Specifically, embodiments of the present disclosure provide a current compensation circuit. As shown in fig. 3, a current compensation circuit 200 provided in an embodiment of the present disclosure includes:
A current mirror 220 including a first transistor 221 and a second transistor 222, the first transistor 221 and the second transistor 222 including a first terminal, a second terminal, and a control terminal, respectively, the current mirror 220 being configured to mirror a first current I1 flowing through the first terminal of the first transistor 221 to the first terminal of the second transistor 222, the first terminal of the second transistor 222 outputting a compensation current I0, wherein a voltage of the first terminal of the first transistor 221 is a first voltage V1;
The resistor module 230 is connected to the first end of the first transistor 221, the resistor module 230 may be connected in series between the first end of the first transistor 221 and the ground, and the resistance value R and the first voltage V1 of the resistor module 230 are used to determine the magnitude of the first current I1;
The fuse module 210 may include a plurality of fuses, the blown states of the fuses are used for storing data, the blown states of the internal fuses may reflect the magnitude of the compensation current, and the fuse module 210 is connected to the resistor module 230 and/or the first terminal of the first transistor 221, where the fuse module 210 is shown as being connected to the resistor module 230 and the first terminal of the first transistor 221, respectively. The fuse module 210 is configured to output a first control signal T1 based on the blown state, where the first control signal T1 is used to calibrate the magnitude of the resistance value R and/or the magnitude of the first voltage V1 of the resistance module 230.
In the embodiment of the present disclosure, the currents of the two current branches of the current mirror 220 are mirror images of each other, so the magnitude of the compensation current I0 output on one branch (the branch where the second transistor 222 is located) can be changed by adjusting the magnitude of the first current I1 on the other branch (the branch where the first transistor 221 is located). Accordingly, the relevant means for adjusting the first current I1 may be connected to the first terminal or the second terminal of the first transistor 221, thereby controlling the magnitude of the first current I1 on the current path in which the first transistor 221 is located.
It should be noted that the current mirror may be a mirror structure including two transistors, and the structure of the current mirror may include a reference transistor and a mirror transistor, where the control terminals of the two transistors are connected, so that they have the same on state. The current in the current path of the reference transistor is mirrored completely to the current path of the mirror transistor, i.e. the mirror current is made equal to the reference current (which may be provided by a current source in series with the reference transistor). It will be appreciated that if the dimensions (channel width to length ratio) of the reference transistor and the mirror transistor are different, the mirrored current may also have a corresponding proportional relationship to the reference current, and therefore a current mirror may be used to output an output current that is a fixed proportion to the reference current.
In an embodiment, the current mirror may be a PMOS current mirror, and the first transistor 221 and the second transistor 222 are PMOS transistors, so that the second terminal of the first transistor 221 and the second terminal of the second transistor 222 are both connected to the power supply terminal VDD, and the resistor module 230 is connected between the first terminal of the first transistor 221 and the ground terminal GND. In another embodiment, the current mirror may be an NMOS current mirror, and the first transistor 221 and the second transistor 222 are both NMOS, so that the second terminal of the first transistor 221 and the second terminal of the second transistor 222 are both connected to the ground GND, and the resistor module 230 is connected between the first terminal of the first transistor 221 and the power supply terminal VDD. In other embodiments, the current mirror 220 may be a self-bias current mirror, a wilson current mirror, a "cascode" current mirror, or the like, and the first transistor 221 may include two or more transistors with source and drain connected in sequence, the second transistor 222 may include two or more transistors with source and drain connected in sequence, and the first and second transistors 221 and 222 may be transistors in the self-bias current mirror, for example, the self-bias current mirror and the "cascode" current mirror, respectively.
In the disclosed embodiment, the first transistor 221 acts as a reference transistor in the current mirror 220 and the second transistor 222 acts as a mirror transistor in the current mirror 220. In the embodiment of the disclosure, the first transistor and the second transistor have the same size (the output compensation current I0 is equal to the first current I1) as an example, and in practical application, the proportional relationship between the sizes of the first transistor and the second transistor may be set according to the requirement, so as to obtain the compensation current I0 with a fixed proportion to the first current I1.
In the embodiment of the disclosure, the first transistor 221 and the resistor module 230 are connected in series on the current path of the first current I1, and the fuse module 210 is utilized to adjust the resistance value of the resistor module 230 or adjust the first voltage V1 at the first end of the first transistor 221 to adjust the magnitude of the first current I1, so that the magnitude of the output compensation current I0 can be adjusted by the fuse module 210.
In the embodiment of the present disclosure, the magnitude of the first current I1 may be adjusted by the fuse module 210. Specifically, the fuse module 210 has a one-time editable capability, and can be written into the first control signal T1, and the first control signal T1 can be applied to the first end of the first transistor 221 to adjust the first voltage V1, or applied to the resistor module 230 to adjust the resistance of the resistor module 230, so as to edit the magnitude of the first current I1.
For the process deviation of the logarithmic detector or other devices such as an amplifier, the logarithmic detector can be calibrated before the product is used to determine the required compensation current I0, so that after the required compensation current I0 is determined, the fuse module 210 can be utilized to perform one-time editing to output a designated first control signal T1, and further obtain a first current I1 corresponding to the required compensation current I0.
The first control signal T1 output by the fuse module 210 may include one or more first control signals for calibrating the resistance value of the resistor module 230 and the magnitude of the first voltage V1, so that the first current I1 can be controlled from at least two dimensions, and coarse calibration and fine calibration can be further realized. Illustratively, the fuse module 210 may include a plurality of fuse arrays, different ones of the fuse arrays for outputting different ones of the first control signals T1.
In addition, the current compensation circuit may also include one or more resistor modules connected in series or parallel to the first current I1 path, and each resistor module may have an adjustable resistance value, respectively. The current compensation circuit may include two or more resistor modules connected in series or parallel, where the resistance range of each resistor module is different, so that current adjustment in different ranges may be implemented, thereby further improving accuracy of the compensation current.
Because the deviation of different logarithmic detectors is different, the data written in the fuse module in different logarithmic detectors is different, and the fuse module needs to know the data to be written in advance. To obtain the data to be written to the fuse block, in some embodiments, as shown in FIG. 4, the current compensation circuit 200 further includes:
The output end of the one or more voltage switching modules 240 (e.g., the voltage switching module 240a and the voltage switching module 240b shown in fig. 4) is configured to output a plurality of second control signals T2, wherein the second control signals T2 are used for calibrating the resistance value of the resistance module 230 and/or the magnitude of the first voltage V1;
One or more check modules 250 (such as check module 250a and check module 250b shown in fig. 4) have input terminals connected to the output terminals of the corresponding voltage switching module 240 and to the output terminal of the fuse module 210, the output terminal of the check module 250a is connected to the first terminal of the first transistor 221, the output terminal of the check module 250b is connected to the resistor module 230, the check module 250a is configured to select one of the second control signal T2 and the first control signal T1 to output to control the magnitude of the first voltage V1, and the check module 250b is configured to select one of the second control signal T2 and the first control signal T1 to output to control the magnitude of the resistor module 230.
As mentioned above, in order to calibrate the process angle deviation of the logarithmic detector and other devices, calibration and debugging are required before the product is used, and the required compensation current I0 is determined. Therefore, in the embodiment of the disclosure, during calibration, the check module 250 selects the second control signal T2 to output, the voltage switching module 240 provides the switchable second control signal T2 to find the second control signal with a suitable size as the target control signal, and writes the target control signal into the fuse module, and during product use, the check module 250 selects the first control signal T1 to output, because the data in the fuse module is not lost due to power-down, the fuse module can provide the stable first control signal T1, and the current compensation circuit can provide a stable and reliable compensation current to compensate the process corner deviation of the logarithmic detector and other devices.
The check module 250 may be implemented by a signal selector, a Multiplexer (MUX), or other logic circuit that selects one of a plurality of input signals as an output signal. The check module has multiple inputs and a single output, and may further have a selection control signal terminal for receiving a selection signal for determining a selected input signal as an output signal and outputting the selected input signal. For example, in the case where the check module 250 has two input signals T1 and T2, the selection signal may include a one-bit binary digital signal of 0 or 1, the input signal T1 may be taken as an output signal when the selection signal is 0, and the input signal T2 may be taken as an output signal when the selection signal is 1.
Here, the first control signal T1 provided for the fuse block 210 or the second control signal T2 provided for the voltage switching block 240 may be selected by the check block 250 as an output signal. In addition, since there may be a plurality of first control signals T1 and a plurality of second control signals T2, the check module 250 may also be used to select one of the plurality of second control signals T2 or output one of the first control signals T1.
The first control signal T1 and the second control signal T2 may be digital signals or analog signals.
In some embodiments, the voltage switching module 240 may be located in the same chip as the fuse module, and in other embodiments, the voltage switching module 240 may be an external test module, and after obtaining the required second control signal T2, the voltage switching module 240 may be removed after editing the fuse module 210 correspondingly and switching the check module 250 to select the output of the fuse module 210.
In some embodiments, as shown in fig. 5, the resistance module 230 includes:
the variable resistance unit Rb, the resistor array unit Ra, or the variable resistance unit Rb and the resistor array unit Ra connected in series are shown in the figure, but in other embodiments, only the variable resistance unit Rb or the resistor array unit Ra may be included. The check modules 250 include 3 check modules 250a (240 a for the voltage switching module connected thereto) connected to the first terminal of the first transistor 122, 250b (240 b for the voltage switching module connected thereto) connected to the control terminal of the variable resistance unit Rb, and 250c (240 c for the voltage switching module connected thereto) connected to the resistor array unit Ra.
In the calibration stage, the control end of the variable resistance unit Rb receives the second control signal T2 output by the check module 250b, and in the calibrated use, the control end of the variable resistance unit Rb receives the first control signal T1 output by the check module 250b to control the first resistance value of the variable resistance unit Rb;
the resistor array unit Ra may include a plurality of resistor elements ri (I represents the number of the resistor elements, 0.ltoreq.i.ltoreq.n, and the total number of the resistor elements in the resistor array unit Ra is n+1), and is configured to change the number of the resistor elements ri in the path where the first current I1 is connected by the first control signal T1 or the second control signal T2 output by the check module 250c, so as to control the second resistance value of the resistor array unit Rb.
In fig. 5, the variable resistance unit Rb is connected in series between the first voltage V1 and the resistor array unit Ra, and in other embodiments, the resistor array unit Ra may be connected in series between the first voltage V1 and the variable resistance unit Rb.
It can be understood that, since the variable resistance unit Rb is connected in series with the resistor array unit Ra, the respective resistance values of the variable resistance unit Rb and the resistor array unit Ra affect the magnitude of the first current I1 on the whole path, and the larger the sum of the first resistance value and the second resistance value is, the smaller the first current I1 is. While two different types of resistors may provide current control with different accuracy. For example, the adjustment range of the first resistance value is smaller, fine adjustment of the first current I1 can be achieved, and the adjustment range of the second resistance value is larger, so that coarse adjustment of the first current I1 can be achieved.
Through the design, resistance of the resistance module can be adjusted through the variable resistance unit or the resistance array unit, that is to say, the resistance has two-stage regulation, and the regulation of the first voltage value is added, and the current compensation circuit can realize three-stage regulation altogether to realize the accurate calibration of compensation current size, be favorable to promoting calibration precision and calibration efficiency.
In some embodiments, the variable resistance unit Rb includes a third transistor;
the control end of the third transistor receives the first control signal or the second control signal, and the first end and the second end of the third transistor are connected in series with the resistor array unit so as to adjust the first resistance value of the third transistor.
It can be appreciated that the variable resistance unit Rb is realized here by using the resistance characteristics of the transistor. Taking a Metal-Oxide-semiconductor field effect transistor (MOSFET, abbreviated as MOS transistor) as an example, when a voltage applied to a gate thereof is within a certain range, the MOS transistor has a resistance characteristic in which a resistance varies with the voltage of the gate.
Fig. 6 shows a variation curve between the gate voltage and the on-resistance of the MOS transistor, i.e., the abscissa represents the gate voltage Vg and the ordinate represents the on-resistance Ron. Fig. 6 (1) is an overall switching characteristic of the MOS transistor, and fig. 6 (2) is an enlarged view within a circled range of fig. 6 (1), wherein a resistance unit magnitude of an ordinate of fig. 6 (1) is kΩ, a current unit magnitude of an ordinate of fig. 6 (2) is Ω, and units of abscissas of fig. 6 (1) and fig. 6 (2) are volts. It can be seen that the MOS tube has the characteristic that the on-resistance is uniformly changed along with the voltage in a certain voltage range, so that the resistance of the MOS tube can be adjusted by adjusting the grid voltage in the range by utilizing the characteristic.
In other embodiments, the variable resistance unit Rb may be a variable resistor other than a transistor, and the embodiments of the present disclosure are not limited thereto.
In some embodiments, as shown in fig. 7A, the resistor array unit Ra includes:
The first switch k1i comprises a plurality of first resistor elements r1i connected in series and a plurality of first switches k1i, wherein a first end and a second end of the first switches k1i are connected with the first resistor elements r1i in parallel, and a control end of the first switches k1i receives a corresponding first control signal T1 or a second control signal T2.
When the first switch k1I is turned off, the corresponding parallel first resistor element r1I is connected to a path through which the first current I1 flows, and the first control signal T1 or the second control signal T2 is used for controlling the first switch k1I.
Specifically, there may be a plurality of first control signals T1 or second control signals T2 respectively connected to each of the first switches k1i, when the first control signals T1 or second control signals T2 are on signals (voltage or current signals enabling the first switches k1i to be in an on state), the connected first switches k1i are enabled to be in an on state, the corresponding first resistive elements r1i are shorted and thus not connected to the paths, and when the first control signals T1 or second control signals T2 are off signals (voltage or current signals enabling the first switches k1i to be in an off state), the connected first switches k1i are enabled to be in an off state, and the corresponding first resistive elements r1i are connected to the paths. It should be noted that, if the first switches k1i corresponding to the plurality of first resistor elements r1i connected in series in the resistor array unit Ra are all in the on state, none of the plurality of first resistor elements r1i is connected to the circuit, and at this time, the total resistance value of the resistor array unit Ra is approximately equal to 0.
It is understood that the resistances of the plurality of first resistive elements r1i may be equal, so that the total resistance of the resistor array unit Ra may be adjusted by changing the number of the first resistive elements r1i of the access path. Of course, the resistance values of the plurality of first resistor elements r1i may also be different, and designed according to actual requirements, so as to realize flexible resistance adjustment.
In some embodiments, as shown in fig. 7B, the resistor array unit Ra includes:
The first ends and the second ends of the second switches k2i are connected with the second resistor elements r2i in series, and the control ends of the second switches k2i receive corresponding first control signals T1 or second control signals T2.
When the second switch k2I is turned on, the corresponding series-connected second resistor element r2I is connected to a path through which the first current I1 flows, and the first control signal T1 or the second control signal T2 is used for controlling the second switch.
Similarly to the case of the series connection, the first control signal T1 or the second control signal T2 may be plural and connected to each of the second switches k2i, respectively. When the first control signal T1 or the second control signal T2 is an on signal (a voltage or current signal enabling the second switch k2i to be in an on state), the second switch k2i connected in series is enabled to be in an on state, and the corresponding second resistor r2i is connected to the circuit, and when the first control signal T1 or the second control signal T2 is an off signal (a voltage or current signal enabling the second switch k2i to be in an off state), the second switch k2i connected to be in an off state, the branch where the corresponding second resistor r2i is located is disconnected, so that the second resistor r2i is not connected to the circuit.
It is understood that the resistances of the plurality of second resistive elements r2i may be equal, so that the total resistance of the resistor array unit Ra may be adjusted by changing the number of the second resistive elements r2i of the access path. Of course, the resistance values of the plurality of second resistor elements r2i can also be different, and the design is performed according to actual requirements, so that flexible resistance value adjustment is realized. Furthermore, it should be noted that, in the case of a plurality of second resistive elements r2i connected in parallel, each branch of the second resistive element r2i connected to the circuit is only turned on, so at least one second resistive element r2i should be connected, otherwise the circuit will be disconnected.
It should be noted that, for the resistor array unit Ra, the first switch or the second switch corresponding to each resistor element may receive the control signal through one check module 250. The input signal of the check module 250 may include only an on voltage for controlling the first switch or the second switch to be turned on and an off voltage, i.e., a high voltage (e.g., a power supply voltage) and a low voltage (e.g., a ground voltage) for controlling the first switch or the second switch to be turned off. Accordingly, the two input terminals of the check module 250 may be connected to the power terminal VDD and the ground terminal GND, respectively.
In some embodiments, as shown in fig. 8, the current compensation circuit 200 further includes:
the voltage follower 260 is connected between the check module 250 and the first terminal of the first transistor 221, and is used for controlling the first voltage V1 of the first terminal of the first transistor 221.
The voltage follower 260 can ensure that the output voltage closely follows the variation of the input voltage, and its working principle is based on the negative feedback of the operational amplifier, when the input voltage changes, the variation is sensed and amplified by the operational amplifier, and the output voltage of the amplifier is partially or completely fed back to its input terminal due to the negative feedback of the operational amplifier, and compared with the original input voltage. The comparison result is used as an adjusting signal to adjust the output of the amplifier so as to ensure that the output voltage always follows the change of the input voltage.
In some embodiments, as shown in FIG. 8, the voltage follower 260 includes an operational amplifier OPA, the negative phase input (-) of the operational amplifier OPA is connected to the output of the check module 250a, the positive phase input (+) of the operational amplifier OPA is connected to the drain of the first transistor 221, and the output of the operational amplifier OPA is connected to the gate of the first transistor 221. The output end of the operational amplifier OPA is connected with the positive phase input end (+) thereof to form negative feedback.
The voltage follower 260 can play a role in buffering, and can transmit an output signal of the front-stage circuit to the rear-stage circuit, and meanwhile, the voltage follower 260 also plays a role in isolating, so that the front-stage circuit is protected from being influenced by the rear-stage circuit, and the voltage follower 260 can drive a larger load, so that the load carrying capacity of the circuit is improved.
In some embodiments, as shown in FIG. 9, the specific structure of the voltage switching module 240 in the embodiment may include a plurality of first voltage dividing resistors R0-Rn connected in series between the power supply terminal VDD and the ground terminal GND, the voltage switching module 240 includes a plurality of output terminals, a connection node between adjacent first voltage dividing resistors R0-Rn is used as an output terminal, the plurality of output terminals are used to output a corresponding alternative voltage to the check module 250, where the alternative voltages in FIG. 9 include Vbias-0 to Vbias n, n are positive integers, and the check module 250 is connected to the plurality of output terminals of the voltage switching module 240 to select an alternative voltage (e.g. Vbias-x) as the second control signal T2, and 0.ltoreq.x.ltoreq.n.
It is understood that the first voltage dividing resistors Rx connected in series between the power supply terminal VDD and the ground terminal GND may be fixed, and the resistance value of each first voltage dividing resistor Rx may be the same or different, and the voltage division of each first voltage dividing resistor Rx is the ratio of the resistance value of the first voltage dividing resistor Rx to the total resistance value of all the first voltage dividing resistors connected in series multiplied by the power supply voltage. The output alternative voltage Vbias-x of each output terminal node is the sum of the divided voltages of all the first dividing resistors Rx connected in series between that node and ground GND. Accordingly, the output voltages of the nodes between the power supply terminal VDD and the ground terminal GND decrease in sequence.
The multiple inputs of the check module 250 may be connected to each output node, respectively, and output an alternative voltage Vbias-x by switching selection to the input of the voltage follower, or to the control terminal of the variable resistance unit Rb.
The voltage switching module 240 in fig. 9 may be used for the voltage switching module 240a in fig. 4, the voltage switching module 240a in fig. 5, and the voltage switching module 240b for providing the simulated second control signal T2.
In some embodiments, as shown in FIG. 10, the specific structure of the fuse module 210 according to the embodiment of the present application may include a first fuse array 211 and a voltage switching unit 212 connected to the first fuse array 211, wherein the first fuse array 211 is configured to output a plurality of third control signals T3< n:0> (n is a positive integer), wherein the third control signals may be digital signals;
The voltage switching unit 212 includes a plurality of second voltage dividing resistors Ry connected in series between the power supply terminal VDD and the ground terminal GND, wherein connection nodes of adjacent second voltage dividing resistors Ry are connected to the first ends of the corresponding third switches K3, the second ends of the third switches K3 serve as output ends of the first fuse arrays 211 for connecting corresponding check modules and outputting the first control signals T1, control ends of the third switches K3 are connected to the first fuse arrays 211 and receive corresponding third control signals, and the third control signals T3<0> -T3< n > are used for controlling on or off of the plurality of third switches K3, respectively.
It can be appreciated that the voltage switching unit 212 includes the second voltage dividing resistor Ry connected in series between the power supply terminal VDD and the ground terminal GND such that the output voltage of the node between every two adjacent second voltage dividing resistors Ry is different. A third switch K3 is connected to each output node, and one or more third switches K3 are selectively turned on to output a corresponding output voltage as the first control signal T1. The third control signals output by the fuse array 211 control the on-off states of the third switches K3, thereby realizing the function of editing the output voltage by the fuse array.
It should be noted that, in the embodiment of the present disclosure, the fuse module 210 may include a plurality of first fuse arrays 211 and voltage switching units 212. As shown in fig. 11, the fuse module 210 includes a first fuse array 211a and a voltage switching unit 212a connected thereto, and a first fuse array 211b and a voltage switching unit 212b connected thereto. The output terminal of the voltage switching unit 212a may be connected to the node for adjusting the first voltage V1 through a check module 250a, and the output terminal of the voltage switching unit 212b may be connected to the control terminal of the variable resistance unit Vb through a check module 250 b.
In addition, in an embodiment, as shown in fig. 11, the fuse module 210 may further include a second fuse array 213, and does not include a voltage switching unit. The second fuse array 213 may include a plurality of output terminals respectively connected to the control terminals of the first switches k11-k13 in fig. 7A or the second switches k21-k23 in fig. 7B, which are exemplified as parallel second switches.
It should be noted that, since the plurality of control switches (the first switch or the second switch) of the resistor array unit Ra are respectively switched on/off by the high/low level, the control signal T1 or T2 is a digital signal, and the resistor array unit Ra corresponds to the second fuse array 213, and does not include the voltage switching unit. At this time, the voltage switching module corresponding to the resistor array unit Ra may be a circuit for providing a plurality of digital signals, and is used for providing a plurality of control signals T2, where the voltage value of the control signal T2 may be 0V or the power supply voltage VDD.
Based on the same inventive concept, the embodiments of the present disclosure further provide a calibration method of a logarithmic detector for calibrating the logarithmic detector shown in fig. 2, which is described below with reference to fig. 2 and 12, the calibration method including the steps of:
Step S101, starting calibration, wherein because the processes of logarithmic detectors of different batches have deviation, when the same radio frequency signals are input into different logarithmic detectors, the output signals are different, and the calibration is needed;
Step S102, inputting a radio frequency signal to the logarithmic detector, specifically, inputting a known radio frequency signal to the radio frequency logarithmic amplifier 110 in FIG. 2, and outputting a fixed output signal which is a target output signal after the logarithmic detector receives the known radio frequency signal when the logarithmic detector has no process deviation;
step S103, all check modules select corresponding second control signals T2 as output, sequentially control different second control signals T2 output by each check module, sequentially detect output signals of the logarithmic detectors under the condition of different output values, and if the process of the logarithmic detectors has deviation, the output signals of the logarithmic detectors are not target output signals and need to be compensated, so that the output signals of the logarithmic detectors reach the target output signals. Specifically, during calibration, the check module selects the corresponding second control signals T2 as output, sequentially traverses the values of the second control signals T2, controls the gear of the compensation current I0 under the value of each second control signal T2, and detects whether the output signal of the logarithmic detector reaches the target output signal under the gear of different compensation currents I0.
Taking the current compensation circuit as an example shown in fig. 11 for illustration, the current compensation circuit includes three check modules with three-stage adjustment, and assuming that the check module 250a corresponds to A1 second control signals T2, the check module 250b corresponds to A2 second control signals T2, and the check module 250c corresponds to A3 second control signals T2, the whole current compensation circuit can realize the gear positions of a1×a2×a3 compensation currents I0, and in step S103, the output adjustment can be sequentially performed on the gear positions a1×a2×a3.
Step S104, determining the output value of the second control signal T2 selected by each check module according to the output signal of the logarithmic detector, wherein when the value of the second control signal T2 is the same as the target output signal under certain conditions, the compensation current I0 can compensate the process deviation at the moment;
In step S105, the output value (target control signal) of the second control signal selected by each check module is programmed into the fuse module, for example, the target second control signal of each check module is programmed into the corresponding fuse array, and each check module is controlled to receive the first control signal T1 provided by the fuse module. At this time, the connection end of each check module for receiving the second control signal may be cut off, or may be reserved.
Under the condition of normal operation after calibration, the check module selects and receives the first control signal T1 output by the fuse module, and the current compensation circuit can output proper compensation current through the first control signal T1, so that the intercept of the logarithmic detector logarithmic curve is compensated, and the influence caused by process deviation is eliminated.
The logarithmic detector of each of the foregoing embodiments may be used for detecting a radio frequency channel, as shown in fig. 13, and the disclosed embodiment further provides a chip 400, which includes at least one radio frequency channel 410, and a logarithmic detector 420 connected to the radio frequency channel 410 and configured to detect a radio frequency signal RF provided by the radio frequency channel 410. In general, the chip 400 further includes a radio frequency amplifier, a mixer, a filter, etc., which are not limited herein.
The logarithmic detector 300 and the chip 400 have the same inventive concept as the current compensation circuit 200, and the specific implementation thereof may refer to the description in any embodiment, and will not be repeated here.
It should be appreciated that reference throughout this specification to "some embodiments," "one embodiment," or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the size of the sequence number of each process does not mean that the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The embodiment numbers of the present disclosure are merely for the purpose of description and do not represent the advantages or disadvantages of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above is merely an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present disclosure, and should be covered in the protection scope of the present disclosure.
Claims (13)
1. A current compensation circuit, comprising:
a current mirror comprising a first transistor and a second transistor, the first transistor and the second transistor each comprising a first terminal, a second terminal, and a control terminal, the current mirror configured to mirror a first current flowing through the first terminal of the first transistor to the first terminal of the second transistor, the first terminal of the second transistor outputting a compensation current;
The resistor module is connected with the first end of the first transistor, and the resistance value of the resistor module and the first voltage of the first end of the first transistor are used for determining the magnitude of the first current;
And the fuse wire module is connected with the resistor module and/or the first end of the first transistor and is used for outputting a first control signal based on the fusing state, and the first control signal is used for calibrating the resistance value of the resistor module and/or the first voltage.
2. The current compensation circuit of claim 1, further comprising:
The output end of the one or more voltage switching modules is used for outputting a plurality of second control signals, and the second control signals are used for calibrating the resistance value of the resistance module and/or the first voltage;
The input end of the check module is connected with the output end of the corresponding voltage switching module and the output end of the fuse module, the output end of the check module is connected with the resistor module and/or the first end of the first transistor, and the check module is used for selecting one from the second control signal and the first control signal to output.
3. The current compensation circuit of claim 2, wherein the resistor module comprises:
A variable resistance unit, a resistance array unit, or a series/parallel variable resistance unit, and a resistance array unit;
The control end of the variable resistance unit receives the first control signal or the second control signal output by the corresponding check module so as to control the first resistance value of the variable resistance unit;
the resistor array unit comprises a plurality of resistor elements, and the resistor elements are used for changing the number of the resistor elements connected into a passage where the first current is located through the first control signal or the second control signal output by the corresponding check module so as to control the second resistance value of the resistor array unit.
4. The current compensation circuit of claim 3 wherein said variable resistance unit comprises a third transistor;
The control end of the third transistor receives the first control signal or the second control signal, and the first end and the second end of the third transistor are connected in series with the resistor array unit so as to adjust the first resistance value of the third transistor.
5. A current compensation circuit according to claim 3 wherein said resistive array element comprises:
A plurality of first resistive elements in series, and a plurality of first switches, the first and second ends of the first switches being connected in parallel with the first resistive elements;
The control end of the first switch receives the corresponding first control signal or the second control signal.
6. A current compensation circuit according to claim 3 wherein said resistive array element comprises:
a plurality of second resistive elements connected in parallel, and a plurality of second switches, the first and second ends of the second switches being connected in series with the second resistive elements;
The control end of the second switch receives the corresponding first control signal or the second control signal.
7. The current compensation circuit according to any one of claims 2 to 6, further comprising:
and the voltage follower is connected between the check module and the first end of the first transistor and is used for controlling the first voltage of the first end of the first transistor.
8. The current compensation circuit of claim 7 wherein said voltage follower comprises an operational amplifier, a negative input of said operational amplifier being connected to an output of said check module, a positive input of said operational amplifier being connected to a drain of said first transistor, an output of said operational amplifier being connected to a gate of said first transistor, or
The voltage follower comprises an operational amplifier and a fourth transistor, wherein the negative phase input end of the operational amplifier is connected with the output end of the check module, the positive phase input end of the operational amplifier is connected with the first end of the fourth transistor, the output end of the operational amplifier is connected with the control end of the fourth transistor, and the second end of the fourth transistor is connected with the drain electrode of the first transistor.
9. The current compensation circuit according to any one of claims 2 to 6, wherein the voltage switching module comprises a plurality of first voltage dividing resistors connected in series between a power supply terminal and a ground terminal, a node adjacent to the first voltage dividing resistor being an output terminal for outputting an alternative voltage to the check module;
the check module selects one of the alternative voltages as the second control signal.
10. The current compensation circuit according to any one of claims 1 to 6, wherein the fuse block includes:
A first fuse array for outputting a plurality of third control signals based on the blown state;
The voltage switching unit comprises a plurality of second voltage dividing resistors and a plurality of third switches, wherein the second voltage dividing resistors and the third switches are connected in series between a power end and a grounding end, nodes of the adjacent second voltage dividing resistors are connected with first ends of the corresponding third switches, second ends of the third switches are connected together to serve as output ends of the fuse modules and are used for outputting the first control signals, and control ends of the third switches are connected with the first fuse arrays and receive the corresponding third control signals.
11. A logarithmic detector, comprising:
The logarithmic amplifier is used for receiving the radio frequency signal and outputting a second current;
A current compensation circuit according to any one of claims 1 to 10;
And the operation unit is connected with the logarithmic amplifier and the current compensation circuit, receives the second current and the compensation current and outputs a third current.
12. The logarithmic detector of claim 11, further comprising:
the output unit is connected with the operation unit and receives the third current to be converted into output voltage;
The feedback unit is used for providing feedback current for the operation unit based on the output voltage;
the operation unit obtains the third current according to the first current and the second current, and outputs the third current to the output unit.
13. A chip, comprising:
at least one radio frequency channel;
A logarithmic detector as claimed in claim 11 or 12, connected to the radio frequency channel for detecting a radio frequency signal provided by the radio frequency channel.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510964798.XA CN120994008A (en) | 2025-02-11 | 2025-02-11 | Current compensation circuit, logarithmic detector and chip |
| CN202510151792.0A CN119620819B (en) | 2025-02-11 | 2025-02-11 | Current compensation circuit, logarithmic detector and chip |
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| CN202510151792.0A CN119620819B (en) | 2025-02-11 | 2025-02-11 | Current compensation circuit, logarithmic detector and chip |
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| CN119990161A (en) * | 2025-04-10 | 2025-05-13 | 上海安其威微电子科技有限公司 | Square circuit, square circuit control method and control module |
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| CN119620819B (en) | 2025-08-01 |
| CN120994008A (en) | 2025-11-21 |
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