CN119603956A - Memory cell structure and memory device - Google Patents

Abstract

The invention relates to a memory cell structure and a memory device, and relates to the technical field of semiconductors, wherein the memory cell structure is arranged between a second end part of a second sub-grid and a second active area at intervals, when a first shared contact structure is arranged, the length of the first shared contact structure can be increased, so that the contact resistance of the first shared contact structure is reduced, the tolerance of the position deviation of the first shared contact structure is increased, and the performance of the memory cell is further improved. In addition, the second sub-grid is obliquely arranged at the staggered vacancy part of the first active area and the second active area, so that the area of the memory cell is not increased, and the miniaturization of the memory cell structure is facilitated.

Description

Memory cell structure and memory device

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to a memory cell structure and a memory device.

Background

Memory devices are a critical part of computer systems for storing data. Memory devices include Dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), and the like.

The conventional static random access memory device comprises a plurality of memory cell structures, and is indispensable to layout design of the memory cells in order to improve the memory speed and power consumption of the memory cells. However, in the conventional layout design, to improve the performance of the memory cell, the area of the memory cell is increased.

Based on this, how to improve the performance of the memory cell without increasing the structural area of the memory cell is a technical problem that needs to be solved by those skilled in the art.

Disclosure of Invention

Based on this, it is necessary to provide a memory cell structure and a memory device with respect to how to improve the performance of the memory cell without increasing the area of the memory cell structure.

In order to achieve the above object, in one aspect, the present invention provides a memory cell structure, comprising:

The semiconductor device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a first active area and a second active area which are sequentially arranged in a first direction; the first active area and the second active area are overlapped on a orthographic projection part of a projection line parallel to a second direction in the first direction, the first direction and the second direction are parallel to a plane of the substrate, and the first direction is perpendicular to the second direction;

The first grid electrode and the second grid electrode are positioned on one side of the substrate and are arranged along the second direction;

The first grid comprises a first sub-grid and a second sub-grid which are mutually connected in the first direction, the first sub-grid extends in the first direction and penetrates through the first active area along the first direction, the second sub-grid comprises a first end portion and a second end portion, the first end portion is connected with the first sub-grid, orthographic projection of the first end portion on the projection line overlaps with orthographic projection of the second active area on the projection line, orthographic projection of the second end portion on the projection line and orthographic projection of the second active area on the projection line are arranged at intervals, the second grid penetrates through the second active area along the first direction, a first shared contact structure extends along the second direction, and the first shared contact structure is connected with the second end portion and the second active area between the second sub-grid and the second grid.

In one embodiment, in the second direction, the second end portion and the second active region have a first distance, and a first side wall is arranged on one side of the second sub-gate close to the second active region;

And in the second direction, the length of the first interval is greater than or equal to the width of the first side wall.

In one embodiment, the second active region between the second gate and the second end is provided with a first heavily doped region extending in the second direction to an end of the second active region.

In one embodiment, the memory cell structure further includes:

A third active region located on a side of the second active region away from the first active region, an orthographic projection of the third active region on the projection line covering at least an orthographic projection of the first active region on the projection line and an orthographic projection of the second active region on the projection line;

the second gate extends in the first direction and traverses the third active region.

In one embodiment, the memory cell structure further includes:

And the third grid electrode penetrates through the third active region, and the orthographic projection of the third grid electrode on the projection line is overlapped with the orthographic projection of the first sub-grid electrode on the projection line.

In one embodiment, the second grid electrode comprises a third sub grid electrode and a fourth sub grid electrode which are mutually connected in the first direction, the third sub grid electrode extends in the first direction and passes through the second active area along the first direction, the fourth sub grid electrode comprises a third end part and a fourth end part, the third end part is connected with the third sub grid electrode, the orthographic projection of the third end part on the projection line overlaps with the orthographic projection part of the first active area on the projection line, and the orthographic projection of the fourth end part on the projection line is arranged at intervals with the orthographic projection of the first active area on the projection line;

a second shared contact structure extends along the second direction, the second shared contact structure connecting the fourth end and connecting the first active region between the fourth sub-gate and the first sub-gate.

In one embodiment, in the second direction, the fourth sub-gate and the first active region have a second distance, a second side wall is disposed at one side of the fourth end portion, which is close to the first active region, and in the second direction, a length of the second distance is greater than or equal to a width of the second side wall.

In one embodiment, the first active region between the fourth sub-gate and the fourth end is provided with a second heavily doped region extending in the second direction to an end of the first active region.

In one embodiment, the memory cell structure further includes:

A fourth active region located on a side of the first active region away from the second active region, an orthographic projection of the fourth active region on the projection line covering at least an orthographic projection of the first active region on the projection line and an orthographic projection of the second active region on the projection line;

The first gate extends in the first direction and passes through the fourth active region;

and the fourth grid electrode penetrates through the fourth active region, and the orthographic projection of the fourth grid electrode on the projection line is overlapped with the orthographic projection of the third sub-grid electrode on the projection line.

In another aspect, the present application further provides a memory device including at least one memory cell structure as described in any one of the above.

Compared with the prior art, the technical scheme has the following advantages:

The memory cell structure comprises a substrate, wherein the substrate comprises a first active area and a second active area, the first active area and the second active area are arranged in a staggered mode in a first direction, and a first grid electrode and a second grid electrode are arranged on one side of the substrate and along a second direction. The first grid electrode comprises a first sub-grid electrode and a second sub-grid electrode which are mutually connected in a first direction, the first sub-grid electrode penetrates through the first active area along the first direction, the second sub-grid electrode comprises a first end part and a second end part, and the first end part is connected with the first sub-grid electrode.

Since the orthographic projection of the first end portion on the projection line overlaps with the orthographic projection portion of the second active region on the projection line, the orthographic projection of the second end portion on the projection line is spaced apart from the orthographic projection of the second active region on the projection line, so that the second sub-gate can be obliquely disposed to the staggered void portions of the first active region and the second active region. The first shared contact structure extends along the second direction, is connected with the second end part and is connected with the second active region between the second sub-grid and the second grid.

In the application, as the second end part of the second sub-grid electrode and the second active region are arranged at intervals, the length of the first shared contact structure can be increased when the first shared contact structure is arranged, which not only reduces the contact resistance of the first shared contact structure, but also increases the tolerance of the position deviation of the first shared contact structure, and further improves the performance of the memory cell. In addition, the second sub-grid is obliquely arranged at the staggered vacancy part of the first active area and the second active area, so that the area of the memory cell is not increased, and the miniaturization of the memory cell structure is facilitated.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present application, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a schematic diagram of a portion of a memory cell structure according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a portion of a conventional memory cell structure;

FIG. 3 is a schematic diagram of another portion of a memory cell structure according to an embodiment of the present application;

FIG. 4 is a schematic cross-sectional view of FIG. 3 along ZZ';

FIG. 5 is another cross-sectional schematic view of FIG. 3 along ZZ';

FIG. 6 is a schematic diagram of a memory cell structure according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a memory cell structure according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a memory cell structure according to an embodiment of the present application;

FIG. 9 is a schematic cross-sectional view of FIG. 8 along DD';

FIG. 10 is another cross-sectional schematic view of FIG. 8 along DD';

FIG. 11 is a schematic diagram of a memory cell structure according to an embodiment of the present application;

FIG. 12 is a schematic diagram of a memory cell structure according to an embodiment of the present application;

fig. 13-21 are schematic structural diagrams of a further portion of a memory cell structure according to an embodiment of the present application;

fig. 22 is another cross-sectional schematic view of fig. 12 along EE'.

The reference numerals indicate 01-substrate, 02-first active region, 03-second active region, 04-first gate, 04 a-first sub-gate, 04B-second sub-gate, 05-second gate, 05 a-third sub-gate, 05B-fourth sub-gate, A-first end, B-second end, C-third end, D-fourth end, 06-first shared contact structure, 07-first sidewall, 08-first heavily doped region, 09-third active region, 10-third gate, 11-second shared contact structure, 12-second sidewall, 13-second heavily doped region, 14-fourth active region, 15-fourth gate, 16-independent contact structure, 17-isolation structure, 18-gate oxide layer, 19-offset sidewall structure, 20-lightly doped region, 21-sidewall structure, 22-metal silicide layer, 23-etching stop layer, 24-interlayer dielectric layer, 25 a-independent metal contact hole, 25B-first shared contact hole.

Detailed Description

In order that the application may be readily understood, a more complete description of the application will be rendered by reference to the appended drawings. Embodiments of the application are illustrated in the accompanying drawings. This application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when a layer is referred to as being "on," "adjacent to," "connected to" another layer, it can be directly on, adjacent to, or connected to the other layer, or intervening layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," or "directly connected to" another layer, there are no intervening layers present.

As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

In order that the manner in which the above recited objects, features and advantages of the present application are obtained will become more readily apparent, a more particular description of the application briefly described above will be rendered by reference to the appended drawings.

Referring to fig. 1, fig. 1 is a schematic diagram of a portion of a memory cell structure according to an embodiment of the present application, where the memory cell structure includes:

The substrate 01 comprises a first active region 02 and a second active region 03 which are sequentially arranged in a first direction X, the first active region 02 and a orthographic projection part of the second active region 03 on a projection line Q parallel to a second direction Y are overlapped in the first direction X, the first direction X and the second direction Y are parallel to a plane of the substrate 01, and the first direction X is perpendicular to the second direction Y.

A first gate 04 and a second gate 05 located on one side of the substrate 01 and arranged along the second direction Y.

The first grid electrode 04 comprises a first sub-grid electrode 04a and a second sub-grid electrode 04B which are mutually connected in a first direction X, the first sub-grid electrode 04a extends in the first direction X and penetrates through the first active area 02 along the first direction X, the second sub-grid electrode 04B comprises a first end part A and a second end part B, the first end part A is connected with the first sub-grid electrode 04a, the orthographic projection of the first end part A on a projection line Q is overlapped with the orthographic projection part of the second active area 03 on the projection line Q, the orthographic projection of the second end part B on the projection line Q is arranged at intervals with the orthographic projection of the second active area 03 on the projection line Q, the second grid electrode 05 penetrates through the second active area 03 along the first direction X, the first shared contact structure 06 extends along the second direction Y, and the first shared contact structure 06 is connected with the second end part B and is connected with the second active area 03 between the second sub-grid electrode 04B and the second active area 05.

Specifically, in the present embodiment, the first active region 02 and the second active region 03, which are sequentially arranged in the first direction X, extend in the second direction Y. Wherein the orthographic projection of the first active region 02 and the second active region 03 on a projection line Q parallel to the second direction Y partially overlaps, that is, the first active region 02 and the second active region 03 are staggered.

On the side of the substrate 01 where the first active region 02 and the second active region 03 are disposed, a first gate 04 and a second gate 05 are further disposed, and in this embodiment, the first gate 04 includes a first sub-gate 04a and a second sub-gate 04b, and the first sub-gate 04a extends in the first direction X and passes through the first active region 02, that is, a first transistor is formed at the first active region 02 and the first sub-gate 04 a.

The second sub-gate 04B includes a first end portion a connected to the first sub-gate 04a and a second end portion B extending outward. The first end portion a overlaps with the orthographic projection of the first sub-gate 04a on the projection line Q, and the first end portion a overlaps with the orthographic projection of the second active region 03 on the projection line Q, while the second end portion B is spaced from the orthographic projection of the first end portion a on the projection line Q. That is, the second end B is not on the same horizontal line as the first end a, so that the second sub-gate 04B structure has a space between the second active region 03 in the second direction Y. The first sub-gate 04a and the second sub-gate 04b are integrated, and the structure is only described here for better illustration. In addition, the second gate electrode 05 crosses the second active region 03 in the first direction X, and a second transistor is formed on the second active region 03.

A first shared contact structure 06 is further provided on the upper side of the second active region 03 and the second end B, wherein the first shared contact structure 06 extends along the second direction Y and connects the second end B with the second active region 03 between the second transistor and the second end B, that is to say, with the second transistor and the first transistor.

Referring to fig. 2, fig. 2 is a schematic diagram of a portion of a conventional memory cell structure, where the front projection of the conventional first gate 04 on the projection line Q partially overlaps the front projection of the second active region 03 on the projection line Q. Since the first shared contact structure 06 is located in the overlapping area, the contact resistance of the first shared contact structure 06 is larger, and the tolerance of the offset of the first shared contact structure 06 is lower.

In the present application of fig. 1, in the second direction Y, the interval between the second end B of the second sub-gate 04B and the second active region 03 may increase the length of the first shared contact structure 06, which not only reduces the contact resistance of the first shared contact structure 06, but also increases the tolerance of the position offset of the first shared contact structure 06, and further improves the performance of the memory cell.

Because the second active region 03 and the first active region 02 are arranged in a staggered manner, in the memory cell structure, a part of the first active region 02, which is not overlapped with the second active region 03 on the projection line Q, is vacant, and the second sub-grid 04b is obliquely arranged in the vacant region, so that the contact resistance of the first shared contact structure 06 is reduced, the tolerance of the position deviation of the first shared contact structure 06 is increased, the area of the memory cell structure is not increased, and the miniaturization of the memory cell structure is facilitated.

Optionally, in another embodiment of the present application, referring to fig. 3, fig. 3 is a schematic structural diagram of another portion of a memory cell structure provided in the embodiment of the present application, referring to fig. 4, fig. 4 is a schematic structural diagram of a cross section along ZZ' of fig. 3, in the second direction Y, the second end B has a first distance H from the second active area 03, and a side of the second sub-gate 04B close to the second active area 03 is provided with a first sidewall 07.

In the second direction Y, the length of the first pitch H is greater than or equal to the width of the first side wall 07.

Specifically, in the second direction Y, a first space H is provided between the second end B of the second sub-gate 04B and the second active region 03, and a shallow trench isolation structure is disposed in the substrate 01 of the first space H, where the shallow trench isolation structure isolates the second active region 03 from the second sub-gate 04B. It should be noted that, a first sidewall 07 is further disposed on a side of the second sub-gate 04b near the second active region 03, and an orthographic projection of the first sidewall 07 on the substrate 01 does not overlap with the second active region 03, and it should be noted that, in fig. 3, the first sidewall 07 is not shown for clarity.

In the conventional structure, since the second sub-gate 04b overlaps the orthographic projection portion of the second active region 03 on the projection line Q, the second sub-gate 04b may cover a portion of the second active region 03, and at this time, the side of the second sub-gate 04b close to the second gate 05 has the first sidewall 07, and when the first shared contact structure 06 is formed, the first sidewall 07 of the second sub-gate 04b may be etched very easily, so that the formed first shared contact structure 06 is connected with the lightly doped region under the first sidewall 07, thereby generating a leakage current.

In the present application of fig. 4, a first space H is provided between the second end B of the second sub-gate 04B and the second active region 03, and the width of the first sidewall 07 of the second sub-gate 04B is set to be less than or equal to the first space H, at this time, even if a portion of the first sidewall 07 is etched, since the lower side of the first sidewall 07 is a shallow trench isolation structure, leakage current is avoided.

Alternatively, in another embodiment of the present application, referring to fig. 5, fig. 5 is another schematic cross-sectional structure along ZZ' of fig. 3, and the second active region 03 between the second gate 05 and the second end B is provided with a first heavily doped region 08, and the first heavily doped region 08 extends to the end of the second active region 03 in the second direction Y.

Specifically, in the present embodiment, the second active region 03 between the second gate 05 and the second end B is provided with a first heavily doped region 08, and the first heavily doped region 08 is a P-type heavily doped region, that is, the second transistor is a PMOS transistor. In order to avoid the generation of leakage current caused by the contact of the first shared contact structure 06 with the lightly doped region, the P-type heavily doped region extends to the end of the second active region 03 in the second direction Y, and at this time, the formed first shared contact structure 06 only forms ohmic contact with the P-type heavily doped region, so that no leakage current is generated.

Optionally, in another embodiment of the present application, referring to fig. 6, fig. 6 is a schematic structural diagram of a further portion of a memory cell structure provided in an embodiment of the present application, where the memory cell structure further includes:

The third active region 09, the third active region 09 is located at a side of the second active region 03 remote from the first active region 02, and the orthographic projection of the third active region 09 on the projection line Q covers at least the orthographic projection of the first active region 02 on the projection line Q and the orthographic projection of the second active region 03 on the projection line Q.

The second gate 05 extends in the first direction X and crosses the third active region 09.

Specifically, in the first direction X, the third active region 09 is located on a side of the second active region 03 away from the first active region 02, the third active region 09 extends in the second direction Y, and the length of the third active region 09 in the second direction Y is greater than that of the first active region 02 or the second active region 03, and the orthographic projection on the projection line Q covers at least the orthographic projection of the first active region 02 on the projection line Q and the orthographic projection of the second active region 03 on the projection line Q.

The second gate 05 extends in the first direction X and crosses the third active region 09, that is, a third transistor is further formed where the second gate 05 overlaps the third active region 09, and the gate of the third transistor is the same gate as the gate of the second transistor. The third transistor is an N-type transistor.

Optionally, in another embodiment of the present application, as shown in fig. 6, the memory cell structure further includes:

The third gate 10, the third gate 10 crosses the third active region 09, and the orthographic projection of the third gate 10 on the projection line Q overlaps with the orthographic projection of the first sub-gate 04a on the projection line Q.

Specifically, the third gate 10 passes through the third active region 09, a fourth transistor is formed at the overlapping position of the third gate 10 and the third active region 09, the fourth transistor and the third transistor are of the same type and are all N-type transistors, at this time, on the third active region 09, the two sides of the second gate 05 and the third gate 10 are respectively provided with a side wall and a source or a drain, which are not shown in the figure, wherein the source or the drain between the third transistor and the fourth transistor can be shared.

The fact that the orthographic projection of the third gate 10 on the projection line Q overlaps the orthographic projection of the first sub-gate 04a on the projection line Q means that the third gate 10 and the second end B of the second sub-gate 04B are staggered in the first direction X, that is, the central axis of the third gate 10 in the first direction X is spaced from the central axis of the second end B in the first direction X, may reduce the possibility of accidental connection between the first gate 04 and the third gate 10.

In the existing preparation process, the shape of the actually formed grid is not ideal rectangle, and particularly, the tail end of the grid can be obviously deformed. In the present application, the length of the third gate 10 near the side of the second active region 03 is increased compared with the conventional width L in fig. 6, which is advantageous to make the morphology of the third gate 10 in the overlapping region with the third active region 09 more uniform, and further to stabilize the electrical performance of the fourth transistor.

Optionally, in another embodiment of the present application, referring to fig. 7, fig. 7 is a schematic structural diagram of a further portion of a memory cell structure provided in the embodiment of the present application, where the second gate 05 includes a third sub-gate 05a and a fourth sub-gate 05b connected to each other in the first direction X, the third sub-gate 05a extends in the first direction X and passes through the second active region 03 along the first direction X, the fourth sub-gate 05b includes a third end portion C and a fourth end portion D, the third end portion C is connected to the third sub-gate 05a, a front projection of the third end portion C on the projection line Q overlaps a front projection of the first active region 02 on the projection line Q, and a front projection of the fourth end portion D on the projection line Q is spaced from a front projection of the first active region 02 on the projection line Q.

The second shared contact structure 11 extends along the second direction Y, and the second shared contact structure 11 is connected to the fourth end D and to the first active region 02 between the fourth sub-gate 05b and the first sub-gate 04 a.

Specifically, in this embodiment, the second gate electrode 05 may further include a third sub-gate electrode 05a and a fourth sub-gate electrode 05b, where the third sub-gate electrode 05a extends in the first direction X and passes through the second active region 03, that is, the second transistor is formed.

Further, the fourth sub-gate 05b includes a third end portion C connected to the third sub-gate 05a and a fourth end portion D extending outward. The third end portion C overlaps with the orthographic projection of the third sub-gate 05a on the projection line Q, and the third end portion C overlaps with the orthographic projection of the first active region 02 on the projection line Q, and the fourth end portion D has a space from the orthographic projection of the third end portion C on the projection line Q. That is, the fourth end D and the third end C are not positioned on the same horizontal line, so that the fourth sub-gate 05b structure has a space from the first active region 02 in the second direction Y. The third sub-gate 05a and the fourth sub-gate 05b are integrated, and the structure thereof is described only for better explanation.

A second shared contact structure 11 is further disposed on the upper side of the first active region 02 and the fourth end D, wherein the second shared contact structure 11 extends along the second direction Y and connects the first active region 02 between the fourth end D and the first and fourth transistors, that is, the first and second transistors.

The provision of the space between the fourth end portion D of the fourth sub-gate 05b and the first active region 02 in the second direction Y may increase the length of the second shared contact structure 11, which not only reduces the contact resistance of the second shared contact structure 11, but also increases the tolerance of the positional deviation of the second shared contact structure 11, further improving the performance of the memory cell.

In addition, the fourth sub-gate 05b is disposed in the empty region of the portion of the first active region 02, which does not overlap the second active region 03 on the projection line Q, so that the contact resistance of the second shared contact structure 11 is reduced, the tolerance of the position offset of the second shared contact structure 11 is increased, and the area of the memory cell structure is not increased. And the miniaturization of the memory cell structure is facilitated.

The second sub-gate 04b and the fourth sub-gate 05b are designed in this way, so that the performance of the memory cell structure can be improved to a greater extent.

Optionally, in another embodiment of the present application, referring to fig. 8, fig. 8 is a schematic structural diagram of a further portion of a memory cell structure provided in the embodiment of the present application, referring to fig. 9, fig. 9 is a schematic structural diagram of a cross section of fig. 8 along DD', in which in the second direction Y, the fourth end D and the first active region 02 have a second distance h, and a side of the fourth sub-gate 05b adjacent to the first active region 02 is provided with a second sidewall 12, and in the second direction Y, a length of the second distance h is greater than or equal to a width of the second sidewall 12.

Specifically, in the second direction Y, a second distance h is provided between the fourth end D of the fourth sub-gate 05b and the first active region 02, and the second distance h is provided with a shallow trench isolation structure, where the shallow trench isolation structure isolates the first active region 02 from the fourth sub-gate 05 b. It should be noted that, a second sidewall 12 is further disposed on a side of the fourth sub-gate 05b near the first active region 02, and a lower side of the second sidewall 12 does not overlap the first active region 02.

In the conventional structure, since the fourth sub-gate 05b overlaps the orthographic projection portion of the first active region 02 on the projection line Q, the fourth sub-gate 05b covers a portion of the first active region 02, and at this time, the second side wall 12 is disposed on the side of the fourth sub-gate 05b close to the first gate 04, and when the second shared contact structure 11 is formed, the second side wall 12 of the fourth sub-gate 05b is very easy to be etched through during etching, so that the formed second shared contact structure 11 is connected with the lightly doped region below the second side wall 12, thereby generating a leakage current.

In the present application of fig. 9, a second space h is provided between the fourth end D of the fourth sub-gate 05b and the first active region 02, and the width of the second sidewall 12 of the fourth sub-gate 05b is set to be smaller than or equal to the second space h, so that even if a portion of the second sidewall 12 is etched away, the occurrence of leakage current is avoided because the lower side of the second sidewall 12 is a shallow trench isolation structure.

Alternatively, in another embodiment of the present application, referring to fig. 10, fig. 10 is another schematic cross-sectional structure along DD' of fig. 8. The first active region 02 between the fourth sub-gate 05b and the fourth end D is provided with a second heavily doped region 13, the second heavily doped region 13 extending to the end of the first active region 02 in the second direction Y.

Specifically, in the present embodiment, the first active region 02 between the first gate 04 and the fourth terminal D is provided with a second heavily doped region 13, and the second heavily doped region 13 is a P-type heavily doped region, that is, the first transistor is a PMOS transistor. In order to avoid the generation of leakage current caused by the contact of the second shared contact structure 11 with the lightly doped region, the P-type heavily doped region extends to the end of the first active region 02 in the second direction Y, and at this time, the second shared contact structure 11 only forms ohmic contact with the P-type heavily doped region, so that no leakage current is generated.

Optionally, in another embodiment of the present application, referring to fig. 11, fig. 11 is a schematic structural diagram of a further portion of a memory cell structure provided in an embodiment of the present application, where the memory cell structure further includes:

The fourth active region 14, the fourth active region 14 being located on the side of the first active region 02 remote from the second active region 03, the orthographic projection of the fourth active region 14 on the projection line Q covering at least the orthographic projection of the first active region 02 on the projection line Q and the orthographic projection of the second active region 03 on the projection line Q.

The first gate 04 extends in the first direction X and crosses the fourth active region 14.

The fourth gate 15, the fourth gate 15 crosses the fourth active region 14, and the orthographic projection of the fourth gate 15 on the projection line Q overlaps with the orthographic projection of the third sub-gate 05a on the projection line Q.

Specifically, in the first direction X, the fourth active region 14 is located on a side of the first active region 02 away from the second active region 03, the fourth active region 14 extends in the second direction Y, and the length of the fourth active region 14 in the second direction Y is greater than that of the first active region 02 or the second active region 03, and the orthographic projection on the projection line Q covers at least the orthographic projection of the first active region 02 on the projection line Q and the orthographic projection of the second active region 03 on the projection line Q. Note that, the orthographic projections of the fourth active region 14 and the third active region 09 on the projection line Q may overlap.

The first gate 04 extends in the first direction X and crosses the fourth active region 14, that is, a fifth transistor is further formed where the first gate 04 overlaps the fourth active region 14, and the gate of the fifth transistor is the same as the gate of the first transistor. The fifth transistor is an N-type transistor.

In addition, the fourth gate 15 passes through the fourth active region 14, and a sixth transistor is formed at the overlapping portion of the fourth gate 15 and the fourth active region 14, and the sixth transistor and the fifth transistor are both N-type transistors, and in this case, on the fourth active region 14, the first gate 04 and the two sides of the fourth gate 15 are respectively provided with a sidewall and a source or a drain, which are not shown in the figure, where the source or the drain between the fifth transistor and the sixth transistor may be shared.

The front projection of the fourth gate electrode 15 on the projection line Q overlaps with the front projection of the third sub-gate electrode 05a on the projection line Q, which means that the second end portions B of the fourth gate electrode 15 and the fourth sub-gate electrode 05B are staggered in the first direction X, that is, the central axis of the fourth gate electrode 15 in the first direction X is spaced from the central axis of the fourth end portion D in the first direction X, so that the possibility of accidental connection between the first gate electrode 04 and the fourth gate electrode 15 can be reduced.

In the present application, also because the possibility of accidental connection is reduced, the length of the fourth gate 15 near the side of the second active region 03 may be increased, for example, the length m of the fourth gate 15 in fig. 11 may be increased, which is beneficial to making the morphology of the fourth gate 15 in the overlapping region with the fourth active region 14 more uniform, and further is beneficial to stabilizing the electrical performance of the sixth transistor.

In this embodiment, the first transistor is a first PU transistor, the second transistor is a second PU transistor, the third transistor is a first PD transistor, the fourth transistor is a first PG transistor, the fifth transistor is a second PD transistor, and the sixth transistor is a second PG transistor. In forming these transistors, referring to fig. 12, fig. 12 is a schematic diagram of another part of a memory cell structure according to an embodiment of the present application, and further includes forming side walls (not shown) on two sides of the gate, and forming separate contact structures 16 on the source and the drain of each transistor, wherein the other separate contact structures 16 are the same as the existing structures, and are not specifically limited herein.

In an embodiment of the present application, referring to fig. 13 to 21, fig. 13 to 21 are schematic views of a further part of a memory cell structure according to an embodiment of the present application, and for clarity of description of a forming process, the present application also provides a method for manufacturing a memory cell structure, and an example is illustrated by a DD' section in fig. 12.

As shown in fig. 13, a substrate 01 is provided, an isolation structure 17 and a first active region 02 are formed in the substrate 01, a first sub-gate 04a is formed on the upper side of the first active region 02, a fourth sub-gate 05b is formed on the upper side of the isolation structure 17, and a gate oxide layer 18 is provided between the first sub-gate 04a and the fourth sub-gate 05b and the substrate 01.

As shown in fig. 14, offset sidewall structures 19 are formed on both sides of the first sub-gate 04a and the fourth sub-gate 05b, respectively.

As shown in fig. 15, LDD lightly doped regions 20 are formed in the first active regions 02 on both sides of the first sub-gate 04 a.

As shown in fig. 16, a sidewall structure 21 is formed on two sides of the first sub-gate 04a and the fourth sub-gate 05b, wherein a sidewall of the fourth sub-gate 05b near the first sub-gate 04a is the first sidewall 07.

As shown in fig. 17, the sidewall structure 21 is used as an implantation barrier layer, and P-type heavy doping is performed in the first active region 02 at two sides of the first sub-gate 04a to form a second heavy doped region 13, where the second heavy doped region 13 is the source or the drain of the first transistor. Note that, the side near the fourth sub-gate 05b may be a drain to connect to the second transistor.

As shown in fig. 18, a metal silicide layer 22 is formed on the first sub-gate 04a, the fourth sub-gate 05b, the source electrode and the drain electrode for enhancing the electrical contact performance S106.

As shown in fig. 19, an etching stop layer 23 and an interlayer dielectric layer 24 are sequentially deposited on one side of the metal silicide layer 22 and the side wall structure 21, and the surface is planarized.

And S108, as shown in FIG. 20, etching the interlayer dielectric layer 24 and the etching stop layer 23 in an etching mode to form a metal contact hole, wherein the metal contact hole of the source region of the first sub-gate 04a is an independent metal contact hole 25a, and the metal contact hole between the fourth sub-gate 05b structure and the first sub-gate 04a is a first shared contact hole 25b.

As shown in fig. 21, the metal contact hole is filled with a metal material to form a contact structure, for example, the second shared contact structure 11 in the first shared contact hole 25b and the individual contact structure 16 in the individual metal contact hole 25 a.

It should be noted that, the other transistors are formed in the same manner as described above, and referring to fig. 22, fig. 22 is another schematic cross-sectional structure along EE' of fig. 12, and the contact structures are the independent contact structures 16, which are described herein as examples and will not be described again.

In SRAM memory devices, the area of the memory cell structure is an important parameter, which is directly related to the storage density per unit area. Because the gate length, the side wall width and the distance from the contact electrode to the side wall of the PG transistor and the PD transistor determine the width of the memory cell, the extended sub-gate is arranged at the original vacant position, and the area of the SRAM memory cell is not increased, namely the width and the length of the memory cell are the same as those of the conventional SRAM cell. That is, the performance of the memory cell is further improved without changing the area of the memory cell.

Based on the above memory cell structure, the present application also provides a memory device, where the memory device includes at least one memory cell, and it should be noted that, since the memory device is composed of a plurality of memory cell structures, the memory device also has the effect achieved by the memory cell structures. And thus will not be described in detail herein.

In the description of the present specification, reference to the term "some embodiments," "another embodiment," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples illustrate only a few embodiments of the application, which are described in detail and are not to be construed as limiting the scope of the claims. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.

Claims (10)

1. A memory cell structure comprising:

The semiconductor device comprises a substrate, a first electrode and a second electrode, wherein the substrate comprises a first active area and a second active area which are sequentially arranged in a first direction; the first active area and the second active area are overlapped on a orthographic projection part of a projection line parallel to a second direction in the first direction, the first direction and the second direction are parallel to a plane of the substrate, and the first direction is perpendicular to the second direction;

The first grid electrode and the second grid electrode are positioned on one side of the substrate and are arranged along the second direction;

The first grid comprises a first sub-grid and a second sub-grid which are mutually connected in the first direction, the first sub-grid extends in the first direction and penetrates through the first active area along the first direction, the second sub-grid comprises a first end portion and a second end portion, the first end portion is connected with the first sub-grid, orthographic projection of the first end portion on the projection line overlaps with orthographic projection of the second active area on the projection line, orthographic projection of the second end portion on the projection line and orthographic projection of the second active area on the projection line are arranged at intervals, the second grid penetrates through the second active area along the first direction, a first shared contact structure extends along the second direction, and the first shared contact structure is connected with the second end portion and the second active area between the second sub-grid and the second grid.

2. The memory cell structure of claim 1, wherein in the second direction, the second end portion has a first distance from the second active region, and a first sidewall is disposed on a side of the second sub-gate adjacent to the second active region;

And in the second direction, the length of the first interval is greater than or equal to the width of the first side wall.

3. The memory cell structure of claim 1, wherein the second active region between the second gate and the second end is provided with a first heavily doped region extending in the second direction to an end of the second active region.

4. The memory cell structure of claim 1, the memory cell structure is characterized by further comprising:

A third active region located on a side of the second active region away from the first active region, an orthographic projection of the third active region on the projection line covering at least an orthographic projection of the first active region on the projection line and an orthographic projection of the second active region on the projection line;

the second gate extends in the first direction and traverses the third active region.

5. The memory cell structure of claim 4, the memory cell structure is characterized by further comprising:

And the third grid electrode penetrates through the third active region, and the orthographic projection of the third grid electrode on the projection line is overlapped with the orthographic projection of the first sub-grid electrode on the projection line.

6. The memory cell structure of claim 1, wherein the second gate includes a third sub-gate and a fourth sub-gate interconnected in the first direction, the third sub-gate extending in the first direction and traversing the second active region in the first direction, the fourth sub-gate including a third end portion and a fourth end portion, the third end portion connecting the third sub-gate, an orthographic projection of the third end portion on the projection line overlapping an orthographic projection of the first active region on the projection line, the orthographic projection of the fourth end portion on the projection line being spaced from an orthographic projection of the first active region on the projection line;

a second shared contact structure extends along the second direction, the second shared contact structure connecting the fourth end and connecting the first active region between the fourth sub-gate and the first sub-gate.

7. The memory cell structure of claim 6, wherein in the second direction, the fourth sub-gate has a second spacing from the first active region, a second sidewall is disposed on a side of the fourth end portion adjacent to the first active region, and in the second direction, a length of the second spacing is greater than or equal to a width of the second sidewall.

8. The memory cell structure of claim 6, wherein the first active region between the fourth sub-gate and the fourth end is provided with a second heavily doped region extending in the second direction to an end of the first active region.

9. The memory cell structure of claim 8, the memory cell structure is characterized by further comprising:

A fourth active region located on a side of the first active region away from the second active region, an orthographic projection of the fourth active region on the projection line covering at least an orthographic projection of the first active region on the projection line and an orthographic projection of the second active region on the projection line;

The first gate extends in the first direction and passes through the fourth active region;

and the fourth grid electrode penetrates through the fourth active region, and the orthographic projection of the fourth grid electrode on the projection line is overlapped with the orthographic projection of the third sub-grid electrode on the projection line.

10. A memory device comprising at least one memory cell structure according to any one of claims 1-9.