CN119601476A - Thermal compression bonding and reflow soldering packaging method, flip-chip bonding structure and chip structure - Google Patents
Thermal compression bonding and reflow soldering packaging method, flip-chip bonding structure and chip structure Download PDFInfo
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- CN119601476A CN119601476A CN202411705199.8A CN202411705199A CN119601476A CN 119601476 A CN119601476 A CN 119601476A CN 202411705199 A CN202411705199 A CN 202411705199A CN 119601476 A CN119601476 A CN 119601476A
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Abstract
The application discloses a packaging method for thermocompression bonding and reflow soldering, a flip-chip bonding structure and a chip structure, and relates to the technical field of chips. The method comprises the steps of preparing a plurality of welding spots on one side of a substrate to obtain a first welding plate, preparing a plurality of gold bumps on one side of a chip to obtain a second welding plate, and welding one side of the first welding plate with solder to one side of the second welding plate with gold bumps to obtain a packaged chip, wherein the welding pressure is 20-25 g/gold bumps. The side of the first welding plate with the solder and the side of the second welding plate with the gold salient point are directly welded, so that the step of flattening the gold salient point in the traditional flip-chip reflow welding is omitted, the preparation of the first welding plate and the preparation of the second welding plate can be simultaneously carried out, flip-chip bonding between a chip and a substrate is realized on the same production line, and electric signal interconnection is realized. The gold bump leveling process links are reduced, the complexity of the process flow is reduced, the yield is improved, the manufacturing cost is reduced, and the production and manufacturing efficiency is improved.
Description
Technical Field
The present application relates to the field of chip technologies, and in particular, to a packaging method for thermocompression bonding and reflow soldering, a flip-chip bonding structure, and a chip structure.
Background
With the rapid development of 5G and artificial intelligence, the demand for computing power is in explosive growth, so that higher requirements are put on packaging of integrated circuit chips, optical chips and the like, and particularly, higher requirements are put on packaging interconnection density and packaging volume. In advanced packaging technology for semiconductor integrated circuit chips, flip chip packaging technology is generally required to realize electrical signal interconnection between chips and substrates. Flip-chip bonding is largely classified into thermocompression bonding (Thermocompression Bonding), thermosonic bonding (Thermosonic Bonding), and Reflow (Mass Reflow).
The conventional gold wire bonding packaging method generally comprises the steps of preparing gold bumps on a chip, leveling the gold bumps for standby by adopting a pressing plate through a hot-pressing bonding process, and then performing reflow soldering flip-chip bonding with a substrate with solder to complete a flip-chip process.
However, the conventional gold wire bonding packaging method has the problems of complex process, long production line, difficulty in realizing packaging in one production line and the like.
Disclosure of Invention
The application provides a packaging method, a flip-chip bonding structure and a chip structure for thermocompression bonding and reflow soldering, which are used for solving the problems that the existing process is complex, the production line is long, and the packaging is difficult to realize in one production line.
In a first aspect, the present application provides a method for packaging thermocompression bonding and reflow soldering, comprising the steps of:
Preparing a plurality of welding spots on one side of a substrate to obtain a first welding plate;
Preparing a plurality of gold bumps on one side of the chip to obtain a second welding plate;
welding one side of the first welding plate with solder with one side of the second welding plate with gold bumps to obtain a packaged chip;
Wherein the welding pressure is 20-25 g/gold bump.
According to the application, the side of the first welding plate with the solder and the side of the second welding plate with the gold salient point are directly welded, so that the step of flattening the gold salient point in the traditional flip-chip reflow welding is omitted, the preparation of the first welding plate and the preparation of the second welding plate can be simultaneously carried out, the production rhythm is consistent, flip-chip bonding between a chip and a substrate is realized on the same production line, and electric signal interconnection is realized. The gold bump leveling process links are reduced, the complexity of the process flow is reduced, the yield is improved, the manufacturing cost is reduced, and the production and manufacturing efficiency is improved. Meanwhile, in order to ensure that the gold bumps of the second welding plate and the solder of the first welding plate are in contact with the solder smoothly during welding, the welding pressure is controlled to be 20-25 g/gold bumps, the welding contact area can be increased, and the welding firmness is improved.
It should be noted that when one side of the first welding plate having solder and one side of the second welding plate having gold bumps are welded, the positions of the first welding plate and the second welding plate need to be aligned to ensure that each gold bump corresponds to each solder point one by one, the number of gold bumps is consistent with the number of welding points, the position of each gold bump corresponds to each welding point to ensure the welding quality, and the alignment accuracy can be improved by the method of high-definition imaging equipment through the alignment marks pre-manufactured on the first welding plate or the second welding plate.
It should be noted that the gold bump may form a gold shoulder during the molding process, and when the first welding plate and the second welding plate are welded, the gold shoulder needs to be flattened, so that the contact area between the gold bump and the welding pad with solder in the first welding plate is maximized, and high-quality electrical signal interconnection is achieved. The welding pressure is lower than 20 g/gold convex points, so that gold shoulders of the gold convex points cannot be completely flattened, and the welding firmness is affected. The welding pressure is higher than 25 g/gold convex points, so that the gold convex points can be shrunken, the ball height is too small, the mechanical supporting effect cannot be well achieved, meanwhile, the operability of the subsequent bottom filling process is not strong, and the yield is low.
In some embodiments, the welding temperature is 217 ℃ to 240 ℃, and the welding temperature is within the range, so that insufficient melting of the solder can be reduced, the condition that the welding spot is shrunken, the surface is not smooth, the cold joint is formed, the mechanical strength is poor and the like can be avoided. Reduces the defects of bridging, short circuit and the like caused by the excessively strong fluidity of the solder, and/or,
The welding time is 15-25 s, the welding time is within the range, the welding flux can be fully melted, the phenomena of cold joint and bridging are reduced, and good connection is formed between the welding spot and the welding pad.
The distribution density of Jin Tu points on the second welding plate is 30-88 points/mu m 2. Under the unit area, the better the welding firmness of the first welding plate and the second welding plate is, however, the higher the welding density of the gold convex points is, the higher the requirement on the forming process of the gold convex points is, and the distribution density of Jin Tu points on the second welding plate is in the range comprehensively considering the welding firmness and the cost, so that the welding firmness can be improved, the welding quality is improved, and the cost is reduced.
In some embodiments, the number of the gold bumps on the second welding plate is 220-660, and the number of the gold bumps on the second welding plate is within the range, so that good welding spots can be formed, and good electrical interconnection performance can be achieved.
In some embodiments, the diameter of the gold bump on the second bonding plate is 40-100 μm, and the diameter of the gold bump on the second bonding plate is within this range, so that the bonding between the gold bump and the bonding pad is firm, the reliability is high, the electrical performance is good, and meanwhile, the interconnection density and the packaging integration level are high.
In some embodiments, the height of the gold bump on the second bonding plate is H, and H1 is 15 μm or less and 50 μm or less, and the height of the gold bump on the second bonding plate is within this range, so that the interconnection density can be made higher, and the feasibility of the underfill process can be ensured.
In some embodiments, the spacing between the adjacent gold bumps on the second welding plate is 10-100 μm, and the spacing between the adjacent gold bumps on the second welding plate is within the range, so that the electric signal interconnection and the mechanical supporting function can be achieved, and meanwhile, the high-density welding spot interconnection is achieved.
In some embodiments, the melting point of the solder of the welding spot on the first welding plate is 217 ℃ to 240 ℃, so that a good bonding welding spot can be formed, the electric performance is stable, the damage risk to the chip microstructure is reduced, the probability of fracture of the welding spot when the welding spot is subjected to external force is reduced, and the strength and the stability of the welding structure are improved.
In a second aspect, the present application provides a flip-chip bonding structure, including the packaged chip manufactured by the thermal compression bonding and reflow soldering packaging method of the first aspect.
In a third aspect, the present application provides a chip structure comprising the flip-chip bonding structure of the second aspect.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a process flow diagram of a prior art thermal compression bonding and reflow soldering packaging method of the present application.
Fig. 2 is a process flow diagram of a thermal compression bonding and reflow soldering packaging method according to an embodiment of the application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described in conjunction with the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Reflow soldering
Reflow soldering is a soldering technique that achieves mechanical and electrical connection between a surface-mount component and a printed board pad by remelting a paste of solder pre-dispensed onto the printed board pad. The core of reflow soldering is the heat conduction process, which transfers heat to the circuit board and components with high efficiency, so that the solder paste is melted and cooled to form a reliable solder joint. The method is widely applied to the fields of consumer electronics, industrial control, automobile electronics and the like, and has the advantages of high efficiency, reliability, strong adaptability and the like. In the reflow soldering process, the accurate control of the temperature rising rate and peak temperature of each temperature zone ensures that the soldering paste is fully melted and forms good welding spots, which is the key for improving the product quality. Reflow soldering is a key technology in electronic manufacturing, and reliable connection of electronic components and a PCB board is achieved by precisely controlling the heating and cooling processes. Not only improves the production efficiency, but also ensures the welding quality of the product.
Thermal compression bonding
The thermocompression bonding is an advanced chip bonding process and is mainly applied to advanced packaging technology. Particularly in applications requiring high accuracy and high reliability, such as solder ball based flip chip bonding packages. The defect of reflow soldering bonding can be well overcome, and more accurate control capability is provided. The core of the thermal compression bonding is to realize the direct metal bonding between the chip and the substrate through the combined action of heat and pressure. Have been widely used in flip chip bonding packages based on solder balls. The principle is similar to that of the traditional diffusion welding, and the main influencing parameters include temperature, pressure and time. In the thermocompression bonding process, the chip and the substrate are both in a vacuum adsorption state, ensuring the flatness thereof. After alignment, bonding is accomplished by precision mechanical control, and the system monitors temperature, pressure and displacement in real time throughout the process. When the chip is contacted with the substrate, the system rapidly increases the temperature above the melting point of the solder balls and rapidly cools and solidifies in the cooling stage.
With the rapid development of 5G and artificial intelligence, the demand for computing power is in explosive growth, so that higher requirements are put on packaging of integrated circuit chips, optical chips and the like, and particularly, higher requirements are put on packaging interconnection density and packaging volume. In advanced packaging technology for semiconductor integrated circuit chips, flip chip packaging technology is generally required to realize electrical signal interconnection between chips and substrates. Flip-chip bonding is largely classified into thermocompression bonding (Thermocompression Bonding), thermosonic bonding (Thermosonic Bonding), and Reflow (Mass Reflow).
As shown in fig. 1, the conventional gold wire bonding packaging method generally comprises the steps of preparing gold bumps on a chip, leveling the gold bumps for standby by using a pressing plate through a thermal compression bonding process, and then performing reflow soldering flip-chip bonding with a substrate with solder to complete a flip-chip process. However, the conventional gold wire bonding packaging method has the problems that the consistency of the leveled gold bumps is required to be controlled at 2 mu m, the whole process flow is complicated due to the addition of steps, the production line is long, packaging is difficult to realize in one production line, the reject ratio is increased, the manufacturing cost is increased, and the efficiency is low.
Therefore, a new packaging structure and a preparation method are needed to be provided, the defects of the traditional packaging are overcome, the traditional packaging structure and method are optimized, and adverse factors are overcome, so that the requirements of high-speed, high-density and low-power consumption packaging required by high-speed operation and artificial intelligence electronic components are met.
In view of this, the application provides a packaging method, a flip-chip bonding structure and a chip structure for thermocompression bonding and reflow soldering, so as to solve the problems of complex process, long production line and difficulty in realizing packaging in one production line.
In a first aspect, as shown in fig. 2, the present application provides a thermal compression bonding and reflow soldering packaging method, which includes the following steps:
Preparing a plurality of welding spots on one side of a substrate to obtain a first welding plate;
Preparing a plurality of gold bumps on one side of the chip to obtain a second welding plate;
welding one side of the first welding plate with solder with one side of the second welding plate with gold bumps to obtain a packaged chip;
Wherein the welding pressure is 20-25 g/gold bump.
According to the application, the side of the first welding plate with the solder and the side of the second welding plate with the gold salient point are directly welded, so that the step of flattening the gold salient point in the traditional flip-chip reflow welding is omitted, the preparation of the first welding plate and the preparation of the second welding plate can be simultaneously carried out, the production rhythm is consistent, flip-chip bonding between a chip and a substrate is realized on the same production line, and electric signal interconnection is realized. The gold bump leveling process links are reduced, the complexity of the process flow is reduced, the yield is improved, the manufacturing cost is reduced, and the production and manufacturing efficiency is improved. Meanwhile, in order to ensure that the gold bumps of the second welding plate and the solder of the first welding plate are in contact with the solder smoothly during welding, the welding pressure is controlled to be 20-25 g/gold bumps, the welding contact area can be increased, and the welding firmness is improved. The bonding pressure includes, but is not limited to, 20 g/gold bump, 20.5 g/gold bump, 21 g/gold bump, 21.5 g/gold bump, 22 g/gold bump, 22.5 g/gold bump, 23 g/gold bump, 23.5 g/gold bump, 24 g/gold bump, 24.5 g/gold bump, or 25 g/gold bump.
It should be noted that when one side of the first welding plate having solder and one side of the second welding plate having gold bumps are welded, the positions of the first welding plate and the second welding plate need to be aligned to ensure that each gold bump corresponds to each solder point one by one, the number of gold bumps is consistent with the number of welding points, the position of each gold bump corresponds to each welding point to ensure the welding quality, and the alignment accuracy can be improved by the method of high-definition imaging equipment through the alignment marks pre-manufactured on the first welding plate or the second welding plate.
It should be noted that the gold bump may form a gold shoulder during the molding process, and when the first welding plate and the second welding plate are welded, the gold shoulder needs to be flattened, so that the contact area between the gold bump and the welding pad with solder in the first welding plate is maximized, and high-quality electrical signal interconnection is achieved. The welding pressure is lower than 20 g/gold convex points, so that gold shoulders of the gold convex points cannot be completely flattened, and the welding firmness is affected. The welding pressure is higher than 25 g/gold convex points, so that the gold convex points can be shrunken, the ball height is too small, the mechanical supporting effect cannot be well achieved, meanwhile, the operability of the subsequent bottom filling process is not strong, and the yield is low.
The gold bump is formed on the bonding pad by gold wire thermosonic bonding, the purity of the gold wire is 99.99%, and 0.001%o Be or 0.001%o Cu can Be doped. The doping of Be and Cu can improve the hardness and tensile strength of the gold wire, and can also reduce the material cost. The diameter of the gold wire can be 15-100 mu m, so that the forming of the gold bumps is facilitated.
It should be noted that, the material of the first solder plate may be alumina, aluminum nitride, or silicon, the material corresponding to the solder joint region of the solder joint is copper or gold, and the solder material of the solder joint may be tin-lead solder, tin-silver solder, tin-copper solder, tin-bismuth solder, tin-zinc solder, or tin-indium solder.
In combination with the first aspect, in some embodiments provided by the application, the welding temperature is 217 ℃ to 240 ℃, and the welding temperature is within the range, so that insufficient melting of the solder can be reduced, and the conditions of shrinkage of the welding spot, unsmooth surface, poor mechanical strength and the like of the welding spot can be reduced. The defects of bridging, short circuit and the like caused by the excessively strong fluidity of the solder are reduced. The temperature of the weld includes, but is not limited to, 217 ℃, 220 ℃, 223 ℃, 225 ℃, 228 ℃, 230 ℃, 232 ℃, 235 ℃, 237 ℃, or 240 ℃.
In combination with the first aspect, in some embodiments provided by the application, the welding time is 15-25 s, and the welding time is in the range, so that the welding flux can be sufficiently melted, the occurrence of the phenomena of cold joint and bridging is reduced, and good connection is formed between the welding spot and the welding pad. The welding time includes, but is not limited to, 15s, 1s, 17s, 18s, 19s, 20s, 21s, 22s, 23s, 24s or 25s.
With reference to the first aspect, in some embodiments of the present application, the Jin Tu points on the second welding plate have a distribution density of 30 to 88 points/μm 2. Under the unit area, the better the welding firmness of the first welding plate and the second welding plate is, however, the higher the welding density of the gold convex points is, the higher the requirement on the forming process of the gold convex points is, and the distribution density of Jin Tu points on the second welding plate is in the range comprehensively considering the welding firmness and the cost, so that the welding firmness can be improved, the welding quality is improved, and the cost is reduced. The distribution density of Jin Tu points includes, but is not limited to, 30/μm 2, 35/μm 2, 40/μm 2, 45/μm 2, 50/μm 2, 55/μm 2, 60/μm 2, 65/μm 2, 70/μm 2, 75/μm 2, 80/μm 2, 85/μm 2, or 88/μm 2.
In combination with the first aspect, in some embodiments of the present application, the number of gold bumps on the second bonding plate is 220-660, and the number of gold bumps on the second bonding plate is within this range, so that good solder joints can be formed, and good electrical interconnection performance can be achieved. The number of gold bumps includes, but is not limited to, 220, 250, 300, 350, 400, 450, 500, 550, or 600.
In combination with the first aspect, in some embodiments of the present application, the diameter of the gold bump on the second bonding plate is 40-100 μm, and the diameter of the gold bump on the second bonding plate is within this range, so that the bonding between the gold bump and the bonding pad is firm, the reliability is high, the electrical performance is good, and meanwhile, the interconnection density and the packaging integration are high. The diameter of the gold bump includes, but is not limited to, 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm or 100 μm.
In combination with the first aspect, in some embodiments provided by the present application, the height of the gold bump on the second bonding plate is H, and is 15 μm and H1 and is less than or equal to 50 μm, and the height of the gold bump on the second bonding plate is within this range, so that the interconnection density can be made higher, and the feasibility of the underfill process can be ensured. The height of the gold bump includes, but is not limited to, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, 45 μm, or 50 μm.
In combination with the first aspect, in some embodiments provided by the application, the spacing between the adjacent gold bumps on the second welding plate is 10-100 μm, and the spacing between the adjacent gold bumps on the second welding plate is within the range, so that the electrical signal interconnection and the mechanical supporting function can be realized, and meanwhile, the high-density welding spot interconnection can be realized. The spacing between adjacent gold bumps includes, but is not limited to, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, or 100 μm.
In combination with the first aspect, in some embodiments provided by the application, the melting point of the solder of the welding spot on the first welding plate is 217 ℃ to 240 ℃, so that a good bonding welding spot can be formed, the electric performance is stable, the damage risk to the chip microstructure is reduced, the probability of fracture of the welding spot when the welding spot is subjected to the action of external force is reduced, and the strength and the stability of the welding structure are improved. The melting point of the solder includes, but is not limited to, 217 ℃, 220 ℃, 225 ℃, 230 ℃, 232 ℃, 235 ℃, 237 ℃, or 240 ℃.
In a second aspect, the present application provides a flip-chip bonding structure, including the packaged chip manufactured by the thermal compression bonding and reflow soldering packaging method of the first aspect. The flip-chip bonding structure has all the technical schemes of the packaging methods of the hot-press bonding and the reflow soldering, so that the flip-chip bonding structure has all the beneficial effects of the packaging methods of the hot-press bonding and the reflow soldering, and the application is not repeated here.
In a third aspect, the present application provides a chip structure comprising the flip-chip bonding structure of the second aspect. The chip structure has all the technical schemes of the packaging method of the hot-press bonding and the reflow soldering, so that the chip structure has all the beneficial effects of the packaging method of the hot-press bonding and the reflow soldering, and the application is not repeated here.
The technical scheme provided by the application is described in detail below with reference to examples.
Example 1
The embodiment 1 of the application provides a packaging method for thermocompression bonding and reflow soldering, which comprises the following steps:
Preparing a plurality of welding spots on one side of a substrate to obtain a first welding plate;
Preparing a plurality of gold bumps on one side of the chip to obtain a second welding plate;
welding one side of the first welding plate with solder with one side of the second welding plate with gold bumps to obtain a packaged chip;
wherein the welding pressure is 25 g/gold bump;
the welding temperature is 217 ℃, and the welding time is 15s;
the distribution density of Jin Tu points on the second welding plate is 88 points/mu m 2, and the number of gold bumps is 880 points;
the diameter of the gold convex points on the second welding plate is 40 mu m, the height is 15 mu m, and the interval between the adjacent gold convex points is 60 mu m;
the melting point of the solder joint on the first solder plate is 217 ℃.
Example 2
The embodiment 2 of the application provides a packaging method for thermocompression bonding and reflow soldering and a processing method thereof.
Preparing a plurality of welding spots on one side of a substrate to obtain a first welding plate;
Preparing a plurality of gold bumps on one side of the chip to obtain a second welding plate;
welding one side of the first welding plate with solder with one side of the second welding plate with gold bumps to obtain a packaged chip;
wherein the welding pressure is 20 g/gold bump;
the welding temperature is 240 ℃, and the welding time is 25s;
The distribution density of Jin Tu points on the second welding plate is 30 points/mu m 2, and the number of gold bumps is 220 points;
the diameter of the gold convex points on the second welding plate is 100 mu m, the height is 50 mu m, and the distance between the adjacent gold convex points is 100 mu m;
the melting point of the solder joint on the first solder plate is 240 ℃.
Example 3
The embodiment 3 of the application provides a packaging method for thermocompression bonding and reflow soldering and a processing method thereof.
Preparing a plurality of welding spots on one side of a substrate to obtain a first welding plate;
Preparing a plurality of gold bumps on one side of the chip to obtain a second welding plate;
welding one side of the first welding plate with solder with one side of the second welding plate with gold bumps to obtain a packaged chip;
wherein the welding pressure is 22.5 g/gold bump;
the welding temperature is 225 ℃ and the welding time is 20s;
The distribution density of Jin Tu points on the second welding plate is 60 points/mu m 2, and the number of gold bumps is 440 points;
the diameter of the gold convex points on the second welding plate is 70 mu m, the height is 30 mu m, and the interval between the adjacent gold convex points is 80 mu m;
The melting point of the solder joint on the first solder plate is 225 ℃.
Comparative example 1
Comparative example 1 of the present application provides a packaging method of thermocompression bonding and reflow soldering, similar to example 2, except that the pressure of soldering is 18 g/gold bump.
In comparative example 1, the pressure of the soldering is less than 22.5 g/gold bump, so that the gold shoulder of the gold bump is not completely flattened, the soldering points are not fully contacted, the binding force is not strong, and the reliability is poor.
Comparative example 2
Comparative example 2 of the present application provides a thermal compression bonding and reflow soldering packaging method similar to example 1, except that the soldering pressure is 26.5 g/gold bump.
The pressure of welding is larger than 25 g/gold convex points in the comparison document 2, so that the gold convex points can be shrunken, the operation is difficult when the bottom filling process is carried out, and filling glue cannot sufficiently flow into gaps, so that the yield is low.
In summary, the step of flattening the gold bump in the traditional flip-chip reflow soldering is omitted by directly soldering the side of the first soldering plate with the solder and the side of the second soldering plate with the gold bump, so that the preparation of the first soldering plate and the preparation of the second soldering plate can be simultaneously performed, the production rhythm is consistent, flip-chip bonding between the chip and the substrate is realized on the same production line, and electric signal interconnection is realized. The gold bump leveling process links are reduced, the complexity of the process flow is reduced, the yield is improved, the manufacturing cost is reduced, and the production and manufacturing efficiency is improved. Meanwhile, in order to ensure that the gold bumps of the second welding plate and the solder of the first welding plate are in contact with the solder smoothly during welding, the welding pressure is controlled to be 20-25 g/gold bumps, the welding contact area can be increased, and the welding firmness is improved.
In the description of the present specification, reference to the terms "one embodiment/manner," "some embodiments/manner," "example," "a particular example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/manner or example is included in at least one embodiment/manner or example of the application. In this specification, the schematic representations of the above terms are not necessarily for the same embodiment/manner or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/modes or examples described in this specification and the features of the various embodiments/modes or examples can be combined and combined by persons skilled in the art without contradiction.
It should be noted that in the present application, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element. In the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically specified otherwise.
The foregoing is only a specific embodiment of the application to enable those skilled in the art to understand or practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
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| CN202411705199.8A CN119601476A (en) | 2024-11-26 | 2024-11-26 | Thermal compression bonding and reflow soldering packaging method, flip-chip bonding structure and chip structure |
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| CN202411705199.8A CN119601476A (en) | 2024-11-26 | 2024-11-26 | Thermal compression bonding and reflow soldering packaging method, flip-chip bonding structure and chip structure |
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