CN119601057A - Failure judgment circuit and failure judgment method, and resistive storage device - Google Patents
Failure judgment circuit and failure judgment method, and resistive storage device Download PDFInfo
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- CN119601057A CN119601057A CN202411557385.1A CN202411557385A CN119601057A CN 119601057 A CN119601057 A CN 119601057A CN 202411557385 A CN202411557385 A CN 202411557385A CN 119601057 A CN119601057 A CN 119601057A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0035—Evaluating degradation, retention or wearout, e.g. by counting writing cycles
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
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Abstract
The disclosure relates to a failure judgment circuit, a failure judgment method and a resistance change storage device. The failure judgment circuit comprises a reference resistance gating circuit and a comparison circuit. The reference resistor gating circuit comprises at least two reference resistor circuits connected in parallel and a control circuit respectively connected with the reference resistor circuits. Wherein, the resistance values of the reference resistors in different reference resistor circuits are different; the control circuit is used for independently gating each reference resistance circuit. The comparison circuit is connected with the resistance change memory array and each reference resistance circuit. The resistive memory array includes a plurality of resistive memory cells including resistive memory cells. The comparison circuit is configured to compare the resistance values between the resistance change memory cell and the reference resistor in the reference resistor circuit to output a failure determination signal according to the comparison result of the resistance values between the resistance change memory cell and the reference resistor. The method and the device can reduce the erasing times while judging whether the resistance change memory unit is invalid.
Description
Technical Field
The disclosure relates to the technical field of storage, and in particular relates to a failure judgment circuit, a failure judgment method and a resistance change storage device.
Background
The resistive random access memory (RESISTIVE RANDOM ACCESS MEMORY, simply referred to as RRAM) is a volatile or nonvolatile memory that records and stores data information based on a change in resistance, has characteristics of high speed and low power consumption, and can realize a memory function in a small size. The preparation process of the resistive random access memory device has good compatibility with the preparation process of the traditional Complementary Metal Oxide Semiconductor (CMOS) circuit. In view of these advantages, resistive random access memory devices are becoming particularly important in the context of current intelligent products and the explosive growth of the internet of things. However, the resistive random access memory device also generally faces problems of writing errors, reading disturbances, reading errors, thermal stability and the like, and increases difficulty for large-scale application of the resistive random access memory device.
Disclosure of Invention
Based on this, the embodiment of the disclosure provides a failure judgment circuit, a failure judgment method and a resistance change storage device, which can reduce erasing times while judging whether a resistance change storage unit fails, so as to improve the service life of the resistance change storage device and reduce the power consumption of the resistance change storage device, thereby being beneficial to realizing the large-scale application of the resistance change storage device.
To achieve the above object, in a first aspect, some embodiments of the present disclosure provide a failure judgment circuit including a reference resistance gating circuit and a comparison circuit. The reference resistor gating circuit comprises at least two reference resistor circuits connected in parallel and a control circuit respectively connected with the reference resistor circuits. The control circuit is used for responding to the control instruction to independently strobe each reference resistance circuit. The comparison circuit is connected with the resistance change memory array and each reference resistance circuit, wherein the resistance change memory array comprises a plurality of resistance change memory units which are arranged in an array mode. The comparison circuit is configured to compare the resistance values between the resistance change memory cell and the reference resistor in the reference resistor circuit to output a failure determination signal according to the comparison result of the resistance values between the resistance change memory cell and the reference resistor.
In some embodiments of the present disclosure, the reference resistance gating circuit includes a reference resistance circuit, a first reference resistance circuit, and a second reference resistance circuit. The reference resistor circuit includes a reference resistor and a reference switch circuit. The first reference resistance circuit includes a first reference resistance and a first switching circuit. The second reference resistance circuit includes a second reference resistance and a second switching circuit. The first end of the reference resistor, the first end of the first reference resistor and the first end of the second reference resistor are all grounded, the second end of the reference resistor is connected with the comparison circuit through the reference switch circuit, the second end of the first reference resistor is connected with the comparison circuit through the first switch circuit, and the second end of the second reference resistor is connected with the comparison circuit through the second switch circuit. The reference switch circuit, the first switch circuit and the second switch circuit are also respectively connected with the control circuit. The control circuit is configured to gate a reference switching circuit to output the storage data of the resistance change memory cell according to a resistance value magnitude relation between the resistance change memory cell and the reference resistor, and to gate the first reference resistance circuit and/or the second reference resistance circuit to output the failure judgment signal according to a resistance value magnitude relation between the resistance change memory cell and the first reference resistor or the second reference resistor.
In some embodiments of the present disclosure, the resistance of the first reference resistor is ten times greater than the first average value of the resistance of each resistive memory cell in the high resistance state. The resistance value of the second reference resistor is less than one tenth of the second average value of the resistance values of the resistance change memory cells in the low resistance state.
In some embodiments of the present disclosure, the reference switching circuit and the first switching circuit include a first conductivity type transistor. The second switching circuit includes a second conductivity type transistor. The control circuit comprises a first control circuit and a second control circuit, wherein the first control circuit is connected with the reference switch circuit and the second switch circuit respectively, and the second control circuit is connected with the first switch circuit. The first control circuit is configured to generate a reference control instruction to turn on the reference switching circuit and to generate a second control instruction to turn on the second switching circuit. Wherein the reference control command and the second control command have opposite level signals. The second control circuit is configured to generate a first control instruction to turn on the first switching circuit.
In some embodiments of the present disclosure, the first conductivity type transistor includes an NMOS transistor, the second conductivity type transistor includes a PMOS transistor, the first control circuit includes a first power circuit for providing a first high level signal and a first low level signal in a time sharing manner, and the second control circuit includes a second power circuit for providing a second high level signal.
In a second aspect, some embodiments of the present disclosure further provide a failure determination method, which may be applied to the failure determination circuit described in any of the foregoing embodiments. The failure judgment method comprises the steps of independently gating a reference resistor circuit in a reference resistor gating circuit in response to a control instruction, wherein the reference resistor gating circuit comprises at least two reference resistor circuits connected in parallel, the resistance values of reference resistors in different reference resistor circuits are different, comparing the resistance values between a resistance change memory unit of a resistance change memory unit in a resistance change memory array and the reference resistor of the reference resistor circuit to be gated, and outputting a failure judgment signal according to the comparison result of the resistance values between the resistance change memory unit and the reference resistor.
In some embodiments of the present disclosure, the reference resistance gating circuit includes a reference resistance circuit, a first reference resistance circuit, and a second reference resistance circuit, wherein the responding control instruction independently gates the reference resistance circuit in the reference resistance gating circuit, compares the resistance values between the resistance change memory cells of the resistance change memory array and the reference resistance of the gated reference resistance circuit, and outputs a failure judgment signal according to the comparison result of the resistance values between the resistance change memory cells and the reference resistance, and may include the following steps.
A reference resistor circuit is gated.
And comparing the resistance value of the reference resistor in the resistance change memory cell and the reference resistor circuit.
And acquiring the storage data of the resistance change storage unit according to the comparison result of the resistance values of the resistance change storage unit and the reference resistor.
The first reference resistance circuit or the second reference resistance circuit is gated.
The resistance values of the first reference resistor in the gated first reference resistor circuit or the second reference resistor in the gated second reference resistor circuit are compared with each other.
And outputting a failure judgment signal according to a comparison result of the resistance values between the resistance change memory unit and the corresponding first reference resistor or second reference resistor.
And outputting the storage data of the resistance change storage unit when the failure judgment signal is a non-failure signal.
In some embodiments of the present disclosure, the resistance of the first reference resistor is ten times greater than the first average value of the resistance of each resistive memory cell in the high resistance state. The resistance value of the second reference resistor is less than one tenth of the second average value of the resistance values of the resistance change memory cells in the low resistance state.
Correspondingly, the step of outputting the failure judgment signal according to the comparison result of the resistance value between the resistance change storage unit and the corresponding first reference resistor or the second reference resistor comprises the step of outputting the failure judgment signal that the resistance change storage unit is in open circuit failure when the resistance value of the resistance change storage unit is larger than the first reference resistor, and outputting the failure judgment signal that the resistance change storage unit is in short circuit failure when the resistance value of the resistance change storage unit is smaller than the second reference resistor.
In some embodiments of the present disclosure, the baseline reference resistance circuit further includes a baseline switching circuit connected to the baseline reference resistance. The first reference resistor circuit further includes a first switching circuit coupled to the first reference resistor. The second reference resistor circuit further includes a second switching circuit coupled to the second reference resistor. The control circuit comprises a first control circuit and a second control circuit, wherein the first control circuit is connected with the reference switch circuit and the second switch circuit respectively, and the second control circuit is connected with the first switch circuit.
Correspondingly, the gating reference resistor circuit comprises a first control circuit, a second control circuit and a reference switch circuit, wherein the first control circuit sends a reference control instruction to the reference switch circuit, and the reference switch circuit is conducted.
The first reference resistance circuit or the second reference resistance circuit is gated, and the second reference resistance circuit comprises a second control circuit which sends a first control instruction to the first switch circuit to conduct the first switch circuit, or the first control circuit sends a second control instruction to the second switch circuit to conduct the second switch circuit.
The reference control command and the second control command are opposite in level signal.
In a third aspect, some embodiments of the present disclosure further provide a resistive memory device including a resistive memory array and a failure determination circuit coupled to the resistive memory array and as described in any of the embodiments above.
Embodiments of the present disclosure may/have at least the following advantages:
In the embodiment of the disclosure, by setting the reference resistor gating circuit, specifically, setting at least two reference resistor circuits connected in parallel and a control circuit respectively connected with the reference resistor circuits, and enabling the resistance values of the reference resistors in different reference resistor circuits to be different, each reference resistor circuit is connected with the resistance change storage unit through the comparison circuit, the control circuit can independently gate different reference resistor circuits in response to a control instruction, and therefore, failure judgment signals can be output according to comparison results of the resistance values between the resistance change storage unit and the reference resistors in the gated reference resistor circuits by comparing the resistance values between the resistance change storage unit and the reference resistors. Therefore, according to the embodiment of the disclosure, the failure judgment signal is output by selecting different reference resistors to compare the resistance values of the resistance change storage units, so that 2 erasing actions for failure judgment can be avoided from being added when data are stored each time, the erasing times can be reduced when judging whether the resistance change storage units fail or not, the service life of the resistance change storage device is prolonged, the power consumption of the resistance change storage device is reduced, and the large-scale application of the resistance change storage device is facilitated.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments or the conventional techniques of the present disclosure, the drawings required for the descriptions of the embodiments or the conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to the drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a schematic diagram of a failure determination circuit according to some embodiments;
FIG. 2 is a schematic diagram of another failure determination circuit provided in some embodiments;
FIG. 3 is a schematic diagram of a further failure determination circuit provided in some embodiments;
FIG. 4 is a schematic diagram of a distribution of range of values of a baseline reference resistance provided in some embodiments;
FIG. 5 is a flow chart of a failure determination method according to some embodiments;
FIG. 6 is a flow chart of another failure determination method according to some embodiments.
Reference numerals illustrate:
1-reference resistor gating circuit, 11-reference resistor circuit, 11A-reference resistor circuit, rref-reference resistor, 111-reference switch circuit, 11B-first reference resistor circuit, R1-first reference resistor, 112-first switch circuit, 11C-second reference resistor circuit, R2-second reference resistor, 113-second switch circuit, 12-control circuit, 12A-first control circuit, 12B-second control circuit, 2-comparison circuit, 3-resistance memory array, SA-read sense amplifier.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or be connected to the other element through intervening elements. Further, "connection" in the following embodiments should be understood as "electrical connection", "communication connection", and the like if there is transmission of electrical signals or data between objects to be connected.
It should be understood that the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the related art, a resistive memory device is manufactured based on a technical principle that a resistive memory cell can realize reversible conversion between a high-resistance state and a low-resistance state. In addition, in the application of the digital circuit, the resistance change memory unit can output data 1 when in a high resistance state, and can output data 0 when in a low resistance state. Next, when determining whether the state of the resistive memory cell is a high-resistance state or a low-resistance state, a reference resistor is usually required to be set for distinguishing the high-resistance state or the low-resistance state of the resistive memory cell, and the reference resistor is usually between the high-resistance state resistance value and the low-resistance state resistance value of the resistive memory cell. Then, since the basic structure of the resistive memory cell in the resistive memory device is generally composed of a phase change material and a lower electrode and an upper electrode respectively connected to the phase change material, the phase change material is often a non-conductive insulating layer film, and thus the resistive memory cell in the resistive memory device will exhibit two states of Open failure or Short failure when the resistive memory cell fails.
For example, if the resistive memory cell exhibits an Open (Open) failure, data 1 is read regardless of whether the resistive memory cell is writing data 0 or writing data 1. Similarly, if the resistive memory cell exhibits a Short circuit (Short) failure, data 0 is read regardless of whether the resistive memory cell is writing data 0 or writing data 1.
In some embodiments, to determine whether a resistive memory cell is failed, the failure state of the resistive memory cell is determined by requiring repeated writing of data 0 and data 1, and by data reading. However, such an operation requires adding 2 erasing actions (for example, writing data 0 and writing data 1) of failure judgment every time data is stored, which easily results in a large number of repeated erasing times of the resistive random access memory device, for example, about 1E8 times, and thus not only reduces the lifetime of the resistive random access memory device, but also easily increases the power consumption of the resistive random access memory device.
Based on this, the embodiment of the disclosure provides a failure judgment circuit, a failure judgment method and a resistance change storage device, which can reduce erasing times while judging whether a resistance change storage unit fails, so as to improve the service life of the resistance change storage device and reduce the power consumption of the resistance change storage device, thereby being beneficial to realizing the large-scale application of the resistance change storage device.
Referring to fig. 1, some embodiments of the present disclosure provide a failure determination circuit including a reference resistor gating circuit 1 and a comparison circuit 2. The reference resistance gating circuit 1 includes at least two reference resistance circuits 11 connected in parallel, and a control circuit 12 connected to each of the reference resistance circuits 11. Wherein the reference resistances in the different reference resistance circuits 11 differ in resistance value, and the control circuit 12 is configured to independently gate each reference resistance circuit 11 in response to a control instruction. The comparison circuit 2 is connected with the resistive memory array 3 and each reference resistor circuit 11, wherein the resistive memory array 3 comprises a plurality of resistive memory units which are arranged in an array manner. The comparison circuit 2 is configured to compare the magnitude of the resistance value between the resistance change memory cell and the reference resistor in the reference resistor circuit 11 that is being turned on, to output a failure judgment signal according to the comparison result of the magnitude of the resistance value between the resistance change memory cell and the reference resistor.
In the embodiment of the disclosure, by setting the reference resistor gating circuit 1, specifically, setting at least two reference resistor circuits 11 connected in parallel and a control circuit 12 connected to each reference resistor circuit 11 respectively, and making the resistance values of the reference resistors in different reference resistor circuits 11 different, each reference resistor circuit 11 is connected to the resistive random access memory unit through the comparison circuit 2, the control circuit 12 can independently gate different reference resistor circuits 11 in response to a control instruction, so that by comparing the resistance values between the resistive random access memory unit and the reference resistors in the gated reference resistor circuits 11, a failure judgment signal can be output according to the comparison result of the resistance values between the resistive random access memory unit and the reference resistors. Therefore, according to the embodiment of the disclosure, the failure judgment signal is output by selecting different reference resistors to compare the resistance values of the resistance change storage units, so that 2 erasing actions for failure judgment can be avoided from being added when data are stored each time, the erasing times can be reduced when judging whether the resistance change storage units fail or not, the service life of the resistance change storage device is prolonged, the power consumption of the resistance change storage device is reduced, and the large-scale application of the resistance change storage device is facilitated.
Referring to fig. 2, in some embodiments of the present disclosure, the reference resistance gating circuit 1 includes a reference resistance circuit 11A, a first reference resistance circuit 11B, and a second reference resistance circuit 11C. The reference resistance circuit 11A includes a reference resistance Rref and a reference switching circuit 111. The first reference resistance circuit 11B includes a first reference resistance R1 and a first switch circuit 112. The second reference resistance circuit 11C includes a second reference resistance R2 and a second switch circuit 113. The first end of the reference resistor Rref, the first end of the first reference resistor R1 and the first end of the second reference resistor R2 are all grounded, the second end of the reference resistor Rref is connected to the comparison circuit 2 through the reference switch circuit 111, the second end of the first reference resistor R1 is connected to the comparison circuit 2 through the first switch circuit 112, and the second end of the second reference resistor R2 is connected to the comparison circuit 2 through the second switch circuit 113. The reference switch circuit 111, the first switch circuit 112, and the second switch circuit 113 are also connected to the control circuit 12, respectively. The control circuit 12 is configured to gate the reference switch circuit 111 to output the stored data of the resistive memory cell according to the resistance magnitude relation between the resistive memory cell and the reference resistor Rref, and to gate the first reference resistor circuit 112 and/or the second reference resistor circuit 113 to output the failure determination signal according to the resistance magnitude relation between the resistive memory cell and the first reference resistor 112 or the second reference resistor 113.
It is to be understood that, for example, the reference switch circuit 111, the first switch circuit 112 and the second switch circuit 113 may be configured by using switch transistors, but the present disclosure is not limited thereto, and any switch device capable of performing an on or off operation in response to a control instruction may be used as the corresponding switch circuit. In some embodiments of the present disclosure, please understand in conjunction with fig. 2 and 3 that the reference switch circuit 111 and the first switch circuit 112 comprise transistors of the first conductivity type. The second switching circuit 113 includes a second conductivity type transistor.
Accordingly, the control circuit 12 includes a first control circuit 12A connected to the reference switch circuit 111 and the second switch circuit 113, respectively, and a second control circuit 12B connected to the first switch circuit 112. The first control circuit 12A is configured to generate a reference control instruction to turn on the reference switching circuit and to generate a second control instruction to turn on the second switching circuit, wherein the reference control instruction and the second control instruction are opposite in level signal. The second control circuit 12B is configured to generate a first control instruction to turn on the first switch circuit 111.
The first conductivity type transistor is, for example, an NMOS transistor that is turned on in response to a high level signal, i.e., the reference control command and the first control command may be the same high level signal or different high level signals. The second conductivity type transistor is a PMOS transistor and is turned on in response to a low level signal, i.e., the second control command may be a low level signal. Also, referring to fig. 3, optionally, the first control circuit 12A includes, but is not limited to, a first power circuit, for example, for providing a first high level signal (e.g., a reference control command) and a first low level signal (e.g., a second control command) in a time-sharing manner. The second control circuit 12B includes, but is not limited to, a second power circuit, for example, for providing a second high level signal (e.g., a first control instruction).
On the contrary, the first conduction type transistor is a PMOS transistor, the second conduction type transistor is an NMOS transistor, and the control instructions can be correspondingly matched with the conduction type generation of the transistors.
It should be noted that, referring to fig. 4, in some embodiments of the present disclosure, the resistance range of the reference resistor Rref is located between the high-resistance normal distribution interval of each resistive memory cell and the low-resistance normal distribution interval of each resistive memory cell.
The low-resistance normal distribution interval of each resistance-change memory cell refers to a low-resistance normal distribution interval of each resistance-change memory cell, wherein after each resistance-change memory cell in the resistance-change memory array is written into a low-resistance state, the resistance value (abscissa) and the sample size (ordinate) of each resistance-change memory cell accord with a first normal distribution Q1, and the resistance value interval corresponding to the first normal distribution Q1 is the low-resistance normal distribution interval of each resistance-change memory cell. The high-resistance normal distribution interval of each resistance-change memory cell refers to a high-resistance normal distribution interval of each resistance-change memory cell, wherein after each resistance-change memory cell in the resistance-change memory array is written into a high-resistance state, the resistance value (abscissa) and the sample size (ordinate) of each resistance-change memory cell accord with the second normal distribution Q2, and the resistance value interval corresponding to the second normal distribution Q2 is the high-resistance normal distribution interval of each resistance-change memory cell.
Accordingly, the resistance range of the reference resistor Rref is located between the high resistance normal distribution interval of each resistance change memory cell and the low resistance normal distribution interval of each resistance change memory cell, which means that the resistance range of the reference resistor Rref is located in the resistance range corresponding to the blank area between the first normal distribution Q1 and the second normal distribution Q2.
In some embodiments of the present disclosure, please continue to refer to fig. 4, the resistance of the first reference resistor R1 is more than ten times (i.e. more than an order of magnitude) the first average value a of the resistance of each resistive memory cell in the high-resistance state, for example, the first average value a is R A, and the first reference resistor R1 may be 10R A. The resistance of the second reference resistor R2 is less than one tenth (i.e. less than an order of magnitude) of the second average value B of the resistance of each resistive memory cell in the low resistance state, for example, the second average value B is R B, and the second reference resistor R2 may be 0.1R B.
For example, the first average value a of the resistance values is a resistance value corresponding to the symmetry axis in the second normal distribution Q2, and the second average value B of the resistance values is a resistance value corresponding to the symmetry axis in the first normal distribution Q1.
In a second aspect, some embodiments of the present disclosure further provide a failure determination method, which may be applied to the failure determination circuit described in any of the foregoing embodiments. The foregoing failure determination circuit has technical advantages, and the failure determination method is also provided, which will not be described herein.
Referring to fig. 5, the failure determination method may include the following steps S100 and S200.
Step S100, independently gating reference resistance circuits in reference resistance gating circuits in response to a control instruction, wherein the reference resistance gating circuits comprise at least two reference resistance circuits connected in parallel, and the resistance values of reference resistances in different reference resistance circuits are different.
Step S200, comparing the resistance values between the resistance change memory units of the resistance change memory units in the resistance change memory array and the reference resistor of the gated reference resistor circuit, and outputting a failure judgment signal according to the comparison result of the resistance values between the resistance change memory units and the reference resistor.
In some embodiments of the present disclosure, please understand with reference to fig. 2 and 3 that the reference resistor gating circuit 1 includes a reference resistor circuit 11A, a first reference resistor circuit 11B, and a second reference resistor circuit 11C, wherein in step S100, the reference resistor circuits in the reference resistor gating circuit are independently gated in response to a control command, and in step S200, the resistance values between the resistance change memory cells of the resistance change memory array and the reference resistors of the gated reference resistor circuits are compared, and a failure determination signal is output according to the comparison result of the resistance values between the resistance change memory cells and the reference resistors.
Referring to fig. 6, the failure determination method may include the following steps S10 to S70.
Step S10, gating the reference resistor circuit.
Step S20, comparing the resistance values of the reference resistors in the resistance change memory cell and the reference resistor circuit.
And step S30, obtaining the storage data of the resistance change storage unit according to the comparison result of the resistance values of the resistance change storage unit and the reference resistor.
In step S40, the first reference resistor circuit or the second reference resistor circuit is gated.
Step S50, comparing the resistance values of the first reference resistor in the resistive memory cell and the first reference resistor in the first reference resistor circuit to be turned on or the second reference resistor in the second reference resistor circuit to be turned on.
Step S60, outputting a failure judgment signal according to a comparison result of the resistance values between the resistance change memory unit and the corresponding first reference resistor or the corresponding second reference resistor.
Step S70, outputting the storage data of the resistance change storage unit when the failure judgment signal is not the failure signal.
As understood in conjunction with fig. 3,4 and 6, in some embodiments of the present disclosure, the resistance range of the reference resistor Rref is located between the high-resistance normal distribution interval of each resistive memory cell and the low-resistance normal distribution interval of each resistive memory cell. The resistance value of the first reference resistor R1 is more than ten times of the first average value A of the resistance values of the resistance change memory cells in the high resistance state. The resistance value of the second reference resistor R2 is less than one tenth of the second average value B of the resistance values of the resistance change memory cells in the low resistance state.
Correspondingly, in the step S60, a failure judgment signal is output according to a comparison result of the resistance values between the resistance change memory unit and the corresponding first reference resistor or the corresponding second reference resistor, wherein the failure judgment signal comprises that the resistance change memory unit is an open circuit failure judgment signal when the resistance value of the resistance change memory unit is larger than the first reference resistor, and the failure judgment signal is output that the resistance change memory unit is a short circuit failure when the resistance value of the resistance change memory unit is smaller than the second reference resistor.
Here, the open circuit failure includes, for example, early preparation failure of the resistive memory cell, end of life of the resistive memory cell, or failure conditions such as severe application environment of the resistive memory cell. The short circuit failure comprises the failure conditions of early preparation failure of the resistive random access memory unit, breakdown of a medium in the resistive random access memory unit or severe application environment of the resistive random access memory unit, and the like.
In some embodiments of the present disclosure, the reference resistance circuit further comprises a reference switch circuit connected to the reference resistance, the first reference resistance circuit further comprises a first switch circuit connected to the first reference resistance, and the second reference resistance circuit further comprises a second switch circuit connected to the second reference resistance. The control circuit comprises a first control circuit and a second control circuit, wherein the first control circuit is connected with the reference switch circuit and the second switch circuit respectively, and the second control circuit is connected with the first switch circuit.
Correspondingly, the step S10 of gating the reference resistance circuit comprises the steps that the first control circuit sends a reference control instruction to the reference switch circuit, and the reference switch circuit is turned on.
In the step S40, the first reference resistor circuit or the second reference resistor circuit is selected, and the step S comprises the step that the second control circuit sends a first control instruction to the first switch circuit to conduct the first switch circuit, or the step S40 comprises the step that the first control circuit sends a second control instruction to the second switch circuit to conduct the second switch circuit.
Illustratively, the reference control command and the second control command are opposite in level signal.
It should be understood that, although the steps in the flowcharts of fig. 5 and 6 are shown in order as indicated by the arrows, these steps are not necessarily performed in order as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least a portion of the steps in fig. 5 and 6 may include a plurality of steps or stages, which are not necessarily performed at the same time, but may be performed at different times, and the order of the execution of the steps or stages is not necessarily sequential, but may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or steps.
For example, it should be added that in other possible embodiments, the reference resistor circuit, the first reference resistor circuit, and the second reference resistor circuit may be randomly gated, or may be gated in other predetermined sequences, for example, the first reference resistor circuit may be gated first, if the failure determination signal may be determined directly, the second reference resistor circuit may not be further gated, or, for example, the second reference resistor circuit may be gated first, if the failure determination signal may be determined directly, the first reference resistor circuit may not be further gated. The embodiment of the disclosure is not limited to this, and can output the failure judgment signal through the comparison result of the resistance value between the reference resistor and the resistance change memory cell.
In order to more clearly illustrate the failure determination method provided by the embodiments of the present disclosure, one possible implementation of the failure determination method is described in detail below in conjunction with the failure determination circuit shown in fig. 3.
Referring to fig. 3, the first conductivity type transistor is an NMOS transistor, and the second conductivity type transistor is a PMOS transistor. The first control circuit 12A is a first power supply circuit for supplying a high level signal. The second control circuit 12B is a second power supply circuit for supplying a low level signal.
First, a high level signal (i.e., a reference control command) is provided by the first power supply circuit (12A), the NMOS transistor of the reference resistor circuit 11A is turned on in response to the high level signal, and the comparison circuit 2 can output data 1 (i.e., the stored data of the resistive memory cell is 1) when the resistance value of the resistive memory cell is greater than the reference resistor Rref and output data 0 (i.e., the stored data of the resistive memory cell is 0) when the resistance value of the resistive memory cell is less than the reference resistor Rref by comparing the resistance values of the resistive memory cell and the reference resistor Rref. At this time, the PMOS transistor of the second reference resistor circuit 11C is in an off state in response to the high level signal.
The comparison circuit 2 can indicate that the resistive memory unit is in a high resistance state or in an open circuit failure when outputting the data 1, and can indicate that the resistive memory unit is in a low resistance state or in a short circuit failure when outputting the data 0, so that the first reference resistor circuit 11B or the second reference resistor circuit 11C is correspondingly gated to output a failure judgment signal according to the comparison result of the resistance value between the resistive memory unit and the corresponding first reference resistor or second reference resistor.
Specifically, the first power supply circuit (12A) provides a low-level signal (i.e., a second control instruction), the PMOS transistor of the second reference resistor circuit 11C is turned on in response to the low-level signal, and the comparison circuit 2 can output data 0 (failure determination signal) when the resistance of the resistance change memory cell is smaller than the resistance of the second reference resistor R2 by comparing the resistances of the resistance change memory cell and the second reference resistor R2, i.e., determining that the resistance change memory cell is short-circuited. At this time, the NMOS transistor of the reference resistance circuit 11A is in an off state in response to the low level signal.
The second power supply circuit (12B) provides a high level signal (i.e. a first control command), the NMOS transistor of the first reference resistor circuit 11B is turned on in response to the high level signal, and the comparison circuit 2 can output data 1 (failure judgment signal) when the resistance value of the resistance change memory cell is greater than the first reference resistor R1 by comparing the resistance values of the resistance change memory cell and the first reference resistor R1, i.e. judges that the resistance change memory cell is open-circuited and failed. At this time, the NMOS transistor of the reference resistance circuit 11A and the PMOS transistor of the second reference resistance circuit 11C are both in an off state.
It will be appreciated that in some embodiments, the first power supply circuit (12A) provides a low level signal (i.e., the second control command) when the comparison circuit 2 outputs data 0 by comparing the resistance values of the resistive memory cell and the reference resistor Rref. The second power supply circuit (12B) supplies a high level signal (i.e., a first control instruction) when the comparison circuit 2 outputs the data 1 by comparing the resistance values of the resistance change memory cell and the reference resistor Rref.
In a third aspect, some embodiments of the present disclosure further provide a resistive memory device including a resistive memory array and a failure determination circuit coupled to the resistive memory array and as described in any of the embodiments above. The failure judgment circuit has the technical advantages that the resistance change storage device also has. The embodiments of the present disclosure will not be described in detail.
In some embodiments of the present disclosure, as will be understood with reference to fig. 3, the resistive random access memory device further includes a read sense amplifier SA connected to the resistive random access memory array, wherein the read sense amplifier SA may be multiplexed as the comparison circuit 2 in the failure determination circuit. Therefore, the comparison circuit 2 does not need to be independently additionally arranged, and the structure of the resistance change storage device and the preparation process thereof are facilitated to be simplified.
It will be understood that the circuit branch of the failure determination circuit formed by the reference resistor circuit 11A and the comparison circuit 2 is a data reading circuit of the resistive memory cells in the resistive memory array, that is, when the failure determination circuit determines that the resistive memory cells are not failed, the comparison circuit 2 compares the resistance values of the reference resistor Rref in the resistive memory cells and the reference resistor circuit 11A, so as to output the read data 1 (i.e., the resistive memory cells are in a high resistance state) or the read data 0 (i.e., the resistive memory cells are in a low resistance state).
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure. Accordingly, the scope of protection of the present disclosure should be determined by the following claims.
Claims (10)
1. A failure judgment circuit, characterized by comprising:
a reference resistance gating circuit comprising:
At least two reference resistor circuits connected in parallel, and resistance values of reference resistors in different reference resistor circuits are different;
a control circuit, respectively connected with the reference resistance circuits, configured to independently gate the reference resistance circuits in response to a control instruction;
The comparison circuit is used for comparing the resistance values between the resistance change memory units and the reference resistors in the gated reference resistor circuit so as to output failure judgment signals according to the comparison result of the resistance values between the resistance change memory units and the reference resistors.
2. The failure judgment circuit according to claim 1, wherein the reference resistance gating circuit includes:
The reference resistor circuit comprises a reference resistor and a reference switch circuit;
a first reference resistance circuit including a first reference resistance and a first switching circuit;
the second reference resistor circuit comprises a second reference resistor and a second switch circuit;
The first end of the reference resistor, the first end of the first reference resistor and the first end of the second reference resistor are all grounded, the second end of the reference resistor is connected with the comparison circuit through the reference switch circuit, the second end of the first reference resistor is connected with the comparison circuit through the first switch circuit, and the second end of the second reference resistor is connected with the comparison circuit through the second switch circuit;
the reference switch circuit, the first switch circuit and the second switch circuit are also respectively connected with the control circuit;
the control circuit is configured to gate the reference switch circuit to output the storage data of the resistive memory cell according to a resistance value magnitude relation between the resistive memory cell and the reference resistor, and to gate the first reference resistor circuit and/or the second reference resistor circuit to output the failure determination signal according to a resistance value magnitude relation between the resistive memory cell and the first reference resistor or the second reference resistor.
3. The failure determination circuit of claim 2, wherein the resistance of the first reference resistor is greater than ten times the first average value of the resistance of each of the resistive memory cells in the high-resistance state, and the resistance of the second reference resistor is less than one tenth the second average value of the resistance of each of the resistive memory cells in the low-resistance state.
4. The failure judgment circuit according to claim 2 or 3, wherein the reference switching circuit and the first switching circuit include a first conductivity type transistor;
The control circuit includes:
The first control circuit is respectively connected with the reference switch circuit and the second switch circuit and is configured to generate a reference control instruction to conduct the reference switch circuit and generate a second control instruction to conduct the second switch circuit;
And the second control circuit is connected with the first switch circuit and is configured to generate a first control instruction to conduct the first switch circuit.
5. The failure determination circuit of claim 4, wherein the first conductivity type transistor includes an NMOS transistor and the second conductivity type transistor includes a PMOS transistor, the first control circuit includes a first power supply circuit for providing a first high level signal and a first low level signal, and the second control circuit includes a second power supply circuit for providing a second high level signal.
6. A failure judgment method, characterized by comprising:
The reference resistance gating circuit comprises at least two reference resistance circuits connected in parallel, and the resistance values of reference resistors in different reference resistance circuits are different;
And comparing the resistance values between the resistance change memory units of the resistance change memory units in the resistance change memory array and the reference resistor of the reference resistor circuit which is gated, and outputting a failure judgment signal according to the comparison result of the resistance values between the resistance change memory units and the reference resistor.
7. The method of judging failure according to claim 6, wherein the reference resistance gating circuit includes a reference resistance circuit, a first reference resistance circuit, and a second reference resistance circuit, wherein the independently gating the reference resistance circuits in the reference resistance gating circuit in response to the control command, and comparing the resistance values between the resistance change memory cells of the resistance change memory array and the reference resistances of the reference resistance circuits to be gated, and outputting a failure judgment signal according to the comparison result of the resistance values between the resistance change memory cells and the reference resistances, includes:
Gating the baseline reference resistance circuit;
Comparing the resistance value of the resistance change memory unit with that of a reference resistor in the reference resistor circuit;
Acquiring storage data of the resistance change storage unit according to a comparison result of the resistance values of the resistance change storage unit and the reference resistor;
Gating the first reference resistance circuit or the second reference resistance circuit;
Comparing the resistance values of the first reference resistor in the first reference resistor circuit which is gated with the resistance values of the second reference resistor in the second reference resistor circuit which is gated;
outputting the failure judgment signal according to a comparison result of the resistance values between the resistance change memory unit and the corresponding first reference resistor or the second reference resistor;
And outputting the storage data of the resistance change storage unit when the failure judgment signal is a non-failure signal.
8. The method of claim 7, wherein the first reference resistor has a resistance greater than ten times the first average value of the resistance of each of the resistive memory cells in the high resistive state, and the second reference resistor has a resistance less than one tenth the second average value of the resistance of each of the resistive memory cells in the low resistive state;
The outputting the failure judgment signal according to the comparison result of the resistance values between the resistance change memory unit and the corresponding first reference resistor or the second reference resistor comprises the following steps:
Outputting a failure judgment signal that the resistance change memory unit is in open circuit failure when the resistance value of the resistance change memory unit is larger than the first reference resistance;
And outputting a failure judgment signal that the resistance change memory unit is failed due to short circuit when the resistance value of the resistance change memory unit is smaller than the second reference resistance.
9. The failure judgment method according to claim 7 or 8, wherein the reference resistance circuit further includes a reference switch circuit connected to the reference resistance, the first reference resistance circuit further includes a first switch circuit connected to the first reference resistance, and the second reference resistance circuit further includes a second switch circuit connected to the second reference resistance;
The first control circuit sends a reference control instruction to the reference switch circuit to conduct the reference switch circuit;
the gating of the first reference resistance circuit or the second reference resistance circuit comprises the steps that the second control circuit sends a first control instruction to the first switch circuit to conduct the first switch circuit, or the first control circuit sends a second control instruction to the second switch circuit to conduct the second switch circuit;
Wherein the reference control command and the second control command have opposite level signals.
10. A resistive memory device is characterized by comprising a resistive memory array and a failure judgment circuit which is connected with the resistive memory array and is in any one of claims 1-5.
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| CN202411557385.1A CN119601057A (en) | 2024-11-04 | 2024-11-04 | Failure judgment circuit and failure judgment method, and resistive storage device |
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| CN202411557385.1A CN119601057A (en) | 2024-11-04 | 2024-11-04 | Failure judgment circuit and failure judgment method, and resistive storage device |
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| CN119601057A true CN119601057A (en) | 2025-03-11 |
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