CN119597203A - Memory chip access control method and device, storage medium and electronic equipment - Google Patents

Abstract

The application discloses a memory chip access control method, a memory chip access control device, a storage medium and electronic equipment. The method comprises the steps of obtaining first delay time of a memory chip responding to an activation command when data access is conducted, wherein the first delay time is used for representing time intervals between sending the activation command to the memory chip and the memory chip responding to the activation command, obtaining second delay time of the memory chip responding to target commands except the activation command when the memory chip conducts data access, wherein the second delay time is used for representing time intervals between sending the target command to the memory chip and the memory chip responding to the target command, and adjusting first target timing parameters of the memory chip based on the first delay time and the second delay time, wherein the first target timing parameters are used for determining target time for accessing the memory chip. The application solves the technical problem that the time of the activation command is not adjusted when the row address is checked by the activation command in the related technology, so that the data read-write efficiency of the operating system is lower.

Description

Memory chip access control method and device, storage medium and electronic equipment

Technical Field

The present application relates to the field of computer technologies, and in particular, to a memory chip access control method, a memory chip access control device, a storage medium, and an electronic device.

Background

Currently, the widely used Dual data Rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, SDRAM, also known as Dynamic Random Access Memory, DRAM) standard is for DDR4 (Double data Rate) and DDR5 memories and provides a channel that can support Dual line memory module (Dual In-line Memory Module, DIMM) devices on both rising and falling clock edges. Typically, DDR5 DRAM supports failed row address repair. Two approaches are provided in DDR5, hard Post-packet repair (Hard Post PACKAGE REPAIR, HPPR) for permanent bank repair and Soft Post-packet repair (Soft Post PACKAGE REPAIR, SPPR) for temporary bank repair, respectively. DDR5 can correct at least one row address per BG (Bank Group) using hPPR, while DDR5 can repair one row address per BG using sPPR, where BG will not have more sPPR available resources if the hPPR resources of one BG are exhausted.

Because of the high density of DDR5, there may be some memory array units losing memory throughout the life cycle of the DIMM, for which reason related technicians have developed a register clock driver (Register Clock Driver, RCD) chip fail-row replacement technique that preserves some addresses as redundant addresses within each BG and never accesses them, and allows the RCD (REGISTERING CLOCK DRIVER, register clock driver) to record and report errors occurring in the DRAM chip, including fail-row addresses and other related information, in the RDIMM (REGISTERED DIMM, registered dual inline memory module) or LRDIMM (Load Reduced DIMM, low load dual inline memory module). Each time an ACT command occurs, the RCD looks up its wrong row table and replaces the redundant row address, and if the operating system has a patrol routine checking the memory capacity of each row address, it notifies the RCD to dynamically update the wrong row address table once some row missing memory capacity is detected.

However, for DDR5, the ACT command is a 2UI command, so the RCD must receive two UIs to check the row address. While the RCD must set a time number of 2 or more to affect all other commands, particularly the read-write command, considering the search time of the lookup row table, doing so reduces the efficiency of the entire DDR5 system.

In view of the above problems, no effective solution has been proposed at present.

Disclosure of Invention

The embodiment of the application provides a memory chip access control method, a memory chip access control device, a storage medium and electronic equipment, which at least solve the technical problem that the time of an activation command is not adjusted when the row address is checked by the activation command in the related technology, so that the data read-write efficiency of an operating system is lower.

According to one aspect of the embodiment of the application, a memory chip access control method is provided, which comprises the steps of obtaining a first delay time of a memory chip responding to an activation command when data access is performed, wherein the first delay time is used for representing a time interval between the transmission of the activation command to the memory chip and the response of the memory chip to the activation command, obtaining a second delay time of the memory chip responding to a target command except the activation command when the data access is performed, wherein the second delay time is used for representing a time interval between the transmission of the target command to the memory chip and the response of the memory chip to the target command, and adjusting a first target timing parameter of the memory chip based on the first delay time and the second delay time, wherein the first target timing parameter is used for determining a target time for accessing the memory chip.

Optionally, acquiring the first delay time of the memory chip responding to the activation command when the data access is performed comprises acquiring the first time of the central processing unit sending the activation command to the memory chip on the Dynamic Random Access Memory (DRAM) module, and acquiring the second time of the memory chip responding to the activation command, wherein the activation command is used for activating a target row in a target bank group on the memory chip, and determining the first delay time of the activation command based on the first time and the second time.

Optionally, acquiring the second delay time of the target command except the activation command when the memory chip performs data access comprises measuring the second delay time of the target command except the activation command when the memory chip performs data access through the adder, wherein the target command comprises at least one of a read request command, a write request command, a refresh command and a precharge command.

Optionally, the types of adders include at least one of carry select adders, carry-ripple adders, carry skip adders.

Optionally, the first target timing parameters include at least one of a first timing parameter for characterizing a time interval between sending a column read request command or a column write request command and a previous activate command, a second timing parameter for characterizing a time interval between selecting a row address by an activate command to executing a precharge command, a third timing parameter for characterizing a time interval between executing two activate commands for the same bank group, and a fourth timing parameter for characterizing a time interval between an activate command and a target command.

Optionally, the first target timing parameter is stored to the serial presence detection device and/or the serial presence detection hub device.

Optionally, after adjusting the first target timing parameter of the memory chip based on the first delay time and the second delay time, the method further comprises adjusting a second target timing parameter of the memory chip based on the first target timing parameter, wherein at least one of the second target timing parameters comprises a fifth timing parameter for representing a time interval for sending the activation command to different bank groups of the same logic level, a sixth timing parameter for representing a time interval for sending the activation command to the same bank group of different logic level, and a seventh interval time for representing a time interval for allowing for sending the activation command of more than 4 rows simultaneously.

According to another aspect of the embodiment of the application, a memory chip access control device is provided, which comprises a first acquisition module, a second acquisition module and an adjustment module, wherein the first acquisition module is used for acquiring a first delay time of a memory chip responding to an activation command when data access is performed, the first delay time is used for representing a time interval between sending the activation command to the memory chip and the memory chip responding to the activation command, the second acquisition module is used for acquiring a second delay time of the memory chip responding to a target command except the activation command when the memory chip performs the data access, the second delay time is used for representing a time interval between sending the target command to the memory chip and the memory chip responding to the target command, and the adjustment module is used for adjusting a first target timing parameter of the memory chip based on the first delay time and the second delay time, and the first target timing parameter is used for determining a target time for accessing the memory chip.

In the embodiment of the application, a first delay time of a response activation command of a memory chip when data access is performed is acquired, wherein the first delay time is used for representing a time interval between transmitting the activation command to the memory chip and the response activation command of the memory chip, a second delay time of a response target command except the activation command when the data access is performed by the memory chip is acquired, wherein the second delay time is used for representing a time interval between transmitting the target command to the memory chip and the response target command of the memory chip, and a first target timing parameter of the memory chip is adjusted based on the first delay time and the second delay time, wherein the first target timing parameter is used for determining the target time for accessing the memory chip. The timing parameters of the memory chip are adjusted according to the difference between the delay time of the activation command and the delay time of other commands, so that the purposes of improving the stability and reliability of the read-write data of the memory chip are achieved, data transmission errors and interference are avoided, the technical effect of improving the system efficiency is realized, and the technical problem that the time of the activation command is not adjusted when the row address is checked by the activation command in the related technology, so that the data read-write efficiency of an operating system is lower is solved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1 is a flow chart of an alternative memory chip access control method according to an embodiment of the application;

FIG. 2a is a timing diagram of an alternative timing parameter without a dedicated ACR delay setting in accordance with an embodiment of the present application;

FIG. 2b is a timing diagram of an alternative timing parameter for setting a dedicated ACR delay setting in accordance with an embodiment of the present application;

FIG. 3 is a schematic diagram of a computer system running a method for controlling read/write operations of a memory chip according to an embodiment of the application;

FIG. 4 is a schematic diagram of a computer system operated by another method for controlling read and write operations of a memory chip according to an embodiment of the application;

FIG. 5 is a schematic diagram of a computer system operated by another memory chip read/write operation control method according to an embodiment of the present application;

FIG. 6 is a schematic diagram of an alternative memory chip access control device according to an embodiment of the present application;

fig. 7 is a block diagram of a hardware architecture of an alternative computer terminal (or mobile device) for implementing a memory chip read/write operation control method according to an embodiment of the present application.

Detailed Description

In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

In addition, the related information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for presentation, analyzed data, etc.) related to the present application are information and data authorized by the user or sufficiently authorized by each party. For example, an interface is provided between the system and the relevant user or institution, before acquiring the relevant information, the system needs to send an acquisition request to the user or institution through the interface, and acquire the relevant information after receiving the consent information fed back by the user or institution.

In order to better understand the embodiments of the present application, technical terms related to the embodiments of the present application are explained as follows:

A register clock driver (Register Clock Driver, RCD) is a circuit or chip that is used to drive the clock signal in the register. Register clock drivers are commonly used in digital systems, particularly in central processing units and other processors. The RCD is responsible for providing a clock signal to synchronize and control the read and write operations of the registers. RCDs typically have multiple clock input ports that can receive clock signals from different sources. The RCD also provides a plurality of clock output ports for delivering clock signals to registers requiring clock signals. These output ports may be configured with different clock frequencies and phases as desired. In addition to providing clock signals, the register clock driver may also provide other functions such as clock division, clock delay, clock phase adjustment, etc. These functions may help optimize system performance and timing requirements. Register clock drivers play an important role in digital systems, ensuring synchronization and correctness of register operations. Proper selection and configuration of register clock drivers is critical to designing a high performance and reliable digital system.

A high bandwidth register clock driver (High Bandwidth Register Clock Driver, HBRCD) is a circuit for driving a high speed register clock signal. The register clock signal is used to synchronize the operation of data input and output to the registers, while the high bandwidth register clock driver is capable of providing a high speed, stable clock signal. The high bandwidth register clock driver typically includes one or more clock generators, a clock divider, and a clock buffer. The clock generator is used for generating a high-frequency clock signal, and the clock divider is used for dividing the high-frequency clock signal into lower frequencies so as to meet different application requirements. The clock buffer is used for amplifying and driving the clock signal so as to ensure that the clock signal can be accurately transmitted to the register. The design of the high bandwidth register clock driver takes into account the delay, jitter, and power consumption of signal transmission. HBRCD typically employ low-delay, low-jitter clock generators and buffers to ensure that clock signals can be accurately transferred to registers and that high-speed data input and output requirements can be met. In addition, the high-bandwidth register clock driver can reduce power consumption and improve performance by optimizing a circuit structure and adopting advanced process technology.

A Multi-register clock driver (Multi-Register Clock Driver, MRCD) is a circuit or chip for driving clock signals for a plurality of registers. MRCD are commonly used in synchronization circuits, such as register files in microprocessors or digital signal processors. The primary function of the multiple register clock driver is to provide a synchronized clock signal for each register to ensure that they operate within the same clock cycle. MRCD typically have multiple clock inputs and multiple clock outputs, and a clock signal may be distributed to multiple registers. The multiple register clock driver typically has the characteristics of 1. Clock distribution, in which one input clock signal can be distributed to multiple registers to ensure that they operate within the same clock cycle, 2. Clock delay, in which each register can be provided with an adjustable clock delay to meet timing requirements between different registers, 3. Clock frequency, in which different clock frequencies can be supported and different clock frequency divisions can be provided as needed, 4. Power noise filtering, typically has a power noise filtering function to reduce noise interference of the clock signal.

DIMM (Daul In-Line Memory Module, dual in-line memory Module) is a 64-bit computer memory of a local type capable of realizing rapid data transmission, and consists of a series of dynamic random access memory integrated circuits. The DIMM stores each data bit in a separate memory unit. DIMMs use a 64-bit data path because processors used in personal computers have a 64-bit data width, and thus DIMMs are commonly used in personal computers, workstations, printers, servers, and the like.

RDIMM (REGISTERED DIMM, registered dual in-line memory module) is a memory stripe with a register added for data transfer, which is located between the CPU and the memory granule to reduce the parallel transfer distance.

According to an embodiment of the present application, there is provided an embodiment of a memory chip access control method, it should be noted that the steps illustrated in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different from that herein.

Fig. 1 is a flow chart of an alternative memory chip access control method according to an embodiment of the present application, as shown in fig. 1, the method at least includes steps S102-S106, where:

step S102, a first delay time of the memory chip responding to the activation command when the memory chip accesses data is obtained.

The first delay time is used for representing a time interval between sending the activation command to the memory chip and responding the activation command by the memory chip.

In the technical solution provided in step S102, the memory chip refers to a memory unit in the DRAM module for storing data. The activate command is typically used to open a Row in a Bank (block) before accessing (referring to read and write operations) data, where the Bank is a two-dimensional memory matrix including rows and columns. In addition, the address signals issued simultaneously with the activate command may be used to determine the Bank Group, bank, row to be activated, a step called Row address strobe (Row Address Strobe, RAS).

In an alternative embodiment, in the technical solution provided in the step S102, the method may include obtaining a first time when the central processing unit sends an activation command to the memory chip on the DRAM module, and obtaining a second time when the memory chip responds to the activation command, where the activation command is used to activate a target row in a target bank group on the memory chip, and determining a first delay time of the activation command based on the first time and the second time.

In general, in order to buffer the memory pressure of the central processing unit (Central Processing Unit, CPU), the instructions or commands from the CPU are typically sent to the RCD for one clock cycle before being transferred from the RCD to the memory chip on the rising edge of the next clock cycle, which plays a mediating role. The main purpose of this is to keep the same memory speed even under the condition of large workload, and ensure the continuous stability of the system. Therefore, in the embodiment of the present application, the activation command from the CPU is received by the RCD first, and then the RCD communicates with the memory chip on the DRAM module to transmit the activation command, so that the first time when the CPU issues the activation command to the memory chip on the DRAM module can be obtained first, the second time when the memory chip responds to the activation command can be obtained, and the first delay time of the activation command can be determined according to the time difference between the first time and the second time.

Step S104, obtaining the second delay time of the memory chip responding to the target command except the activation command when the memory chip performs data access.

The second delay time is used for representing the time interval between sending the target command to the memory chip and the memory chip responding to the target command.

In the technical scheme provided in step S104, after the memory chip responds to the activation command, the memory chip may acquire the read-write command at the same time and send an address signal synchronously with the read-write command to determine the initial column address of burst transmission, which is called column address strobe (Column Address Strobe, CAS), so as to read and write data in a unit in the selected two-dimensional memory matrix in the Bank in row access and column access respectively. In addition, since a single Bank has only one SENSE AMPLIFIER (sense amp) to cache the contents of a single line, a Precharge command needs to be used to close the currently active line before accessing other different lines within the same Bank after a line is activated by the active command, where the line address cached in current SENSE AMPLIFIER is written back to the original address after the Precharge command is issued. Instead of directly using the Precharge command to close a line, an RDA (Read with Auto-Precharge) command or a WDA (WRITE WITH Auto-Precharge) command may also be used in the related art, so that the current line is automatically closed after the current transmission of a line is completed. Thus, target commands in embodiments of the present application include, but are not limited to, read request commands, write request commands, refresh commands, precharge commands, read and auto precharge commands, write and auto precharge commands.

The precharge is understood as an operation of preparing to open a new operation row with respect to a current operation row, and thus the operation is irregular, and the refresh is an operation of performing all rows at once in a fixed cycle to retain data of a memory bank that has not undergone overwriting.

In an alternative embodiment, in the solution provided in step S104, the method may include measuring, by the adder, a second delay time of the memory chip in response to the target command other than the activate command when the memory chip performs the data access.

In this embodiment, the delay time of each target command is measured by different types of high-speed adders, where the high-speed adders adopted in the embodiment of the present application include, but are not limited to, carry select adders, carry-skip adders, and the like, and the selection of a specific adder type may be determined in combination with an actual application scenario, and is not limited herein.

It should be noted that, the high-speed adders are all existing adders, and the design composition is disclosed by the related art, so that the description of the parts is not repeated in the present application.

Step S106, adjusting a first target timing parameter of the memory chip based on the first delay time and the second delay time, wherein the first target timing parameter is used for determining a target time for accessing the memory chip.

In the technical solution provided in step S106, the first target timing parameters include at least one of a first timing parameter for characterizing a time interval between sending a column read request command or a column write request command and a previous activate command, a second timing parameter for characterizing a time interval between selecting a row address by an activate command and executing a precharge command, a third timing parameter for characterizing a time interval between executing two activate commands for the same bank group, and a fourth timing parameter for characterizing a time interval between an activate command and a target command.

Specifically, the first timing parameter may be denoted as t _RCD (i.e., RAS to CASDelay), which refers to the RAS-to-CAS delay, where CAS and RAS together determine the addressing of the memory chip, and RAS (first activated after an access request) and CAS (activated after completion of RAS) are not consecutive, and there is a delay between these two operations, so this delay time may be denoted as the first timing parameter. The second timing parameter may be referred to as t _RAS (i.e., RAS ACTIVE TIME), which refers to the shortest period from the active to the precharge of the memory line. Generally, if the waiting period of t _RAS is too long, the performance of the operating system is reduced due to nonsensical waiting, and if the waiting period of t _RAS is too short, the activated row address is caused to enter the inactive state earlier, so that burst transmission of data cannot be completed due to lack of enough time, and thus, proper t _RAS plays a critical role for the performance of the operating system. The third timing parameter may be denoted as t _RC (i.e., row CYCLE TIME), which is the minimum time between two Row activation commands in the same Bank, or the time when a Row operation cycle is completed in one Bank. Typically, if t _RC is too long, this can result in reduced performance of the operating system due to meaningless latency, while if t _RC is too short, this can result in a new cycle being initiated before the activated row is fully charged, resulting in data loss and corruption. Likewise, the appropriate t _RC plays a vital role in the performance of the operating system. Finally, the fourth timing parameter may then be understood as timing information related to the timing between the activate command and the other commands.

In order to facilitate the direct use of the timing parameters described above, it is proposed in an embodiment of the present application that the first target timing parameters may also be stored to the serial presence detection device and/or the serial presence detection hub device.

The serial presence detection (SERIAL PRESENCE DETECT, SPD) is an 8 pin EEPROM (ELECTRICALLY ERASABLE PROGRAMMABLE ROM, electrically erasable programmable read only memory) chip, which is used to record many important information of the memory, such as the memory chip and parameters of module manufacturers, operating frequencies, operating voltages, speeds, capacities, voltages, row and column address bandwidths, etc., so that SPD information is generally written into the ROM chip by the memory module manufacturers according to the actual performance of the memory chip before shipment.

Generally, after the computer is started, the motherboard BIOS (Basis Input Output System, basic input/output system) will read the information in the SPD, and automatically configure the corresponding memory operation timing and control registers according to the parameter information, so as to fully play the performance of the memory bank.

Further, after adjusting the first target timing parameter of the memory chip, a second target timing parameter of the memory chip may be adjusted based on the first target timing parameter, wherein the second target timing parameter includes at least one of a fifth timing parameter for characterizing a time interval for sending an activate command to different banks of the same logic level, a sixth timing parameter for characterizing a time interval for sending an activate command to the same banks of different logic levels, and a seventh interval time for characterizing that an activate command of greater than 4 rows is allowed to be sent simultaneously.

Specifically, the fifth timing parameter may be denoted as t _{RRD_S} (i.e., row to Roe Delay Short), which represents the length of time interval that needs to be satisfied between activation commands when consecutive activation commands are issued to banks of different Bank groups. The sixth timing parameter may be denoted as t _{RRD_L} (i.e., row to Roe Delay Long), which indicates the length of time interval that needs to be satisfied between activation commands when consecutive activation commands are issued to a plurality of banks belonging to the same Bank Group. Finally, the fifth timing parameter may be denoted as t _FAW (i.e. Four Activate Window), which limits the window containing at most four activation commands, and only four activation commands may be issued for a period of time, where the activation commands need to satisfy the above-mentioned t _{RRD_S} and t _{RRD_L} on the one hand, and wait for the end window of t _FAW to be transmitted after transmitting the four activation commands on the other hand.

It should be noted that the method according to the embodiment of the present application may be applied to at least one of a register clock driver, a high-bandwidth register clock driver, or a multi-register clock driver.

For example, fig. 2a is a timing diagram of an optional timing parameter without setting a dedicated ACR delay setting according to an embodiment of the present application, fig. 2b is a timing diagram of an optional timing parameter with setting a dedicated ACR delay setting according to an embodiment of the present application, it is not difficult to find from fig. 2a and fig. 2b that the timing time of t _RCD、t_RAS、t_RC between the host interface and the DRAM module interface in fig. 2a is the same, the timing time of t _RCD、t_RAS、t_RC in fig. 2b is different, and it is assumed that the timing time of t _RCD、t_RAS、t_RC in fig. 2b is one period shorter than the timing time of each timing parameter in fig. 2a when the ACT delay is set to 2 and the normal delay is set to 1, in order to compensate for the influence of the dedicated ACT delay, the timing time of t _RCD、t_RAS、t_RC should be increased accordingly according to the method of the embodiment of the present application, thereby ensuring the operation efficiency of the system.

Based on the above-defined schemes in steps S102 to S106, it may be known that in an embodiment, a first delay time of the memory chip responding to the activation command when performing data access is obtained, where the first delay time is used to characterize a time interval between sending the activation command to the memory chip and the memory chip responding to the activation command, a second delay time of the memory chip responding to the target command other than the activation command when performing data access is obtained, where the second delay time is used to characterize a time interval between sending the target command to the memory chip and the memory chip responding to the target command, and a first target timing parameter of the memory chip is adjusted based on the first delay time and the second delay time, where the first target timing parameter is used to determine a target time of accessing the memory chip. The timing parameters of the memory chip are adjusted according to the difference between the delay time of the activation command and the delay time of other commands, so that the purposes of improving the stability and reliability of the read-write data of the memory chip are achieved, data transmission errors and interference are avoided, the technical effect of improving the system efficiency is realized, and the technical problem that the time of the activation command is not adjusted when the row address is checked by the activation command in the related technology, so that the data read-write efficiency of an operating system is lower is solved.

FIG. 3 is a schematic diagram of a computer system operating with a memory chip read/write operation control method according to an embodiment of the present application, as shown in FIG. 3, a computer system 960, including a host Central Processing Unit (CPU) 970, memory controllers (Memory Controller, MC) 980, and sub-channels of a Dual Inline Memory Module (DIMM) 300, where the DIMM may be a JEDEC standard DDR5. The DIMM includes two sub-channels. Each subchannel includes 20 dynamic random access memory chips (DRAMs) 341-345 and host data buses 301-305. Within the DIMM is a Registered Clock Driver (RCD) 330 that will be shared by the two sub-channels. The command/address bus 320 connects the MC and RCD. The serial presence detect EEPROM (SPD) or serial presence detect EEPROM and HUB function (spd_hub) 350 stores DRAM timing information and is accessible by the SMBUS.

FIG. 4 is a schematic diagram of a computer system operated by another memory chip read/write operation control method according to an embodiment of the present application, as shown in FIG. 4, the computer system 930 includes a host Central Processing Unit (CPU) 940, a Memory Controller (MC) 950, and subchannels of a DIMM 200, wherein the DIMM may be a JEDEC standard DDR5 High Bandwidth DIMM (HBDIMM) or a hybrid DIMM as defined in reference 8. The DIMM includes two sub-channels. Each sub-channel includes 20 or 18-DRAM chips 241-245, 5 high bandwidth data buffers (High Bandwidth Data Buffer, HBDB) 211-215, host data buses 201-205, and data buses 221-225 between HBDB and DRAM chips. Buses 221-225 run at half the data rate of buses 201-205. There is a high bandwidth registered clock driver (High Bandwidth Register Clock Drive, HBRCD) 230 in the DIMM that will be shared by the two sub-channels. Command/address bus 220 connects MC and HBRCD. The serial presence detect EEPROM (SPD) or serial presence detect EEPROM and HUB function (spd_hub) 250 stores DRAM timing information and is accessible by the SMBUS.

Fig. 5 is a schematic diagram of a computer system operated by another method for controlling read and write operations of a memory chip according to an embodiment of the present application, as shown in fig. 5, the computer system 900 includes a host Central Processing Unit (CPU) 910, a Memory Controller (MC) 920, and subchannels of a DDR5 multi rank dual inline memory module (Multiple Rank Dual Inline Memory Module, MRDIMM) 100. MRDIMM include two sub-channels. Each sub-channel includes 20x4 DRAM chips 141-145, 5 multi-way data buffers (Multi Data Buffer, MDB) 111-115, host data buses 101-105, and data buses 121-125 between the MDB and the DRAM chips. Buses 121-125 run at half the data rate of buses 101-105. In MRDIMM there is a Multiple Registration Clock Driver (MRCD) 130 that will be shared by both sub-channels. The serial presence detect EEPROM (SPD) or the serial presence detect EEPROM and HUB function (spd_hub) 150 stores DRAM timing information and can be accessed by the SMBUS.

In addition, the embodiment of the application also provides an embodiment of a memory chip access control device, and the device executes the memory chip access control method of the embodiment when running. Fig. 6 is a schematic structural diagram of an alternative memory chip access control device according to an embodiment of the present application, and as shown in fig. 6, the memory chip access control device includes at least a first obtaining module 61, a second obtaining module 62 and an adjusting module 63, where:

A first obtaining module 61, configured to obtain a first delay time of the memory chip responding to the activation command when performing data access, where the first delay time is used to characterize a time interval between sending the activation command to the memory chip and the memory chip responding to the activation command;

a second obtaining module 62, configured to obtain a second delay time for responding to the target command other than the activate command when the memory chip performs the data access, where the second delay time is used to characterize a time interval between sending the target command to the memory chip and the memory chip responding to the target command;

The adjusting module 63 is configured to adjust a first target timing parameter of the memory chip based on the first delay time and the second delay time, where the first target timing parameter is used to determine a target time for accessing the memory chip.

Note that each module in the memory chip access control device shown in fig. 6 may be a program module (for example, a set of program instructions for implementing a specific function), or may be a hardware module, and for the latter, it may be expressed in a form, but not limited to, that each module is expressed in a form of one processor, or the functions of each module are implemented by one processor.

Further, fig. 7 shows a block diagram of a hardware structure of a computer terminal (or mobile device) for implementing the memory chip read/write operation control method. As shown in fig. 7, the computer terminal 70 (or mobile device 70) may include one or more processors 702 (shown in the figures as 702a, 702 b..the term "702 n"), which processors 702 may include, but are not limited to, a processing means such as a microprocessor MCU or a programmable logic device FPGA, a memory 704 for storing data, and a transmission module 706 for communication functions. Among other things, a display, an input/output interface (I/O interface), a Universal Serial BUS (USB) port (which may be included as one of the ports of the BUS BUS), a network interface, a power supply, and/or a camera. It will be appreciated by those of ordinary skill in the art that the configuration shown in fig. 7 is merely illustrative and is not intended to limit the configuration of the electronic device described above. For example, the computer terminal 70 may also include more or fewer components than shown in FIG. 7, or have a different configuration than shown in FIG. 7.

It should be noted that the one or more processors 702 and/or other data processing circuits described above may be referred to generally herein as "data processing circuits. The data processing circuit may be embodied in whole or in part in software, hardware, firmware, or any other combination. Furthermore, the data processing circuitry may be a single stand-alone processing module, or incorporated, in whole or in part, into any of the other elements in the computer terminal 70 (or mobile device). As referred to in embodiments of the application, the data processing circuit acts as a processor control (e.g., selection of the path of the variable resistor termination connected to the interface).

The memory 704 may be used to store software programs and modules of application software, such as program instructions/data storage devices corresponding to the memory chip read/write operation control method in the embodiment of the present application, and the processor 702 executes the software programs and modules stored in the memory 704, thereby executing various functional applications and data processing, that is, implementing the memory chip read/write operation control method described above. Memory 704 may include high-speed random access memory, but may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 704 may further include memory located remotely from the processor 702, which may be connected to the computer terminal 70 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission module 706 is used to receive or transmit data via a network. The specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal 70. In one example, the transmission module 706 includes a network adapter (Network Interface Controller, NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission module 706 may be a Radio Frequency (RF) module for communicating with the internet wirelessly.

The display may be, for example, a touch screen type Liquid Crystal Display (LCD) that may enable a user to interact with a user interface of the computer terminal 70 (or mobile device).

It should be noted here that, in some alternative embodiments, the computer device (or the electronic device) shown in fig. 7 may include hardware elements (including circuits), software elements (including computer code stored on a computer readable medium), or a combination of both hardware elements and software elements. It should be noted that fig. 7 is only one example of a specific example, and is intended to illustrate the types of components that may be present in the computer device (or electronic device) described above.

It should be noted that, the electronic device shown in fig. 7 is used for executing the read-write operation control method of the memory chip shown in fig. 1, so the explanation of the execution method of the command is also applicable to the electronic device, and will not be repeated here.

According to an embodiment of the present application, there is also provided a nonvolatile storage medium in which a program is stored, wherein the device in which the nonvolatile storage medium is controlled to execute the memory chip access control method in embodiment 1 when the program runs.

Optionally, the device with the nonvolatile storage medium performs the following steps by running the program, wherein the first delay time of the memory chip responding to the activation command when performing data access is obtained, the first delay time is used for representing the time interval between sending the activation command to the memory chip and the memory chip responding to the activation command, the second delay time of the memory chip responding to the target command except the activation command when performing data access is obtained, the second delay time is used for representing the time interval between sending the target command to the memory chip and the memory chip responding to the target command, the first target timing parameter of the memory chip is adjusted based on the first delay time and the second delay time, and the first target timing parameter is used for determining the target time for accessing the memory chip

According to an embodiment of the present application, there is further provided an electronic device, where the electronic device includes one or more processors, and a memory for storing one or more programs, which when executed by the one or more processors, cause the one or more processors to implement a method for running the programs, where the programs are configured to execute the memory chip access control method in embodiment 1.

Optionally, the processor is configured to implement the steps of obtaining a first delay time of the memory chip responding to the activation command when the memory chip is subjected to data access, wherein the first delay time is used for representing a time interval between sending the activation command to the memory chip and the memory chip responding to the activation command, obtaining a second delay time of the memory chip responding to the target command except the activation command when the memory chip is subjected to data access, wherein the second delay time is used for representing a time interval between sending the target command to the memory chip and the memory chip responding to the target command, and adjusting a first target timing parameter of the memory chip based on the first delay time and the second delay time, wherein the first target timing parameter is used for determining a target time for accessing the memory chip.

The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed technology may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of units may be a logic function division, and there may be another division manner in actual implementation, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be essentially or a part contributing to the related art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of the embodiments of the present application. The storage medium includes a U disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, etc. which can store the program code.

The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application, which are intended to be comprehended within the scope of the present application.

Claims (10)

1. A memory chip access control method, comprising: Acquire a first delay time of the memory chip responding to an activation command when performing data access, wherein the first delay time is used to represent a time interval between sending the activation command to the memory chip and the memory chip responding to the activation command; Acquire a second delay time for the memory chip to respond to a target command other than the activation command when performing data access, wherein the second delay time is used to represent a time interval between sending the target command to the memory chip and the memory chip responding to the target command; A first target timing parameter of the memory chip is adjusted based on the first delay time and the second delay time, wherein the first target timing parameter is used to determine a target time for accessing the memory chip. 2. The method according to claim 1, wherein obtaining a first delay time of the memory chip responding to an activation command when performing data access comprises: Acquire a first time when a central processing unit sends an activation command to a memory chip on a dynamic random access memory DRAM module, and acquire a second time when the memory chip responds to the activation command, wherein the activation command is used to activate a target row in a target bank group on the memory chip; A first delay time of the activation command is determined based on the first time and the second time. 3. The method according to claim 1, wherein obtaining a second delay time of the memory chip responding to a target command other than the activation command when accessing data comprises: The second delay time of the memory chip responding to the target command other than the activation command when accessing data is measured by an adder, wherein the target command includes at least one of the following: a read request command, a write request command, a refresh command, and a precharge command. 4. The method according to claim 3, characterized in that the type of the adder includes at least one of the following: Carry select adder, ripple carry adder, carry skip adder. 5. The method according to claim 3, characterized in that: The first target timing parameter includes at least one of the following: a first timing parameter used to characterize the time interval between sending a column read request command or a column write request command and the previous activation command, a second timing parameter used to characterize the time interval between selecting a row address through the activation command and executing the precharge command, a third timing parameter used to characterize the time interval between executing two activation commands on the same bank group, and a fourth timing parameter used to characterize the time interval between the activation command and the target command. 6 . The method according to claim 1 , wherein the first target timing parameter is stored in a SPI device and/or a SPI hub device. 7. The method according to claim 1, characterized in that after adjusting a first target timing parameter of the memory chip based on the first delay time and the second delay time, the method further comprises: Adjust the second target timing parameters of the memory chip based on the first target timing parameters, wherein the second target timing parameters include at least one of the following: a fifth timing parameter for characterizing the time interval for sending activation commands to different bank groups at the same logical level, a sixth timing parameter for characterizing the time interval for sending activation commands to the same bank groups at different logical levels, and a seventh interval time for characterizing the permission to send activation commands for more than 4 rows at the same time. 8. A memory chip access control device, comprising: A first acquisition module, used for acquiring a first delay time of the memory chip responding to an activation command when performing data access, wherein the first delay time is used for representing a time interval between sending the activation command to the memory chip and the memory chip responding to the activation command; A second acquisition module, used for acquiring a second delay time for the memory chip to respond to a target command other than the activation command when performing data access, wherein the second delay time is used to represent a time interval between sending the target command to the memory chip and the memory chip responding to the target command; An adjustment module is used to adjust a first target timing parameter of the memory chip based on the first delay time and the second delay time, wherein the first target timing parameter is used to determine a target time for accessing the memory chip. 9. A non-volatile storage medium, characterized in that a computer program is stored in the non-volatile storage medium, wherein a device where the non-volatile storage medium is located executes the memory chip access control method described in any one of claims 1 to 7 by running the computer program. 10. An electronic device, comprising: a memory and a processor, wherein the processor is used to run a program stored in the memory, wherein the memory chip access control method according to any one of claims 1 to 7 is executed when the program is run.