CN119580816B

CN119580816B - A memory testing method, system, device and storage medium

Info

Publication number: CN119580816B
Application number: CN202510113142.7A
Authority: CN
Inventors: 杨祖放
Original assignee: Shenzhen Jingcun Technology Co ltd
Current assignee: Shenzhen Jingcun Technology Co ltd
Priority date: 2025-01-24
Filing date: 2025-01-24
Publication date: 2025-05-13
Anticipated expiration: 2045-01-24
Also published as: CN119580816A

Abstract

The present invention discloses a memory testing method, system, device and storage medium, the method comprising: obtaining an initial memory after initializing the memory to be tested; repeatedly writing test data into the storage unit of the nth row and the mth column of the initial memory according to a preset number of writes, and performing data verification on other storage units of the nth row to obtain a verification result each time the test data is written; and configuring the initial memory as a good memory or a faulty memory according to the verification result. By comprehensively and specifically detecting the data changes of other storage units in the same row when writing data to a certain storage unit in the entire memory, the data jump caused by hardware failure is discovered in advance, thereby screening out defective products, ensuring the quality of the memory product finally delivered for use, and reducing the subsequent troubleshooting and maintenance costs caused by hardware problems.

Description

Memory testing method, system, device and storage medium

Technical Field

The present invention relates to the field of data processing technologies, and in particular, to a method, a system, an apparatus, and a storage medium for testing a memory.

Background

At present, when testing a produced memory, a read-write test is usually performed on a target storage location, so as to test the read-write performance of the target storage location of the memory.

The data jump caused by the hardware problem of the memory cannot be tested, so that the hardware problem of the produced memory is difficult to detect, and the memory has a large number of defective products.

Disclosure of Invention

Accordingly, an object of the embodiments of the present invention is to provide a method, a system, an apparatus, and a storage medium for testing a memory, which can test data jump caused by a hardware problem of the memory, find the memory with the hardware problem, and reduce defective products of the memory.

In a first aspect, an embodiment of the present invention provides a memory testing method, including:

Initializing a memory to be tested to obtain an initial memory, wherein data of all storage units in the initial memory are initialized to preset data;

repeatedly writing test data into the storage units of the nth row and the mth column of the initial memory according to preset writing times, and carrying out data verification on other storage units of the nth row when the test data are written each time to obtain a verification result, wherein N and M are positive integers which are larger than or equal to 1, N is smaller than or equal to the maximum line number N of the storage units, and M is smaller than or equal to the maximum column number M of the storage units;

If the verification result indicates that the storage data of the other storage units of the nth row are equal to the preset data, configuring the storage units of the nth row and the mth column as good units, otherwise configuring the storage units of the nth row and the mth column as fault units;

and under the condition that all the storage units in the initial storage are not fault units, configuring the initial storage as good-quality storage, otherwise configuring the initial storage as fault storage.

In some alternative embodiments, after the configuring the storage units of the nth row and the mth column as the failed units, the method further includes:

Acquiring the memory unit with data jump in the nth row;

the storage units of the nth row and the mth column are associated with the storage units with data jump to obtain a hardware association group;

detecting a circuit inside the hardware association group to obtain a detection result;

and determining the hardware fault type of the hardware association group according to the detection result.

In some optional embodiments, the determining the hardware fault type of the hardware association group according to the detection result includes:

Under the condition that the detection result represents that a circuit inside the hardware association group is short-circuited or broken, configuring the hardware fault type as a circuit fault;

and under the condition that the detection result indicates that the circuit inside the hardware association group is not short-circuited or broken, configuring the hardware fault type as a stability fault.

In some alternative embodiments, the method further comprises:

Under the condition that the hardware fault type is configured as the stability fault, replacing a first storage address of a standby unit in the initial memory with a second storage address of the storage unit with the data jump, and deleting the storage address of the storage unit with the data jump;

and under the condition that the hardware fault type is configured as a line fault, acquiring a line image of the hardware association group through a scanning electron microscope, determining a fault position according to the line image, and repairing the line at the fault position.

In some alternative embodiments, the setting of the preset number of writing times includes:

Acquiring the historical write-in times of the test data when a preset number of tested memories in the same batch detect a fault unit;

converting the historical writing times of the measured memories with preset quantity into a coordinate system to obtain a coordinate point set;

Acquiring a coordinate neighborhood of each coordinate point in the coordinate point set;

Calculating the average write-in times of each coordinate neighborhood, wherein the average write-in times represent the average value of the write-in times represented by other coordinate points in the coordinate neighborhood;

Calculating according to the average write-in times to obtain a standard deviation;

Determining a deviation coordinate point according to the average write-in times, the standard deviation and a preset standard deviation multiple;

deleting the deviation coordinate points to obtain a plurality of standard coordinate points;

Linearly fitting the standard coordinate points to obtain a fitting curve;

And configuring the write-in times corresponding to the fitting curve as the preset write-in times.

In some optional embodiments, the repeatedly writing test data into the memory cells of the nth row and the mth column of the initial memory according to a preset number of writing times includes:

Acquiring the storage capacity of the storage units of the nth row and the mth column, wherein the storage capacity represents the maximum data storage capacity;

repeatedly writing the test data into the storage units of the nth row and the mth column of the initial memory at preset writing times under the condition that the data volume of the test data is smaller than or equal to the storage capacity;

And under the condition that the data volume of the test data is larger than the storage capacity, splitting the test data into first data and second data, repeatedly writing the first data into the storage units of the nth row and the mth column of the initial memory with preset writing times, wherein the data volume of the first data is smaller than or equal to the storage capacity.

In some optional embodiments, the determining the offset coordinate point according to the average write times, the standard deviation, and a preset standard deviation multiple includes:

obtaining deviation times according to the standard deviation and the preset standard deviation multiple;

Acquiring the average write-in times corresponding to each point of the coordinate point set;

And configuring the point with the average writing times larger than the deviation times as the deviation coordinate point.

In a second aspect, an embodiment of the present invention provides a memory test system, including:

The first module is used for initializing the memory to be tested to obtain an initial memory, and the data of all storage units in the initial memory are initialized to preset data;

The second module is used for repeatedly writing test data into the storage units of the nth row and the mth column of the initial memory according to preset writing times, and carrying out data verification on other storage units of the nth row when the test data are written each time to obtain a verification result, wherein N and M are positive integers which are larger than or equal to 1, N is smaller than or equal to the maximum number N of the storage units, and M is smaller than or equal to the maximum number M of the storage units;

A third module, configured to configure the storage units of the nth row and the mth column as good units when the verification result indicates that the storage data of the other storage units of the nth row is equal to the preset data, otherwise configure the storage units of the nth row and the mth column as faulty units;

And a fourth module, configured to configure the initial memory as a good memory if all the storage units in the initial memory are not failure units, otherwise configure the initial memory as a failure memory.

In a third aspect, an embodiment of the present invention provides a memory test device applied to a smart card, where the device includes:

At least one processor;

at least one memory for storing at least one program;

The at least one program, when executed by the at least one processor, causes the at least one processor to implement the method as described above.

In a fourth aspect, embodiments of the present invention provide a computer readable storage medium having stored therein a processor executable program for performing the method as described above when executed by a processor.

The embodiment of the application provides a memory testing method, which comprises the following steps of initializing a memory to be tested to obtain an initial memory, repeatedly writing test data into the memory cells of an nth row and an mth column of the initial memory according to preset writing times, carrying out data verification on other memory cells of the nth row when the test data are written each time to obtain a verification result, wherein N and M are positive integers which are larger than or equal to 1, N is smaller than or equal to the maximum number N of the memory cells, M is smaller than or equal to the maximum number M of the memory cells, configuring the memory cells of the nth row and the mth column as good memory cells under the condition that the verification result represents that the memory data of the other memory cells of the nth row are equal to the preset data, otherwise configuring the memory cells of the nth row and the mth column as fault cells, configuring all the memory cells in the initial memory as good memory cells under the condition that all the memory cells of the nth row are not fault cells, and configuring the memory as good memory cells of the initial memory under the condition that all the memory cells of the nth row are not fault cells, otherwise configuring the initial memory as good memory. By implementing the technical means, defective products with hardware problems in the memory can be found. The method avoids serious problems such as data errors, crashes and the like caused by the fact that a memory product with hardware problems is put into use, and influences the stability and the reliability of the whole equipment or the system. The application can effectively make up the defects of the existing test method, and can detect the data change of one storage unit in the whole memory in the same row in a comprehensive and targeted way when writing data, and discover the data jump condition caused by hardware faults in advance, thereby screening out defective products, guaranteeing the quality of the memory products which are finally delivered and used, and reducing the subsequent fault investigation and maintenance cost caused by hardware problems.

Drawings

FIG. 1 is a flowchart illustrating steps of a memory testing method according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a memory cell of the memory according to an embodiment of the present invention;

FIG. 3 is a block diagram of a memory test system according to an embodiment of the present invention;

fig. 4 is a block diagram of a memory testing device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

It should be noted that although functional block division is performed in a device diagram and a logic sequence is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart. The terms first, second and the like in the description, in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

The embodiment of the invention provides a memory testing method, which comprises the steps of initializing a memory to be tested to obtain initial memory, initializing data of all storage units in the initial memory to preset data, repeatedly writing test data into the storage units of an nth row and an mth column of the initial memory according to preset writing times, carrying out data verification on other storage units of the nth row when the test data are written each time to obtain a verification result, wherein N and M are positive integers which are larger than or equal to 1, N is smaller than or equal to the maximum number N of the storage units, M is smaller than or equal to the maximum number M of the storage units, configuring the storage units of the nth row and the mth column as good units when the verification result represents that the storage data of the other storage units of the nth row are equal to the preset data, otherwise configuring the storage units of the nth row and the mth column as faulty units, and configuring the initial memory as good units when all the storage units in the initial memory are not faulty units, otherwise configuring the initial memory as good memories. In the technical scheme of the embodiment, when one storage unit in the whole memory writes data, the data change of other storage units in the same row is detected, so that the data jump caused by the hardware problem of the memory can be tested, the memory with the hardware problem can be found, and the defective products of the memory are reduced.

Embodiments of the present invention will be further described below with reference to the accompanying drawings.

As shown in fig. 1, an embodiment of the present invention provides a memory testing method, which includes the following steps.

S100, initializing a memory to be tested to obtain an initial memory, wherein data of all storage units in the initial memory are initialized to preset data.

Specifically, before the memory to be tested starts to be tested, all memory cells of the whole memory to be tested are fully written with preset data, and a unified initial state is provided for subsequent targeted writing and detection. By writing the preset data, each memory cell in the memory can have an initial set value, so that the change condition of the data of other memory cells under the specific writing operation can be conveniently observed, namely, after the writing operation is carried out on the memory cell of the target address, if the data of the memory cells of other addresses of the same row are changed, the abnormal change can be easily found compared with the preset uniform initial value, thereby judging whether the data jump caused by the hardware problem exists or not more accurately, and when new data is written into the target address, if the data of other addresses of the same row are changed, the data jump caused by the hardware problem can mean that crosstalk or other hardware problems such as line short circuit, signal interference and the like exist among the memory cells, and the problem is difficult to find in the traditional test method for writing the data only aiming at the target position. The specific preset data may be, for example, a simple numerical mode such as "0" or "1" that is set to be the same as or different from the preset data written in each storage unit, and the specific setting is not limited herein.

And S200, repeatedly writing test data into the storage units of the nth row and the mth column of the initial memory according to preset writing times, and carrying out data verification on other storage units of the nth row when the test data are written each time to obtain a verification result, wherein N and M are positive integers which are larger than or equal to 1, N is smaller than or equal to the maximum number N of the storage units, and M is smaller than or equal to the maximum number M of the storage units.

Specifically, referring to fig. 2, test data is written into the memory cells of the nth row and the mth column designated in the initial memory for a plurality of times according to the preset writing times, that is, the preset writing times, wherein the nth row represents any row number between the maximum row number N and the minimum row number 1 of the memory cells, and the mth column represents any column number between the maximum column number M and the minimum column number 1 of the memory cells. It should be noted that the preset number of writing times is usually determined based on past experience, test standard or requirement for fully detecting the performance of the memory, for example, in order to fully simulate the data writing scene frequently occurring in actual use, a relatively large number of writing times, such as hundreds of thousands or even millions, is set, so as to fully test whether the data of other memory cells in the same row of the memory cell jump under repeated writing operations. In the physical structure of the memory, the memory units in different rows and columns are respectively connected with each other in a circuit connection and correlation mode, and the memory units in the same row are in circuit correlation. And specifically initializing all storage units of the memory to perform test data writing with preset writing times, detecting whether data jump occurs to other storage units in the same row with each storage unit when each storage unit performs test data writing, and analyzing the mutual influence condition among the storage units.

In some optional embodiments, after the storage units in the nth row and the mth column are configured as fault units, the method further includes obtaining the storage unit in the nth row, which generates data jump, associating the storage unit in the nth row and the mth column with the storage unit in which generates data jump to obtain a hardware association group, detecting a circuit inside the hardware association group to obtain a detection result, and determining a hardware fault type of the hardware association group according to the detection result.

Specifically, each time test data is written to a specified memory cell of an nth row and an mth column, data of other memory cells of the nth row are verified at the same time. This is because memory cells in the same row often share portions of the circuit lines within the memory, with potential interactions between them. For example, when writing to a target memory cell, if there is a hardware problem such as a short circuit or signal disturbance on a line, abnormal changes in data of other memory cells in the same row are likely to occur. And judging whether the data of other storage units in the same row change or not through a specific verification algorithm or comparison mechanism, and recording the judgment result as a verification result. The way of checking may be simply comparing whether the current data of the memory cell is consistent with the known data (or preset data) after the last write operation, or using a more complex check code (e.g., parity check, CRC check, etc.) to check the integrity and accuracy of the data. Therefore, a hardware association group is obtained by associating the memory unit with the data jump, and whether the circuit between the hardware association groups is short-circuited, broken-circuit or not is detected, so that the corresponding hardware fault type is generated, namely, the hardware fault exists between the hardware association groups is obtained through the hardware fault type, and the subsequent fault processing is carried out, so that the fault is eliminated, the yield of the memory is improved, and the waste and the increase of the production cost caused by directly discarding the memory are avoided.

In some optional embodiments, the determining the hardware fault type of the hardware association group according to the detection result includes configuring the hardware fault type as a line fault when the detection result indicates that a line inside the hardware association group is short-circuited or broken, and configuring the hardware fault type as a stability fault when the detection result indicates that the line inside the hardware association group is not short-circuited or broken.

Specifically, when the detection result shows that a short circuit or a broken circuit occurs in a line inside the hardware association group, the hardware fault type is determined as a line fault. The short circuit means that the abnormal condition of direct conduction occurs between the non-conducting lines, which causes the problems of abnormal increase of current, signal interference and the like, and the disconnection is that the lines are interrupted, so that the signals cannot be normally transmitted, and the data read-write operation of the related memory cells is affected. Whether short or open indicates a hardware problem at the line level and is therefore classified as a line fault.

If the detection result shows that the circuit inside the hardware association group is not short-circuited or broken, but other data abnormal conditions occur, for example, the storage unit with data jump in the 3 rd row is the storage unit A, the storage unit with test data writing in the 3 rd row is the storage unit B, and the phenomenon that the data cannot be stably stored due to the data jump of the storage unit A frequently occurs in the normal reading and writing process of the storage unit B, the problem that the circuit connection between the storage unit A and the storage unit B is not caused is described, but the storage unit A or the whole hardware association group has defects in terms of stability, and the hardware fault type is configured as a stability fault in the case. The failure is caused by the quality problem of the storage unit, imperfect storage control mechanism, external interference and other factors, so that the stability of data storage and reading and writing is affected.

Through the definite fault type configuration mode, the root cause of hardware faults can be more accurately positioned. Has important guiding significance for the subsequent links of maintenance, improvement, quality control and the like. If the storage unit is determined to be in a stable fault, the maintenance personnel can find out reasons from factors affecting stability such as performance of the storage unit, storage control logic, electromagnetic interference protection and the like, and efficiency of fault detection and solution is improved.

In some alternative embodiments, the method further comprises the steps of replacing a first storage address of a standby unit in the initial memory with a second storage address of the storage unit with data jump, deleting the storage address of the storage unit with data jump under the condition that the hardware fault type is configured as the stability fault, acquiring a line image of the hardware association group through a scanning electron microscope under the condition that the hardware fault type is configured as the line fault, determining a fault position according to the line image, and repairing the line at the fault position.

Specifically, when the hardware fault type is configured as a stability fault, it means that the data storage stability of the storage unit itself is problematic, and the abnormal situation such as data jump is represented. At this time, replacing the first memory address of the spare unit in the initial memory with the second memory address of the memory unit with data jump is a strategy for ensuring the normal overall function of the memory through redundancy design. The standby unit is originally in an inactive state and is used for replacing a problematic storage unit when the fault occurs, so that the storage can continuously and stably store and read and write data, and the influence on the whole storage caused by the instability of the individual storage units is reduced as much as possible. Specifically, the second storage address of the storage unit with the data jump is obtained first, then the first storage address corresponding to the standby unit is configured to the logic position of the storage unit corresponding to the original second storage address in the whole storage system through the control logic of hardware, so that the subsequent data read-write operation can correctly point to the replaced standby unit, seamless connection is realized, and the normal processing flow of the data is ensured not to be interfered. After the replacement of the memory cell is completed, the memory address of the memory cell with the data jump is deleted, and this step is mainly used to avoid the system from continuously attempting to operate the memory cell with the stability problem, so as to prevent the occurrence of data errors or interference with the operation of other normal memory cells. By removing the memory address from the memory management system, the problematic memory cells are logically isolated, further ensuring the overall stability and reliability of the memory.

Scanning Electron Microscope (SEM) has high resolution imaging capability, and can clearly show microstructure, morphology and connection condition of internal circuits of the hardware association group. When the hardware fault type is determined to be a line fault, the line image of the hardware association group is acquired through SEM, so that whether the line is damaged in a physical layer or not can be detected, such as the conditions of breakage of the line, abnormal connection at a short circuit point, corrosion of the surface of the line and the like, and a reliable basis is provided for accurately determining the fault position. In the scanning electron microscope detection, the hardware association group sample containing the fault line is properly prepared to meet the observation requirement of the SEM, for example, necessary cleaning, fixing and other treatments are carried out to ensure that the hardware association group sample can be clearly imaged under the microscope. The sample is then placed on a sample stage of a scanning electron microscope, and high quality line images are acquired by adjusting scanning parameters of the electron beam, such as acceleration voltage, scanning range, etc. And detecting the integrity and the connection state of the circuit according to the obtained image, and finding out abnormal characteristics related to faults from the detected image.

And analyzing and judging the position of the line fault by using upper computer equipment connected with the scanning electron microscope according to the line image acquired by the scanning electron microscope. For example, if a significant trace of break appears in the middle of a certain section of line in the image, this location is the open fault point, and if it is found that there is an excess conductive material between two lines that are not connected to form a short circuit path, this is the short circuit fault point. The accurate determination of the fault location is a key precondition for effective repair subsequently.

And (3) line repair, namely adopting corresponding line repair means aiming at the determined fault position. For the disconnection problem, the disconnected lines can be reconnected by using technologies such as micro-welding, metal wire bridging and the like, and if the short circuit fault occurs, the excessive conductive substances at the short circuit point need to be carefully removed, so that the normal insulating state between the lines is recovered. The repair is automatically performed through specific repair equipment, in the repair process, the repair specification of the precise electronic circuit is followed, the repaired circuit can meet the requirements of normal operation of the memory in the aspects of electrical performance, mechanical stability and the like, and meanwhile, new fault hidden danger caused by repair operation is avoided.

In some optional embodiments, the setting of the preset writing times includes obtaining historical writing times of the test data when a fault unit is detected in a preset number of tested memories in the same batch, converting the historical writing times of the preset number of tested memories to a coordinate system to obtain a coordinate point set, obtaining a coordinate neighborhood of each coordinate point in the coordinate point set, calculating average writing times of each coordinate neighborhood, wherein the average writing times represent an average value of writing times represented by other coordinate points in the coordinate neighborhood, calculating to obtain a standard deviation according to the average writing times, determining a deviation coordinate point according to the average writing times, the standard deviation and a preset standard deviation multiple, deleting the deviation coordinate point to obtain a plurality of standard coordinate points, linearly fitting the standard coordinate points to obtain a fitting curve, and configuring the preset writing times corresponding to the fitting curve.

In some optional embodiments, the determining the offset coordinate point according to the average writing frequency, the standard deviation and the preset standard deviation multiple includes obtaining the offset frequency according to the standard deviation and the preset standard deviation multiple, obtaining the average writing frequency corresponding to each point of the coordinate point set, and configuring the point with the average writing frequency greater than the offset frequency as the offset coordinate point.

Specifically, when analyzing the tested memories in the same batch, knowing the historical write-in times of the test data when each tested memory detects the fault unit can provide basic data for the follow-up exploration of the overall performance, the fault occurrence rule and the like of the batch of memories. The historical write times reflect write times which can be born by different individual memories when faults occur in an actual test, the different write times indicate that differences exist among the memories in terms of quality, stability and the like, memories in the same batch have similar quality and stability, the historical write times of test data are detected when a tested memory detects a fault unit, therefore, the write times, namely preset write times, of other memories in the same batch are determined, the test time is prolonged due to the fact that excessive write times are avoided, and the test efficiency is improved. The data of the historical writing times are converted into a coordinate system to form a coordinate point set, so that abstract data are presented in an intuitive geometric form, and the subsequent analysis and mining of internal rules between the data are facilitated by using a mathematical method. In this coordinate system, the storage unit of each tested memory can be generally regarded as an independent coordinate point (the storage unit generates data jump when writing test data into other storage units in the same row, and the writing times of the corresponding test data when the data jump occurs are the historical writing times of the storage unit), the abscissa and the ordinate of the independent coordinate point can be set according to specific analysis requirements, for example, the abscissa is the number or other identification information of the storage unit in the memory, and the ordinate is the corresponding historical writing times. According to the selected coordinate system rule, the historical writing times corresponding to a plurality of storage units of each measured memory are in one-to-one correspondence with corresponding identification information, and are converted into specific points on a coordinate plane, and a plurality of the points jointly form a coordinate point set.

The coordinate neighborhood of each coordinate point is determined by considering that in the data analysis, the data around a certain data point often has certain relevance or similarity with the data, and the data situation around each coordinate point can be focused by defining the coordinate neighborhood, so that the local data characteristics and the change trend are analyzed, and the local abnormal situation or rule in the data can be found. The range of the coordinate neighborhood is determined based on a distance metric (e.g., euclidean distance, etc.). For each coordinate point in the coordinate system, a neighborhood range is defined according to a preset distance threshold (for example, a circular area with a certain fixed length as a radius or a certain rectangular range is defined), and other coordinate points falling in the range form a coordinate neighborhood of the coordinate point. The average write-in times of each coordinate neighborhood is calculated, namely the write-in times represented by all relevant coordinate points in the coordinate neighborhood are comprehensively considered, an average value is used for representing the approximate write-in times level when the memory in the local area fails, and the average value can smooth out possible fluctuation or error of individual data points in the local area and can reflect the write-in times characteristic with certain commonality. And summing the writing times corresponding to all the coordinate points in the coordinate neighborhood, and dividing the sum by the number of the coordinate points in the coordinate neighborhood to obtain the average writing times of the coordinate neighborhood.

The standard deviation is an important statistical indicator that measures the degree of dispersion of a set of data. By calculating the standard deviation of the average writing times of each coordinate neighborhood, the distribution dispersion condition of the average writing times in the whole can be known, namely the difference of the average writing times among different coordinate neighborhood is reflected. The larger standard deviation means that the data distribution is more scattered, the write-in times of memories in different areas are larger when faults occur, and the smaller standard deviation means that the data is relatively concentrated, and the conditions of the areas are similar. According to a standard deviation calculation formula in statistics, calculating the average writing times of all coordinate neighborhoods, firstly calculating the square of the difference value between each average writing time and the average value of all average writing times, summing the square values, dividing the sum by the number of the coordinate neighborhoods (or adjusting according to specific freedom degree requirements), and finally taking the square root to obtain the standard deviation.

And determining deviation coordinate points according to the average write-in times, the standard deviation and the preset standard deviation multiple, and aiming at finding out data points which are obviously inconsistent with the overall data distribution rule and have larger deviation degree. These off-coordinate points may be due to anomalies during testing, special defects in individual memories, or other contingencies, whose presence can interfere with accurate knowledge of the overall data law, so they need to be identified and culled. Coordinate points whose difference from the average number of writing exceeds the preset standard deviation times by the standard deviation are determined as deviating from the coordinate points by setting a reasonable preset standard deviation times (for example, 2 times, 3 times standard deviation, etc. according to experience or the requirement of data analysis).

The plurality of standard coordinate points obtained after the deviation coordinate points are deleted can more accurately reflect the actual distribution rule and the internal trend of the test data writing times when the batch of memories fail. And (3) carrying out linear fitting on the standard coordinate points, namely finding a straight line which can best fit the distribution trend of the data points, so that the standard coordinate points are distributed near the straight line as uniformly as possible, and therefore, the general rule of the batch of memories is represented by the fitting curve, and a scientific basis is provided for the follow-up configuration preset writing times. And fitting the standard coordinate points by using a mathematical linear fitting algorithm (such as a least square method and the like) to obtain a fitting curve. The write-in times corresponding to the fitting curve are configured to be preset write-in times, which means that when the same batch of unmeasured memories or similar memories are tested later, the operation can be performed according to the representative write-in times analyzed and summarized from the historical data, so that the testing process is more scientific and reasonable, the actual performance characteristics of the batch of memories are more met, the potential fault condition can be detected more accurately, and the testing efficiency and quality are improved.

In some alternative embodiments, the step of repeatedly writing test data into the storage units of the nth row and the mth column of the initial memory according to the preset writing times comprises the steps of obtaining the storage capacity of the storage units of the nth row and the mth column, wherein the storage capacity represents the maximum data storage capacity, repeatedly writing the test data into the storage units of the nth row and the mth column of the initial memory according to the preset writing times when the data amount of the test data is smaller than or equal to the storage capacity, and splitting the test data into first data and second data when the data amount of the test data is larger than the storage capacity, and repeatedly writing the first data into the storage units of the nth row and the mth column of the initial memory according to the preset writing times, wherein the data amount of the first data is smaller than or equal to the storage capacity.

Specifically, when the data amount of the test data is smaller than or equal to the storage capacity of the storage unit, it means that the test data can be stored in the designated n-th row and m-th column of storage units in one go. At this time, the test data is repeatedly written into the memory unit according to the preset writing times, so that a data writing scene of repeatedly and stably writing the memory unit in a normal memory capacity range can be simulated, the performance of other memory units in the same row under repeated operation can be conveniently observed, for example, whether hardware association problems such as data jump and memory errors occur or not can be conveniently observed, and further the quality and stability of the memory can be effectively detected. For example, the storage capacity of a certain storage unit is 1024 bytes, the data volume of the test data is 512 bytes, under the condition that the preset writing times are set to 10 ten thousand times, the test data of the 512 bytes can be directly written into the storage unit repeatedly for 10 ten thousand times according to the rule, the data written in each time can be completely stored in the storage unit, and then whether the hidden trouble exists or not is judged through the subsequent operations such as data verification on other storage units in the same row.

When the data volume of the test data is larger than the storage capacity of the storage unit, if the whole test data is directly tried to be written, the data cannot be stored completely, the data of the exceeding part can be lost or cover the data of other storage areas, the data integrity of the whole storage is damaged, and the follow-up fault detection is not easy to accurately perform. Therefore, it is necessary to split the test data into the first data and the second data to ensure that the amount of data written each time is within an acceptable range for the memory cell.

And (3) writing the first data, namely repeatedly writing the split first data with the data quantity smaller than or equal to the storage capacity into the storage units of the nth row and the mth column of the initial memory according to preset writing times. The purpose of this is also to simulate the processing situation of the memory cells when the memory cells are in large data volume in actual use, and observe the response of the memory cells in the process of writing many times and whether the abnormal phenomena such as the data change of other memory cells in the same row can be caused, so as to detect the hardware relevance and stability of the memory. For example, the total amount of the test data is 2048 bytes, and the storage capacity of the storage unit is 1024 bytes, so that the test data can be split into two 1024 bytes of data (first data and second data), the first data is selected and repeatedly written into the storage unit according to the preset writing times (such as 10 ten thousand times), and then the second data is deleted or alternatively written according to specific conditions and corresponding detection analysis is performed.

S300, under the condition that the verification result represents that the storage data of the other storage units of the nth row are equal to the preset data, configuring the storage units of the nth row and the mth column as good units, and otherwise configuring the storage units of the nth row and the mth column as fault units.

Specifically, when the verification result shows that the stored data of the other memory cells in the nth row is equal to the preset data, it means that the other memory cells in the same row are not disturbed in the process of performing the test data writing operation on the memory cells in the nth row and the mth column, and the stored data is still kept in the preset data state which is originally set. This means that under the current write operation and hardware environment, there is no abnormal change condition of data caused by hardware faults (such as line short circuit, crosstalk between memory cells, etc.) between the memory cell (the memory cell in the nth row and the mth column) and other memory cells in the same row, so from the point of view, the working state of the memory cell is normal, so the memory cell can be configured as a good cell. The configuration mode provides clear basis for subsequent evaluation of the overall quality of the memory and further use and management, and is helpful for screening out the memory units with reliable performance.

For example, the whole memory is written with all '0' preset data in advance, then test data is written into the 3 rd row and 5 th column memory cells according to preset writing times, the data condition of other 3 rd row memory cells is checked every time, if the check finds that the data of other 3 rd row memory cells are always kept to be all '0', the 3 rd row memory cells and the 5 th column memory cells can be judged to be good units, so that the memory cells have no adverse effect on other same row memory cells when the data writing operation is performed, and the memory functions of the memory cells can be normally exerted.

Otherwise, if the verification result indicates that the stored data of the other storage units in the nth row are not equal to the preset data, it indicates that when the writing operation is performed on the storage units in the nth row and the mth column, the data of the other storage units in the same row are abnormally changed, and the data are not the preset data which are originally set. The situation is likely to be that the memory unit has hardware problems, such as abnormal signal interference generated when writing data due to the failure of an internal circuit of the memory unit, so that the data storage condition of other memory units in the same row is affected, or the memory unit with data jump has hardware defects, or the whole hardware association group (including the line of the row, the aspects of storage control logic and the like) has defects, so that the data cannot be stably and correctly stored. In view of the existence of these hardware-related factors that may cause data anomalies, it is necessary to configure this memory cell of the nth row and the mth column as a faulty cell in order to perform further troubleshooting, repair, or marking it as a defective product later, so as to avoid causing more serious data errors and the like due to this problematic memory cell in actual use.

Taking the preset data fully written with all 0's as an example, in the process of writing test data into the storage units of the 4 th row and the 7 th column, the situation that the data of other storage units of the 4 th row is partially changed into 1's or other storage units not conforming to the preset data of all 0's is found, which indicates that the storage unit of the 4 th row and the 7 th column and/or the storage unit with data jump in the associated hardware association group have faults, the storage unit needs to be marked as a fault unit, and then the specific fault cause can be determined through further detection means (such as checking lines, analyzing the electrical performance of the storage unit and the like).

S400, under the condition that all storage units in the initial storage are not fault units, configuring the initial storage as good-quality storage, otherwise configuring the initial storage as fault storage.

Specifically, after all the storage units in the initial memory are tested (such as repeating operations of writing test data, checking data of other storage units in the same row, and the like), it is determined that all the storage units in the initial memory are not fault units, which means that each storage unit can normally write and store data in the whole detection process, and bad data influence on other storage units in the same row is avoided, and data abnormality caused by hardware fault is avoided. The initial memory has good performance under various detection indexes, has complete and stable hardware structure and reliable data storage capacity, and can meet the use requirement in practical application. Therefore, the storage device is configured as a good storage device, and the quality of the factory products is guaranteed.

For example, assuming that an initial memory having 100×100 (row×column) memory cells is tested, according to a predetermined test method, operations such as writing corresponding test data into each memory cell and checking data of the memory cells in the same row are performed, and finally it is found that all 10000 memory cells can keep stable data in each test process, and the checking result accords with expectations, and if no situation that any unit determined to be a failure occurs, the initial memory is configured as a good memory, and can be normally put into use.

In the detection process, only one storage unit in the initial memory is configured as a fault unit, so that the memory has a hardware problem. Even if only one memory cell fails, a series of serious consequences such as data errors, unstable systems and the like may be caused in the subsequent practical use, because of the relevance among the memory cells, one failure cell may affect the work of other normal memory cells in a way of line, signal interference and the like, or cause the data read-write operation of the whole memory to be abnormal. Therefore, as long as a fault unit exists, the whole initial memory is required to be configured as a fault memory, so that the memory with potential problems can be prevented from flowing into markets or application scenes, the used memories are ensured to have reliable performance, meanwhile, the fault memory is convenient to further analyze and repair, the cause of the fault is found, and the production process or the product design is improved so as to improve the overall qualification rate of the product.

For example, in the detection process, if the memory cell of the 30 th row and the 40 th column is found to be judged as a fault cell through verification, even if the other 9999 memory cells are normal, the initial memory is configured as a fault memory according to rules, and then the initial memory is subjected to corresponding processing, such as checking whether the problem of the memory cell is itself or the fault hidden danger exists in the aspects of row and column related hardware circuits and the like.

In a second aspect, referring to fig. 3, an embodiment of the present invention provides a memory test system, including:

It can be seen that the content in the above method embodiment is applicable to the system embodiment, and the functions specifically implemented by the system embodiment are the same as those of the method embodiment, and the beneficial effects achieved by the method embodiment are the same as those achieved by the method embodiment.

In a third aspect, referring to fig. 4, an embodiment of the present invention provides a memory test apparatus, including:

At least one processor;

at least one memory for storing at least one program;

It can be seen that the content in the above method embodiment is applicable to the embodiment of the present device, and the functions specifically implemented by the embodiment of the present device are the same as those of the embodiment of the above method, and the beneficial effects achieved by the embodiment of the above method are the same as those achieved by the embodiment of the above method.

In a fourth aspect, furthermore, the embodiments of the present application disclose a computer program product or a computer program, which is stored in a computer-storable medium. The computer program may be read from a computer readable storage medium by a processor of a computer device, the processor executing the computer program to cause the computer device to perform the method or the system described above. Similarly, the content in the above method embodiment is applicable to the present storage medium embodiment, and the specific functions of the present storage medium embodiment are the same as those of the above method embodiment, and the achieved beneficial effects are the same as those of the above method embodiment.

It is to be understood that all or some of the steps, systems, and methods disclosed above may be implemented in software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, a digital information processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data message such as a carrier wave or other transport mechanism and includes any information delivery media.

The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present invention.

Claims

1. A method for testing a memory, comprising:

2. The method of claim 1, wherein after the configuring the memory cells of the nth row and the mth column as failed cells, the method further comprises:

Acquiring the memory unit with data jump in the nth row;

3. The method according to claim 2, wherein determining the hardware fault type of the hardware association group according to the detection result comprises:

4. A method according to claim 3, characterized in that the method further comprises:

5. The method of claim 1, wherein the setting of the preset number of writes comprises:

Linearly fitting the standard coordinate points to obtain a fitting curve;

6. The method of claim 1, wherein the repeatedly writing test data into the memory cells of the nth row and mth column of the initial memory according to a preset number of writes comprises:

7. The method of claim 5, wherein determining the offset coordinate point based on the average number of writes, the standard deviation, and a preset standard deviation multiple comprises:

8. A memory test system, comprising:

9. A memory test apparatus, comprising:

At least one processor;

at least one memory for storing at least one program;

the at least one program, when executed by the at least one processor, causes the at least one processor to implement the method of any of claims 1-7.

10. A computer readable storage medium, in which a processor executable program is stored, characterized in that the processor executable program is for performing the method according to any of claims 1-7 when being executed by a processor.