CN119578315A - A method for implementing a high-speed hardware self-checker for a linked list disorder - Google Patents
A method for implementing a high-speed hardware self-checker for a linked list disorder Download PDFInfo
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Abstract
本发明涉及通信芯片技术领域，具体涉及一种链表乱序硬件极速自查器的实现方法，包括以下步骤，系统上电，芯片链表初始化，ptrList数据结构清空，业务流打起来，芯片开始对数据帧进行存储、转发，与此同时ptrList开始对帧片段的指针做压入，以为存储操作，实时监控ptrList记录的指针及指针状态，若出现相同指针，且相同指针状态也一样时，则说明链表已经乱序，触发中断，系统进行初始化。本发明通过上述方法使得能够自动感知链表乱序，以及在乱序时能够触发中断并同时系统进行初始化，从而实现了在链表发生乱序初始时硬件就能自动感知并通知系统做出处理，且容易实现，逻辑简单，且容易基于此方法拓展多种场景应用。
The present invention relates to the field of communication chip technology, and specifically to a method for implementing a hardware high-speed self-checker for disordered linked lists, comprising the following steps: powering on the system, initializing the chip linked list, clearing the ptrList data structure, starting the service flow, and the chip starting to store and forward data frames. At the same time, ptrList starts to push pointers to frame fragments for storage operations, and monitors the pointers and pointer states recorded in ptrList in real time. If the same pointer appears and the same pointer state is the same, it means that the linked list is disordered, triggering an interrupt, and the system is initialized. The present invention enables automatic perception of disordered linked lists through the above method, and can trigger an interrupt and initialize the system at the same time when the disorder occurs, thereby realizing that the hardware can automatically perceive and notify the system to process when the disorder occurs in the linked list, and is easy to implement, simple in logic, and easy to expand multiple scene applications based on this method.
Description
Technical Field
The invention relates to the technical field of communication chips, in particular to a method for realizing a linked list disordered hardware extremely-fast self-checking device.
Background
In the design of the exchange chip, the messages input on the data path are interactive, and at the moment, the linked list is used for maintaining the front-back relation of the frame fragments in the storage space;
When the data frame fragments are written into the storage space, the linked list records that the fragments are connected to a specific address of the storage space, and when the data frame is read from the storage space, the next frame is found according to the storage addresses of the next frames of the frame before and after the linked list records, and the linked list space needs to be released when the data frame is read.
However, under some abnormal conditions, such as improper operation, bad environmental electrical characteristics, etc., the linked list is disordered, and at this time, memory leakage, design locking, etc., are caused;
most of the storage media based on Sram are used for recording the state of the pointer in the market, and the use state of the pointer is observed by reading the Sram, and the implementation method has the following defects:
the Sram can only read one item in each clock period, can not observe all pointer states in real time, and can not clear the states instantaneously;
sram occupies a larger chip area than the register set;
3. When the design main frequency is very high, especially in the FPGA design, the Sram has huge timing violations;
Therefore, if the state can be sensed at the beginning of the disorder, and the port can be closed by instantaneous clearing, the system can be informed to be initialized in advance, the serious problems can be avoided, and therefore, the realization method of the linked list disorder hardware self-checking device is provided.
Disclosure of Invention
Therefore, the invention aims to provide a method for realizing a linked list disordered hardware extremely-fast self-checking device, so as to solve the problems of memory disorder and system crash caused by the fact that hardware cannot automatically sense disordered when the disordered state occurs in the initial stage.
Based on the above purpose, the invention provides a method for realizing a linked list disordered hardware extremely-speed self-checking device, which comprises the following steps:
Step S1, powering up the system, initializing a chip linked list, emptying a ptrList data structure, parameterizing ptrList depth, matching the depth of storage units, PTRLISTCNT the number of ptrList used units, and initializing PTRLISTCNT to 0;
Step S2, the service flow is beaten up, the chip starts to store and forward the data frame, and meanwhile ptrList starts to push in pointers of the frame fragments, wherein the push-in content is { linked list pointers, pointer states };
step S3, real-time monitoring ptrList the linked list pointers and pointer states recorded, and observing the content of ptrList corresponding to the number according to the value of PTRLISTCNT;
S4, if the same pointer appears and the same pointer state is the same, indicating that the linked list is disordered;
In step S5, an interrupt is triggered, and the system is initialized, and meanwhile, the whole system ptrList is initialized by resetting PTRLISTCNT =0.
Preferably, in step S1, the method further comprises the steps of:
step S1.1, powering up the system, and setting a linked list pointer window array ptrList = { };
where { } represents initializing to a null pointer array or list;
Step S1.2, a state flag ptrStatus is set for each linked list pointer, wherein a ptrStatus value of 0 represents writing, and a ptrStatus value of 1 represents releasing;
Step S1.3, setting ptrList the depth occupancy count PTRLISTCNT, initializing to 0, indicating that there is no valid pointer in ptrList.
Preferably, in step S2, the method further comprises the steps of:
step S2.1, when the chip writes the frame fragments, the { linked list pointer, ptrStatus (0) } is used as a state variable to be pressed into ptrList, and PTRLISTCNT +1 is performed at the same time;
Step S2.2, when the chip releases the frame fragments, pressing { linked list pointers, ptrStatus (1) } into ptrList and PTRLISTCNT +1 at the same time;
Step S2.3, PTRLISTCNT-1 when PTRLISTCNT reaches the maximum depth of ptrList, indicates that the original pointer is cleared.
Preferably, in step S4, as the frame fragments are written or released continuously, there are PTRLISTCNT pointers other than 0, and of these numbers, if there are pointers of the same name and the status is the same, it is indicated that the pointers are already in disorder.
Preferably, in step S5, by initializing PTRLISTCNT =0, the entire reset ptrList, the system initialization includes turning off the interface receiving function and initializing the linked list.
The method has the beneficial effects that the method is realized by setting the linked list pointer window array PtrList and the array window depth scale parameter PTRLISTCNT, setting the ptrStatus value to 0 to represent writing and setting the ptrStatus value to 1 to represent releasing, so that the linked list disorder can be automatically perceived, and the interrupt can be triggered and the system is initialized at the same time when the disorder occurs, thereby realizing that the hardware can automatically perceive and inform the system to make treatment when the disorder occurs at the beginning of the linked list, being easy to realize, having simple logic and being easy to expand various scene applications based on the method.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an organization structure of an embodiment ptrList of the present invention;
FIG. 2 is a diagram illustrating a state shift of a linked list according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure when a chain table disorder occurs according to an embodiment of the present invention.
Detailed Description
The present invention will be further described in detail below with reference to specific embodiments and with reference to the accompanying drawings, in order to make the objects, technical solutions and advantages of the present invention more apparent.
It should be noted that unless otherwise defined, technical or scientific terms used in the embodiments of the present invention should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present invention belongs. The terms "first," "second," and the like, as used herein, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
As shown in fig. 1, 2 and 3, the method for implementing the linked list out-of-order hardware extremely-speed self-checker comprises the following steps:
Step S1, powering up the system, initializing a chip linked list, emptying a ptrList data structure, parameterizing ptrList depth, matching the depth of storage units, PTRLISTCNT the number of ptrList used units, and initializing PTRLISTCNT to 0;
In step S1, the method further comprises the steps of:
step S1.1, powering up the system, and setting a linked list pointer window array ptrList = { };
where { } represents initializing to a null pointer array or list;
Step S1.2, a state flag ptrStatus is set for each linked list pointer, wherein a ptrStatus value of 0 represents writing, and a ptrStatus value of 1 represents releasing;
Step S1.3, setting ptrList the depth occupancy count PTRLISTCNT, initializing to 0, indicating that there is no valid pointer in ptrList.
Compared with the prior two sets of storage spaces of the storage resource pointer and the empty linked list pointer, the storage resource and the empty linked list are one set, and at least half of the storage resource and the empty linked list are less used on the chip area.
Step S2, the service flow is beaten up, the chip starts to store and forward the data frame, meanwhile ptrList starts to push in pointers of the frame fragments, push in contents are { linked list pointers, pointer states }, the pointer states pushed in during storage are written in, and the pointer states pushed in during release are released;
in step S2, the method further comprises the steps of:
step S2.1, when the chip writes the frame fragments, the { linked list pointer, ptrStatus (0) } is used as a state variable to be pressed into ptrList, and PTRLISTCNT +1 is performed at the same time;
Step S2.2, when the chip releases the frame fragments, pressing { linked list pointers, ptrStatus (1) } into ptrList and PTRLISTCNT +1 at the same time;
Step S2.3, PTRLISTCNT-1 when PTRLISTCNT reaches the maximum depth of ptrList, indicates that the original pointer is cleared.
The writing of the packet fragments into the cache is performed by a special function control module, when the packet fragments come, the control module takes a free pointer, writes the fragments into the memory address indicated by the free pointer, and simultaneously presses the pointer into prtList.
Step S3, real-time monitoring ptrList the linked list pointers and pointer states recorded, and observing the content of ptrList corresponding to the number according to the value of PTRLISTCNT;
in step S3, as the frame fragments are continuously written or released, ptrList will shift, when ptrList is full, the linked list pointer overflows, the overflow refers to natural discarding, the pointer entering the window must be subjected to two states before overflowing according to the actual performance of the design, namely, the use and release states are performed, namely, the pointer is subjected to two states before overflowing under normal conditions, and the design ensures that the window period of the pointer meets the normal condition time.
Step S4, if the same pointer appears and the same pointer states are the same, the linked list is described as being disordered, as shown in FIG. 3, more than 1 ptr10 appears at the moment, and the states of the two ptr10 are written, so that the linked list is described as being disordered;
Step S5, triggering an interrupt, the system initializes, and at the same time, by resetting PTRLISTCNT =0 the whole initialization ptrList,
In step S5, by initializing PTRLISTCNT =0, the whole reset ptrList, the system initialization includes closing the interface receiving function and initializing the linked list, so that the system can be initialized at the beginning of the disorder of the linked list, the user does not feel the linked list, and the system crash caused by the disorder of the memory is effectively prevented.
Aging is absolutely unusable in this process, because traffic is always forwarded on the chip, and aging is done at this time, for some jumbo frames or low priority messages that exist for some QOS reasons, if aging at this time, would result in memory leaks in actual use,
Because the invention is a register array, the logic can see the content of all registers in actual operation, and can update the content of all registers at one time, and can be aged instantaneously.
The PtrList data structure is realized by using a queue built by a register array instead of the FIFO, that is, the states of all the pressed pointers can be observed at one time at the same time, and the actual problem caused by the depth of the FIFO is not considered in the design of a high-speed chip. The shift register includes S1-S5, which will function throughout the process.
In summary, the method and the system can automatically sense the disorder of the linked list, trigger the interrupt and initialize the system at the same time when the disorder occurs, so that the hardware can automatically sense and inform the system to process when the disorder occurs at the beginning of the linked list, the method and the system are easy to realize, the logic is simple, and various scene applications are easily expanded based on the method.
It will be appreciated by persons skilled in the art that the above discussion of any embodiment is merely exemplary and is not intended to imply that the scope of the invention is limited to these examples, that combinations of technical features in the above embodiments or in different embodiments may also be implemented in any order, and that many other variations of the different aspects of the invention as described above exist, which are not provided in detail for the sake of brevity.
The embodiments of the invention are intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omission, modification, equivalent replacement, improvement, etc. of the present invention should be included in the scope of the present invention.
Claims (5)
1. The method for realizing the chain list disordered hardware extremely-speed self-checking device is characterized by comprising the following steps of:
Step S1, powering up the system, initializing a chip linked list, emptying a ptrList data structure, parameterizing ptrList depth, matching the depth of storage units, PTRLISTCNT the number of ptrList used units, and initializing PTRLISTCNT to 0;
Step S2, the service flow is beaten up, the chip starts to store and forward the data frame, and meanwhile ptrList starts to push in pointers of the frame fragments, wherein the push-in content is { linked list pointers, pointer states };
step S3, real-time monitoring ptrList the linked list pointers and pointer states recorded, and observing the content of ptrList corresponding to the number according to the value of PTRLISTCNT;
S4, if the same pointer appears and the same pointer state is the same, indicating that the linked list is disordered;
In step S5, an interrupt is triggered, and the system is initialized, and meanwhile, the whole system ptrList is initialized by resetting PTRLISTCNT =0.
2. The method for implementing the linked list out-of-order hardware fast self-checker according to claim 1, wherein in step S1, the method further comprises the steps of:
step S1.1, powering up the system, and setting a linked list pointer window array ptrList = { };
where { } represents initializing to a null pointer array or list;
Step S1.2, a state flag ptrStatus is set for each linked list pointer, wherein a ptrStatus value of 0 represents writing, and a ptrStatus value of 1 represents releasing;
Step S1.3, setting ptrList the depth occupancy count PTRLISTCNT, initializing to 0, indicating that there is no valid pointer in ptrList.
3. The method for implementing the linked list out-of-order hardware fast self-checker according to claim 2, further comprising the following steps in step S2:
step S2.1, when the chip writes the frame fragments, the { linked list pointer, ptrStatus (0) } is used as a state variable to be pressed into ptrList, and PTRLISTCNT +1 is performed at the same time;
Step S2.2, when the chip releases the frame fragments, pressing { linked list pointers, ptrStatus (1) } into ptrList and PTRLISTCNT +1 at the same time;
Step S2.3, PTRLISTCNT-1 when PTRLISTCNT reaches the maximum depth of ptrList, indicates that the original pointer is cleared.
4. A method of implementing a linked list out-of-order hardware fast self-checker as claimed in claim 3, characterized in that in step S4 there are PTRLISTCNT pointers other than 0 as the frame fragments are written or released, of which number pointers, if there are homonymous pointers and the status is the same, it is stated that the pointers are out of order.
5. The method according to claim 1, wherein in step S5, by initializing PTRLISTCNT =0, the whole reset ptrList, the system initialization includes turning off the interface receiving function and initializing the linked list.
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| US20080301646A1 (en) * | 2007-05-29 | 2008-12-04 | Satish Chandra Gupta | Detecting Dangling Pointers and Memory Leaks Within Software |
| US20170031815A1 (en) * | 2015-07-29 | 2017-02-02 | Pradeep Varma | Wand: Concurrent Boxing System For All Pointers With Or Without Garbage Collection |
| CN118524120A (en) * | 2024-07-05 | 2024-08-20 | 积成电子股份有限公司 | Method for solving problem of frame disorder generated by data reception during CAN communication based on electric energy meter |
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- 2024-11-19 CN CN202411653066.0A patent/CN119578315B/en active Active
Patent Citations (7)
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| US5388238A (en) * | 1992-07-24 | 1995-02-07 | At&T Corp. | System and method for monitoring the validity of circulating pointers in a FIFO memory |
| US5539875A (en) * | 1994-12-30 | 1996-07-23 | International Business Machines Corporation | Error windowing for storage subsystem recovery |
| US6697366B1 (en) * | 1998-11-18 | 2004-02-24 | Samsung Electronics Co., Ltd. | Ethernet memory management system and methods for operation thereof |
| US6542512B1 (en) * | 1999-07-02 | 2003-04-01 | Jenny Liu Fischer | Architecture and method for flushing non-transmitted portions of a data frame from a transmitted FIFO buffer |
| US20080301646A1 (en) * | 2007-05-29 | 2008-12-04 | Satish Chandra Gupta | Detecting Dangling Pointers and Memory Leaks Within Software |
| US20170031815A1 (en) * | 2015-07-29 | 2017-02-02 | Pradeep Varma | Wand: Concurrent Boxing System For All Pointers With Or Without Garbage Collection |
| CN118524120A (en) * | 2024-07-05 | 2024-08-20 | 积成电子股份有限公司 | Method for solving problem of frame disorder generated by data reception during CAN communication based on electric energy meter |
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