CN119421470B - Semiconductor device and preparation method thereof - Google Patents
Semiconductor device and preparation method thereof Download PDFInfo
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- CN119421470B CN119421470B CN202510012846.5A CN202510012846A CN119421470B CN 119421470 B CN119421470 B CN 119421470B CN 202510012846 A CN202510012846 A CN 202510012846A CN 119421470 B CN119421470 B CN 119421470B
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Abstract
The invention discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, an epitaxial layer, a grid electrode structure and a buried layer structure, wherein the substrate is provided with a first conductive type, the epitaxial layer is provided with the first conductive type and is positioned on the surface of the substrate, the epitaxial layer comprises a first surface, a grid electrode groove is formed in the first surface, the grid electrode structure is positioned in the grid electrode groove, the buried layer structure comprises a first buried layer and a second buried layer, the second buried layer is provided with the first conductive type, the first buried layer is provided with the second conductive type, the ion concentration of the second buried layer is larger than that of the epitaxial layer, and the second buried layer is configured to reduce the width of a depletion region between the second buried layer and the first buried layer. The technical scheme of the embodiment of the invention can protect the gate oxide layer from being broken down easily, improve the reliability of the device and ensure the on-state current of the device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
A metal oxide semiconductor field effect Transistor (Metal Oxide Semiconductor FIELD EFFECT Transistor, MOSFET) with a silicon carbide (SiC) trench gate structure has the advantages of large current density, small cell spacing, high switching speed and the like, and becomes a main research object of a new generation of SiC MOSFETs.
In a MOSFET of a SiC trench gate structure, the electric field at the trench bottom and the trench corner is high, resulting in a high electric field on the gate oxide of the trench gate structure, which is prone to breakdown. In order to protect the gate oxide layer from breakdown and improve the reliability of the MOSFET, the prior art proposes to use a double trench structure or an asymmetric structure to achieve the above effects. However, the use of additional fabrication of the dual source trench structure or the use of an asymmetric structure may increase process complexity or affect on-state current of the device.
Disclosure of Invention
The invention provides a semiconductor device and a preparation method thereof, which are used for solving the problem that the reliability of the device is low due to the fact that a gate oxide layer of a MOSFET with a SiC trench gate structure is easy to break down, and ensuring the on-state current of the MOSFET.
According to an aspect of the present invention, there is provided a semiconductor device including:
a substrate having a first conductivity type;
An epitaxial layer of the first conductivity type and located on a surface of the substrate, the epitaxial layer comprising a first surface provided with a gate trench;
a gate structure located inside the gate trench;
The semiconductor device includes a buried layer structure including a first buried layer and a second buried layer, the second buried layer having the first conductivity type, the first buried layer having a second conductivity type, and an ion concentration of the second buried layer being greater than an ion concentration of the epitaxial layer, the second buried layer being configured to reduce a depletion region width between the second buried layer and the first buried layer.
Optionally, the first buried layer includes a first buried sub-layer portion and a second buried sub-layer portion, the first buried sub-layer portion is located at a side of the bottom of the gate structure, which is close to the substrate, the second buried sub-layer portion is located at a side of the first buried sub-layer portion, which is far from the gate structure, and the second buried sub-layer portion is in contact with the first buried sub-layer portion;
The first buried sub-layer part has a width smaller than that of the second buried sub-layer part, and the second buried sub-layer part is arranged on at least one side of the second buried sub-layer part in the thickness direction perpendicular to the substrate.
Optionally, a side of the first buried sub-layer portion, which is close to the gate structure, has a first preset width, a side of the first buried sub-layer portion, which is far away from the gate structure, has a second preset width, and the width of the first buried sub-layer portion is between the first preset width and the second preset width;
the first preset width is smaller than the third preset width, and the second preset width is smaller than or equal to the third preset width.
Optionally, the first preset width is smaller than the second preset width, and the width of the first buried sub-layer portion gradually increases from the first preset width to the second preset width.
Optionally, the second preset width is equal to the first preset width, and the first preset width and the second preset width are both smaller than the third preset width.
Optionally, the first buried layer further includes a third buried sub-layer portion;
The third buried sub-layer part is positioned at one side of the second buried sub-layer part far away from the first buried sub-layer part, and is contacted with the second buried sub-layer part;
The third buried sub-layer portion has a fourth preset width, which is smaller than the third preset width.
Optionally, the gate structure comprises two opposite sides, and the semiconductor device further comprises a first doped region located on at least one side of the gate structure;
The second buried layer comprises a fourth buried sub-layer part and a fifth buried sub-layer part, wherein the fourth buried sub-layer part comprises a second surface and a third surface which are perpendicular to each other, and the fifth buried sub-layer part comprises a fourth surface and a fifth surface which are perpendicular to each other;
the second surface is in contact with the bottom of the first doped region, and the third surface is in contact with the second buried sub-layer portion in a thickness direction perpendicular to the substrate;
The fourth surface is in contact with the side surface of the first doped region, and the fifth surface is in contact with the fourth buried sub-layer portion;
wherein the first doped region has the second conductivity type.
Optionally, the semiconductor device further includes:
A second doped region of the first conductivity type located on the first surface of the epitaxial layer;
A body region of the second conductivity type on a side of the second doped region remote from the first surface;
The dielectric layer is positioned on one side of the epitaxial layer far away from the substrate, and the orthographic projection of the dielectric layer on the substrate covers the orthographic projection of the grid structure on the substrate;
the source electrode is positioned on one side of the dielectric layer far away from the epitaxial layer, and the orthographic projection of the source electrode on the substrate is completely overlapped with the orthographic projection of the substrate;
The passivation layer is positioned on one side of the source electrode far away from the epitaxial layer, and the orthographic projection of the passivation layer on the substrate covers the orthographic projection of the first doped region on the substrate;
And the drain electrode is positioned on one side of the substrate away from the epitaxial layer.
According to another aspect of the present invention, there is provided a semiconductor device manufacturing method including:
providing a substrate, wherein the substrate has a first conductivity type;
Forming an epitaxial layer on the surface of the substrate, wherein the epitaxial layer has the first conductivity type and comprises a first surface;
Forming a buried layer structure in the epitaxial layer, the buried layer structure comprising a first buried layer and a second buried layer, the second buried layer having the first conductivity type, the first buried layer having a second conductivity type, and an ion concentration of the second buried layer being greater than an ion concentration of the epitaxial layer, the second buried layer being configured to reduce a depletion region width between the second buried layer and the first buried layer;
forming a gate trench on the first surface;
And forming a gate structure inside the gate trench.
Optionally, the first buried layer includes a first buried sub-layer portion, a second buried sub-layer portion and a third buried sub-layer portion, and the second buried layer includes a fourth buried sub-layer portion and a fifth buried sub-layer portion;
the forming a buried layer structure in the epitaxial layer comprises the following steps:
performing ion implantation on the epitaxial layer to form a third buried sub-layer part;
performing ion implantation on the epitaxial layer again to form a second buried sub-layer part and a fourth buried sub-layer part, wherein the fourth buried sub-layer part is in contact with the second buried sub-layer part in the direction perpendicular to the substrate, and the third buried sub-layer part is in contact with the second buried sub-layer part in the thickness direction of the substrate;
forming the epitaxial layer again at one side of the second buried sub-layer part and the fourth buried sub-layer part away from the substrate;
ion implantation is carried out on the epitaxial layer again to form a first buried sub-layer part and a fifth buried sub-layer part, wherein the first buried sub-layer part is contacted with the second buried sub-layer part, and the fifth buried sub-layer part is contacted with the fourth buried sub-layer part;
Forming the epitaxial layer again at one side of the first buried sub-layer part and the fifth buried sub-layer part away from the substrate;
The method further comprises the following steps before forming the grid groove in the epitaxial layer:
Performing ion implantation on the first surface to form a body region and a second doped region, wherein the second doped region is positioned on the first surface of the epitaxial layer, and the body region is positioned on one side of the second doped region away from the first surface;
after the gate trench is formed in the epitaxial layer, the method further comprises:
Performing ion implantation on the first surface to form a first doped region, wherein the first doped region is positioned on at least one side of the grid electrode groove;
The preparation method of the semiconductor device further comprises the following steps:
Forming a dielectric layer on one side of the epitaxial layer far away from the substrate, wherein the orthographic projection of the dielectric layer on the substrate covers the orthographic projection of the grid structure on the substrate;
Forming a source electrode on one side of the dielectric layer far away from the epitaxial layer, wherein the orthographic projection of the source electrode on the substrate is completely overlapped with the orthographic projection of the substrate;
Forming a passivation layer on one side of the source electrode far away from the epitaxial layer, wherein the orthographic projection of the passivation layer on the substrate covers the orthographic projection of the first doped region on the substrate;
and forming a drain electrode on one side of the substrate away from the epitaxial layer.
In the semiconductor device provided by the embodiment of the invention, the epitaxial layer has the first conductivity type, the buried layer structure is arranged in the epitaxial layer, and comprises a first buried layer and a second buried layer, wherein the first buried layer has the second conductivity type, and the second buried layer has the first conductivity type. And the ion doping concentration of the first buried layer and the ion doping concentration of the second buried layer are higher than the ion doping concentration of the epitaxial layer, so that a depletion region can be formed around the gate structure by the first buried layer and the epitaxial layer, thereby shielding a higher electric field around the gate structure and protecting the gate oxide layer from breakdown. And the formation of the depletion region between the first buried layer and the epitaxial layer also can obstruct the flow of electrons in the semiconductor device, and influence the on-state current of the semiconductor device. Therefore, a depletion region with smaller width is formed between the second buried layer and the first buried layer with higher ion doping concentration, which is beneficial to ensuring a current conduction channel at two sides of the grid structure and increasing on-state current of the semiconductor device. The first buried layer and the second buried layer are arranged in such a way, so that a good shielding effect can be achieved on a higher electric field around the grid structure, the reliability of the semiconductor device can be improved, a current conduction channel in the semiconductor device can be ensured, and the on-state current of the semiconductor device can be increased.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional structure of a semiconductor device according to an embodiment of the present invention;
Fig. 2 is a schematic cross-sectional structure of still another semiconductor device provided according to an embodiment of the present invention;
Fig. 3 is a schematic cross-sectional structure of yet another semiconductor device provided in accordance with an embodiment of the present invention;
fig. 4 is a schematic cross-sectional structure of still another semiconductor device provided according to an embodiment of the present invention;
Fig. 5 is a schematic cross-sectional structure of still another semiconductor device provided according to an embodiment of the present invention;
fig. 6 is a schematic cross-sectional structure of yet another semiconductor device provided in accordance with an embodiment of the present invention;
Fig. 7 is a schematic cross-sectional structure of still another semiconductor device provided according to an embodiment of the present invention;
fig. 8 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 9 is a schematic cross-sectional view corresponding to each step in FIG. 8;
fig. 10 is a schematic diagram of a specific flow of step S130 in a semiconductor device manufacturing method according to an embodiment of the present invention;
Fig. 11 is a schematic sectional structure corresponding to each step in step S130;
fig. 12 is a schematic cross-sectional structure corresponding to a step before forming a gate trench;
fig. 13 is a schematic cross-sectional structure corresponding to a step after forming a gate trench;
fig. 14 is a schematic flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 15 is a schematic sectional structure corresponding to step S160 to step S190.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the invention provides a semiconductor device. Fig. 1 is a schematic cross-sectional structure of a semiconductor device according to an embodiment of the present invention. As shown in fig. 1, the semiconductor device includes a substrate 10, an epitaxial layer 11, a gate structure 12, and a buried layer structure 13.
The substrate 10 has a first conductivity type, the epitaxial layer 11 has the first conductivity type and is located on the surface of the substrate 10, the epitaxial layer 11 comprises a first surface 111, the first surface 111 is provided with a gate trench, the gate structure 12 is located inside the gate trench, the buried layer structure 13 comprises a first buried layer 131 and a second buried layer 132, the second buried layer 132 has the first conductivity type, the first buried layer 131 has the second conductivity type, the ion concentration of the second buried layer 132 is greater than the ion concentration of the epitaxial layer 11, and the second buried layer 132 is configured to reduce the depletion region width between the first buried layer 131.
Specifically, the substrate 10 may be a silicon carbide base with a high ion doping concentration. A silicon carbide film layer having a low ion doping concentration of the first conductivity type is grown on the surface of the substrate 10 to form the epitaxial layer 11. The first conductivity type may be N-type or P-type, for example, and is not limited herein. In the embodiment of the present invention, the structure of the semiconductor device will be described by taking the first conductivity type as N-type and the second conductivity type as P-type as an example. A surface of the epitaxial layer 11 on a side away from the substrate 10 is a first surface 111, and a gate trench is provided extending from the first surface 111 into the epitaxial layer 11, and the gate trench is filled with a gate structure 12. Note that, the gate trench is a process structure generated in the manufacturing process of the semiconductor device, and thus, the gate trench is not labeled in fig. 1. The gate structure 12 includes a gate oxide layer 121 covering the bottom and the sidewall of the gate trench and a gate 122 disposed on a side of the gate oxide layer 121 away from the gate trench, and the thickness of the gate oxide layer 121 disposed at the bottom of the gate trench is greater than the thickness of the gate oxide layer 121 disposed on the sidewall of the gate trench 22, so as to enhance the breakdown resistance of the gate oxide layer 121 in the gate trench, which is beneficial to improving the reliability of the semiconductor device.
A buried layer structure 13 is further provided in the epitaxial layer 11, and the buried layer structure 13 includes a first buried layer 131 located at the bottom of the gate structure 12 and a second buried layer 132 located at least on one side of the first buried layer 131. Illustratively, the first buried layer 131 may be a P-type heavily doped region, and the second buried layer 132 is an N-type heavily doped region. Since the first buried layer 131 and the epitaxial layer 11 form a depletion region, it is advantageous to shield a higher electric field at the bottom of the gate structure 12, so as to ensure that the gate oxide layer 121 in the gate structure 12 is not easily broken down. However, if the depletion region formed between the first buried layer 131 and the epitaxial layer 11 is too wide, electron flow is hindered, and on-state current of the semiconductor device is affected. By disposing the second buried layer 132 on at least one side of the first buried layer 131 in the thickness direction perpendicular to the substrate 10. Since the ion doping concentration of the second buried layer 132 is higher than that of the epitaxial layer 11, the width of the depletion region formed between the second buried layer 132 and the first buried layer 131 can be effectively reduced, and a current conduction channel can be provided for the semiconductor device, so that the on-state current of the semiconductor device can be increased.
In the semiconductor device provided by the embodiment of the invention, the epitaxial layer has the first conductivity type, the buried layer structure is arranged in the epitaxial layer, and comprises a first buried layer and a second buried layer, wherein the first buried layer has the second conductivity type, and the second buried layer has the first conductivity type. And the ion doping concentration of the first buried layer and the ion doping concentration of the second buried layer are higher than the ion doping concentration of the epitaxial layer, so that a depletion region can be formed around the gate structure by the first buried layer and the epitaxial layer, thereby shielding a higher electric field around the gate structure and protecting the gate oxide layer from breakdown. And the formation of the depletion region between the first buried layer and the epitaxial layer also can obstruct the flow of electrons in the semiconductor device, and influence the on-state current of the semiconductor device. Therefore, a depletion region with smaller width is formed between the second buried layer and the first buried layer with higher ion doping concentration, which is beneficial to ensuring a current conduction channel at two sides of the grid structure and increasing on-state current of the semiconductor device. The first buried layer and the second buried layer are arranged in such a way, so that a good shielding effect can be achieved on a higher electric field around the grid structure, the reliability of the semiconductor device can be improved, a current conduction channel in the semiconductor device can be ensured, and the on-state current of the semiconductor device can be increased.
Optionally, fig. 2 is a schematic cross-sectional structure of still another semiconductor device according to an embodiment of the present invention. On the basis of the above embodiment, as shown in fig. 2, the first buried layer 131 includes the first buried sub-layer portion 311 and the second buried sub-layer portion 312, the first buried sub-layer portion 311 is located at a side of the bottom of the gate structure 12 close to the substrate 10, the second buried sub-layer portion 312 is located at a side of the first buried sub-layer portion 311 away from the gate structure 12, and the second buried sub-layer portion 312 is in contact with the first buried sub-layer portion 311, the width of the first buried sub-layer portion 311 is smaller than the width of the second buried sub-layer portion 312, and the second buried sub-layer 132 is disposed at least at one side of the second buried sub-layer portion 312 in a thickness direction perpendicular to the substrate 10.
Specifically, the first buried sub-layer portion 311 is disposed near the bottom of the gate structure 12, and the first buried sub-layer portion 311 is in contact with the bottom of the gate structure 12. The second buried sub-layer portion 312 is disposed on a side away from the gate structure 12 with respect to the position of the first buried sub-layer portion 311, and the second buried sub-layer portion 312 is in contact with the first buried sub-layer portion 311. By arranging the first buried sub-layer portion 311 close to the bottom of the gate structure 12 to have a smaller width, a wider depletion region can be formed between the first buried sub-layer portion 311 with higher ion doping concentration and the epitaxial layer 11, a certain shielding effect is achieved on the electric field at the bottom of the gate structure 12, and a wider current conduction channel can be ensured at the bottom of the gate structure 12, so that the on-state current of the semiconductor device is increased. By providing the second buried sub-layer portion 312 far away from the bottom of the gate structure 12 with a larger width, the electric field at both sides of the gate structure 12 can be shielded, which is beneficial to improving the shielding effect on the electric field around the gate structure 12, improving the breakdown resistance of the gate oxide layer 121, and further improving the reliability of the semiconductor device.
The arrangement of the widths of the first buried sub-layer portion 311 and the second buried sub-layer portion 312 in the first buried layer 131 may include various cases, and the following embodiments will specifically describe cases in which the widths of the first buried sub-layer portion 311 and the second buried sub-layer portion 312 may occur.
Optionally, fig. 3 is a schematic cross-sectional structure of still another semiconductor device according to an embodiment of the present invention. On the basis of the above embodiment, as shown in fig. 3, a side of the first buried sub-layer portion 311 close to the gate structure 12 has a first preset width d1, a side of the first buried sub-layer portion 311 far from the gate structure 12 has a second preset width d2, and the width of the first buried sub-layer portion 311 is between the first preset width d1 and the second preset width d2, the second buried sub-layer portion 312 has a third preset width, and the first preset width d1 is smaller than the third preset width, and the second preset width d2 is smaller than or equal to the third preset width.
Specifically, the widths of the first buried sub-layer portion 311 disposed near the gate structure 12 may be different at different positions, and the electric field shielding effect generated by the different widths may be different. Illustratively, a side of the first buried sub-layer portion 311 close to the gate structure 12 may have a first preset width d1, a side distant to the gate structure 12 may have a second preset width d2, and the widths of different positions of the first buried sub-layer portion 311 are each between the first preset width d1 and the second preset width d 2. The second buried sub-layer portion 312 has a smaller extension depth in the epitaxial layer 11, and has a uniform third preset width d3 at different positions. In order to ensure that the first buried sub-layer portion 311 has a certain shielding effect on an electric field around the gate structure 12, and also ensure that the semiconductor device has a wider current conduction channel, on-state current is increased, the first preset width d1 may be set smaller than the third preset width d3, and the second preset width d2 is smaller than or equal to the third preset width d3, so that the width of the first buried sub-layer portion 311 at a position close to the gate structure 12 is smaller, and the electric field in the middle of the gate structure 12 is shielded to a certain extent, and meanwhile, current circulation at two sides of the gate structure 12 is ensured, and on-state current of the semiconductor device is increased.
Note that, the third preset width d3 of the second buried sub-layer portion 312 may be smaller than the width of the gate structure 12, may be equal to the width of the gate structure 12, or may be larger than the width of the gate structure 12, which is not limited herein. The larger the width of the first buried layer 131, the better the shielding effect on the higher electric field around the gate structure 12, but the transmission channel of the on-current is reduced, so that the on-current is reduced. Therefore, the specific width of the first buried layer 131 may be set by the user according to the actual requirement of the semiconductor device, and only the size relationship between the widths needs to be satisfied, which is not limited herein.
Optionally, fig. 4 is a schematic cross-sectional structure of still another semiconductor device according to an embodiment of the present invention. On the basis of the above embodiments, referring to fig. 3 and 4, the first preset width d1 is smaller than the second preset width d2, and the width of the first buried sub-layer portion 311 gradually increases from the first preset width d1 to the second preset width d2.
Illustratively, the width of the first buried sub-layer portion 311 may be set between the first preset width d1 and the second preset width d2, and the width of the first buried sub-layer portion 311 gradually increases from a side close to the gate structure 12 to a side far from the gate structure 12, i.e., the cross-sectional shape of the first buried sub-layer portion 311 may be a positive trapezoid, as shown in fig. 3. When the first preset width d1 is 0, the cross-sectional shape of the first buried sub-portion 311 may also be triangular, as shown in fig. 4. It should be noted that the second preset width d2 of the first buried sub-layer portion 311 may be equal to the third preset width d3 of the second buried sub-layer portion 312, and the second preset width d2 may also be smaller than the third preset width d3, which is not limited herein. This allows the first buried sub-layer portion 311 near the bottom of the gate structure 12 to shield a higher electric field in the middle of the gate structure 12 and to secure an on-current path of the semiconductor device, thereby increasing on-current.
Optionally, with continued reference to fig. 2, the second preset width d2 is equal to the first preset width d1, and the first preset width d1 and the second preset width d2 are both smaller than the third preset width d3.
Illustratively, the second preset width d2 is set equal to the first preset width d1, i.e., the widths of the first buried sub-layer portion 311 at different positions are all equal. Thus, the first buried sub-layer portion 311 and the second buried sub-layer portion 312 form an inverted T-shaped cross-section, so that the first buried sub-layer portion 311 near the bottom of the gate structure 12 can not only shield the electric field in the middle of the gate structure 12, but also ensure the current conduction channels at two sides of the gate structure 12 and increase the on-state current.
Optionally, fig. 5 is a schematic cross-sectional structure of still another semiconductor device according to an embodiment of the present invention. On the basis of the above embodiments, as shown in fig. 5, the first buried layer 131 further includes a third buried sub-layer portion 313.
The third buried sub-layer portion 313 is located at a side of the second buried sub-layer portion 312 away from the first buried sub-layer portion 311, and the third buried sub-layer portion 313 is in contact with the second buried sub-layer portion 312, wherein the third buried sub-layer portion 313 has a fourth preset width d4, and the fourth preset width d4 is smaller than the third preset width d3.
Specifically, the third buried sub-layer portion 313 is disposed on the side of the second buried sub-layer portion 312 away from the first buried sub-layer portion 311, so that the extension depth of the first buried sub-layer 131 in the epitaxial layer 11 is prolonged, and the shielding effect of the first buried sub-layer 131 on the higher electric field around the gate structure 12 can be further enhanced, so that the gate oxide 121 in the gate structure 12 is protected from being broken down, and the reliability of the semiconductor device is improved. The fourth preset widths d4 of the third buried sub-layer portion 313 at different positions are smaller than the third preset width d3 of the second buried sub-layer portion 312, so that a transmission channel of on-current can be ensured, and on-state current of the semiconductor device can be increased. Illustratively, the fourth preset widths d4 at different positions of the third buried sub-layer portion 313 may be all equal, i.e., the third buried sub-layer portion 313 is provided in a rectangular shape or a stripe shape. Referring to fig. 5, the cross-section of the first buried layer 131 formed by the first buried sub-layer 311, the second buried sub-layer 312 and the third buried sub-layer 313 is cross, which can play a good role in shielding a higher electric field around the gate structure 12, protect the gate oxide 121 from breakdown, improve the reliability of the semiconductor device, and ensure that the semiconductor device has a sufficient on-current transmission channel, thereby increasing on-state current and ensuring that the performance of the semiconductor device is not affected.
Optionally, fig. 6 is a schematic cross-sectional structure of still another semiconductor device according to an embodiment of the present invention. On the basis of the above embodiments, the gate structure comprises two opposite sides, and the semiconductor device further comprises a first doped region 14 located on at least one side of the gate structure 12, as shown in fig. 6.
The second buried layer 132 includes a fourth buried sub-layer portion 321 and a fifth buried sub-layer portion 322, the fourth buried sub-layer portion 321 includes a second surface 3211 and a third surface 3212 perpendicular to each other, and the fifth buried sub-layer portion 322 includes a fourth surface 3221 and a fifth surface perpendicular to each other.
The second surface 3211 contacts the bottom of the first doped region 14 and the third surface 3212 contacts the second buried sub-layer 312 in a thickness direction perpendicular to the substrate 10, the fourth surface 3221 contacts the side of the first doped region 14 and the fifth surface contacts the fourth buried sub-layer 321, wherein the first doped region 14 has the second conductivity type.
Specifically, the first doped region 14 may be a heavily doped region. In the present embodiment, the first conductivity type of the epitaxial layer 11 is N-type, and the second conductivity type of the first doped region 14 is P-type. The first doped region 14 may be disposed on one side of the gate structure 12 perpendicular to the thickness direction of the substrate 10, or may be disposed on both sides of the gate structure 12 perpendicular to the thickness direction of the substrate 10, which is not limited herein, and fig. 6 illustrates a case where the first doped region 14 is disposed on both sides of the gate structure 12 perpendicular to the thickness direction of the substrate 10, for example. The cross-sectional shapes of the fourth buried sub-layer portion 321 and the fifth buried sub-layer portion 322 in the second buried layer 132 are rectangular, and the fourth buried sub-layer portion 321 and the second buried sub-layer portion 312 are arranged in the same layer, and illustratively, the third surface 3212 in the fourth buried sub-layer portion 321 may contact the second buried sub-layer portion 312, or a smaller gap may also be formed between the fourth buried sub-layer portion 321 and the second buried sub-layer portion 312, which is not limited herein. The fourth buried sub-layer portion 321 has a higher ion doping concentration, so that an on-current transmission channel can be formed with the second buried sub-layer portion 312, which is beneficial to increasing on-state current. The fifth surface of the fifth buried sub-layer portion 322 is in contact with a portion of the second surface 3211 of the fourth buried sub-layer portion 321, and the fourth surface 3221 of the fifth buried sub-layer portion 322 is in contact with a side surface of the first doped region 14. Wherein the fifth surface is not labeled in fig. 6. That is, the fourth buried sub-layer portion 321 and the fifth buried sub-layer portion 322 form one half surrounding structure, and half surrounding is achieved to the bottom surface of the first doped region 14 and the side surface portion near the gate structure 12. Since the conductivity type of the first doped region 14 is different from the conductivity type of the second buried layer 132, and the first doped region 14 and the second buried layer 132 are both heavily doped regions, the width of the depletion region is reduced, and thus the conduction effect of the freewheeling diode formed in the region where the first doped region 14 and the second buried layer 132 are in contact is good. And the fourth buried sub-layer portion 321 and the fifth buried sub-layer portion 322 are arranged to form a semi-surrounding to the first doped region 14, so that the contact area between the second buried layer 132 and the first doped region 14 can be further increased, and the on-state current of the flywheel diode can be further increased.
Alternatively, fig. 7 is a schematic cross-sectional structure of still another semiconductor device according to an embodiment of the present invention. On the basis of the above embodiments, the semiconductor device further includes a second doped region 15, a body region 16, a dielectric layer 17, a source electrode 18, a passivation layer 19, and a drain electrode 20, as shown in fig. 7.
The second doped region 15 has a first conductivity type and is located at a first surface 111 of the epitaxial layer 11, the body region 16 has a second conductivity type and is located at a side of the second doped region 15 remote from the first surface 111, the dielectric layer 17 is located at a side of the epitaxial layer 11 remote from the substrate 10 and an orthographic projection of the dielectric layer 17 on the substrate 10 covers an orthographic projection of the gate structure 12 on the substrate 10, the source 18 is located at a side of the dielectric layer 17 remote from the epitaxial layer 11 and an orthographic projection of the source 18 on the substrate 10 is completely coincident with an orthographic projection of the substrate 10, the passivation layer 19 is located at a side of the source 18 remote from the epitaxial layer 11 and an orthographic projection of the passivation layer 19 on the substrate 10 covers an orthographic projection of the first doped region 14 on the substrate 10, and the drain 20 is located at a side of the substrate 10 remote from the epitaxial layer 11.
Specifically, the second doped region 15 and the body region 16 are disposed on two sides of the gate structure 12, wherein the conductivity type of the body region 16 is the same as the conductivity type of the first doped region 14, and the conductivity type of the second doped region 15 is different from the conductivity type of the body region 16. Illustratively, in the present embodiment, the body region 16 may be P-type in conductivity, and the second doped region 15 may be an N-type heavily doped region. The body region 16 is in contact with the first doped region 14 and is connected to the source 18 by the first doped region 14. The second doped region 15 serves as an active region of the semiconductor device and is in contact with the body region 16 to transmit an on-current. A dielectric layer 17 is disposed on the surface of the gate structure 12 such that the dielectric layer 17 covers the gate structure 12 and insulates the gate structure 12 from the source electrode 18. The drain electrode 20 is formed on the side of the substrate 10 remote from the epitaxial layer 11, i.e., on the back surface of the substrate 10, thereby obtaining a completed semiconductor device.
The embodiment of the invention also provides a preparation method of the semiconductor device. Fig. 8 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention, and fig. 9 is a schematic cross-sectional structure corresponding to each step in fig. 8. Referring to fig. 8 and 9, the method for manufacturing a semiconductor device specifically includes the following steps:
S110, providing a substrate 10, wherein the substrate 10 has a first conductivity type.
Illustratively, the substrate may be an N-type heavily doped silicon carbide base.
The epitaxial layer 11 is formed on the surface of the substrate 10, the epitaxial layer 11 has the first conductivity type, and the epitaxial layer 11 includes the first surface 111.
Illustratively, an N-type lightly doped silicon carbide epitaxial layer is epitaxially grown on a surface of the substrate, and a surface of the epitaxial layer on a side remote from the substrate is a first surface.
And S130, forming a buried layer structure 13 in the epitaxial layer 11, wherein the buried layer structure 13 comprises a first buried layer 131 and a second buried layer 132, the second buried layer 132 is of a first conductivity type, the first buried layer 131 is of a second conductivity type, the ion concentration of the second buried layer 132 is larger than that of the epitaxial layer 11, and the second buried layer 132 is configured to reduce the depletion region width between the first buried layer 131.
Illustratively, ion implantation is performed from the first surface of the epitaxial layer to the inside with corresponding conductive ions, thereby forming a first buried layer and a second buried layer with higher ion doping concentrations in the epitaxial layer. By arranging the first buried layer and the epitaxial layer to form a depletion region around the gate structure, a higher electric field around the gate structure can be shielded, the gate oxide layer is protected from being broken down easily, and the reliability of the semiconductor device is improved. The second buried layer with higher ion doping concentration is arranged at the same time of shielding a higher electric field around the grid structure, so that the width of the formed depletion region is reduced, the current conduction channels at two sides of the grid structure are guaranteed, and the on-state current of the semiconductor device is increased.
S140, a gate trench 112 is formed in the first surface 111.
Illustratively, the gate trench is formed by etching the first surface of the epitaxial layer inward.
S150, the gate structure 12 is formed inside the gate trench 112.
Illustratively, a silicon oxide material is deposited inside the gate trench, forming a gate oxide layer 121. And the polysilicon material is filled in the gate oxide layer to form the gate electrode 122.
In the method for manufacturing the semiconductor device, the first buried layer and the second buried layer which have higher ion doping concentration than the epitaxial layer are arranged in the epitaxial layer, so that a depletion region can be formed by the first buried layer and the epitaxial layer, a higher electric field in the middle of a grid structure is shielded, the reliability of the semiconductor device is improved, meanwhile, a depletion region with smaller width is formed by the second buried layer and the first buried layer, a sufficient conduction current transmission channel is ensured, and on-state current of the semiconductor device can be increased.
Optionally, on the basis of the above embodiment, the first buried layer includes a first buried sub-layer portion, a second buried sub-layer portion and a third buried sub-layer portion, the second buried layer includes a fourth buried sub-layer portion and a fifth buried sub-layer portion, fig. 10 is a schematic flowchart of step S130 in the semiconductor device manufacturing method according to the embodiment of the present invention, and fig. 11 is a schematic cross-sectional structure corresponding to each step in step S130. Forming a buried layer structure in the epitaxial layer in step S130 in combination with fig. 10 and 11 specifically includes the following steps:
S131, ion implantation is performed on the epitaxial layer 11 to form a third buried sub-layer portion 313.
Specifically, the first ion implantation is performed on the middle position of the surface of the epitaxial layer far away from the substrate side by adopting P-type conductive ions, and the ion implantation depth is deeper, so that a third buried layer part is formed.
And S132, performing ion implantation on the epitaxial layer 11 again to form a second buried sub-layer portion 312 and a fourth buried sub-layer portion 321, wherein the fourth buried sub-layer portion 321 is in contact with the second buried sub-layer portion 312, and the third buried sub-layer portion 313 is in contact with the second buried sub-layer portion 312 in the thickness direction of the substrate 10.
The second buried layer portion is formed by performing second ion implantation of P-type conductive ions at a middle position of the surface of the epitaxial layer far from the substrate side, and performing ion implantation of N-type conductive ions at a position other than the middle of the surface of the epitaxial layer far from the substrate side, thereby forming the fourth buried layer portion.
S133, the epitaxial layer 11 is formed again on the side of the second buried sub-layer portion 312 and the fourth buried sub-layer portion 321 away from the substrate 10.
And S134, performing ion implantation on the epitaxial layer 11 again to form a first sub-buried layer part 311 and a fifth sub-buried layer part 322, wherein the first sub-buried layer part 311 is in contact with the second sub-buried layer part 312, and the fifth sub-buried layer part 322 is in contact with the fourth sub-buried layer part 321.
The first buried sub-layer portion is formed by performing P-type ion implantation again from a position in the middle of the surface of the newly formed epitaxial layer, which is away from the substrate side, and the fifth buried sub-layer portion is formed by performing N-type ion implantation again from a position other than the middle of the surface.
S135, the epitaxial layer 11 is formed again on the side of the first buried sub-layer portion 311 and the fifth buried sub-layer portion 322 away from the substrate 10.
Illustratively, after the buried layer structure is prepared, an epitaxial layer is formed again on the surfaces of the first buried sub-layer portion and the fifth buried sub-layer portion, and the surface of the epitaxial layer, which is far from the substrate, is the first surface.
Alternatively, fig. 12 is a schematic cross-sectional structure corresponding to a step before forming the gate trench, and fig. 13 is a schematic cross-sectional structure corresponding to a step after forming the gate trench. On the basis of the above embodiments, referring to fig. 12 and 13, before forming the gate trench in the epitaxial layer, the method further includes:
The first surface 111 is ion-implanted to form a body region 16 and a second doped region 15, wherein the second doped region 15 is located on the first surface 111 of the epitaxial layer 11, and the body region 16 is located on a side of the second doped region 15 away from the first surface 111.
Illustratively, referring to fig. 12, ion implantation is performed on the first surface using P-type conductive ions, and the implantation depth is deeper, forming a body region. And then, carrying out ion implantation on the first surface by adopting N-type conductive ions, wherein the implantation depth is shallower, and forming a second doped region.
After forming the gate trench in the epitaxial layer, further comprising:
ion implantation is performed on the first surface 111 to form a first doped region 14, wherein the first doped region 14 is located on at least one side of the gate trench 112;
Specifically, ion implantation is performed on the first surface by adopting P-type conductive ions, and the implantation depth is deeper, so that a first doped region is formed on at least one side of the gate trench. Illustratively, fig. 13 shows a case where the first doped region is formed on both sides of the gate trench.
Optionally, fig. 14 is a schematic flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention, and fig. 15 is a schematic cross-sectional structure corresponding to step S160-step S190. On the basis of the above embodiments, in combination with fig. 14 and 15, the method for manufacturing a semiconductor device further includes the following steps:
and S160, forming a dielectric layer 17 on the side of the epitaxial layer 11 away from the substrate 10, wherein the orthographic projection of the dielectric layer 17 on the substrate 10 covers the orthographic projection of the gate structure 12 on the substrate 10.
Illustratively, a dielectric layer is formed on the first surface of the epitaxial layer using an insulating material deposition such that the dielectric layer covers the gate structure and exposes the first doped region to provide ohmic contact to the source.
And S170, forming a source electrode 18 on one side of the dielectric layer 17 away from the epitaxial layer 11, wherein the orthographic projection of the source electrode 18 on the substrate 10 is completely overlapped with the orthographic projection of the substrate 10.
Illustratively, a source is formed by depositing a metallic material on a surface of the dielectric layer.
And S180, forming a passivation layer 19 on the side of the source electrode 18 away from the epitaxial layer 11, wherein the orthographic projection of the passivation layer 19 on the substrate 10 covers the orthographic projection of the first doped region 14 on the substrate 10.
Illustratively, a silicon nitride material is deposited on the source surface, the silicon nitride 191 is etched to remain at the location corresponding to the first doped region, and a polyimide layer 192 is formed on the surface of the silicon nitride, surrounding the silicon nitride, forming a passivation layer.
And S190, forming a drain electrode 20 on the side of the substrate 10 away from the epitaxial layer 11.
Illustratively, a drain is formed by depositing a metallic material on the back side of the substrate.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
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| CN111668312A (en) * | 2020-06-15 | 2020-09-15 | 东南大学 | A trench silicon carbide power device with low on-resistance and its manufacturing process |
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