CN119420327A

CN119420327A - SiC MOSFET hard switching loss measurement method and system without current sensor

Info

Publication number: CN119420327A
Application number: CN202411402155.8A
Authority: CN
Inventors: 罗安; 魏伊杨; 徐千鸣; 胡家瑜; 徐百龙
Original assignee: Hunan University
Current assignee: Hunan University
Priority date: 2024-10-09
Filing date: 2024-10-09
Publication date: 2025-02-11

Abstract

The invention discloses a method and a system for measuring hard switching loss of a SiC MOSFET without a current sensor, on the basis of the double pulse measuring method, the current measurement is canceled, and the current waveform is obtained by analyzing the change characteristics of the voltage waveform. The drain-source voltage is very simple and convenient to measure, the layout and the volume of the converter are not affected, and the measurement time is very short. The method can be generalized to any topology with an equivalent half-bridge commutation loop.

Description

SiC MOSFET hard switching loss measurement method and system without current sensor

Technical Field

The invention relates to the technical field of power electronics, in particular to a method and a system for measuring hard switching loss of a SiC MOSFET without a current sensor.

Background

SiC MOSFETs have excellent electrical and thermal properties, lower switching losses and allow higher switching frequencies than Si devices, thereby reducing passive device size, achieving higher efficiency and power density, and making them widely used in automotive, aerospace and military applications. SiC devices remain a major source of power converter losses, with accurate assessment of the losses having a significant impact on the cooling system. The loss of the device is divided into conduction loss and switching loss, the conduction loss can be calculated by the conduction resistance given in a data manual, but the switching loss is not easy to obtain, and the switching loss is also influenced by parasitic parameters of a driving circuit, a complementary tube and a power circuit. Thus, even under the same conditions, the actual losses tend to differ, or even differ significantly, from the results given in the data manual.

There are two main current methods of measuring switching loss, namely, electrical measurement and thermal measurement. The electric measurement method mainly comprises the step of double pulse test, and is used for measuring the drain-source voltage and the drain-source current of the device. The switching loss is the integral of the voltage-current product calculated over a defined switching time. The method has the advantages of short measurement time and few additional peripheral devices. But has the disadvantage of requiring high bandwidth probes and oscilloscopes and correcting for the time delay between the voltage probe and the current probe due to the faster switching speed of SiC devices. The thermal measurement rule is to measure the heat dissipation of the device to be measured to determine the total loss thereof without measuring the transient process of the switch, so the bandwidth requirement on the measurement equipment is not high, but the accuracy of the thermal resistance network model and the conduction loss extraction is dependent, and the measurement time is long. The two methods have the common disadvantage that the loss measurement results are only applicable to the prototype used for testing and cannot be used in an actual power converter, since even if the switching devices are identical, the power and drive loops cannot be identical. It is not practical to build a test platform in an actual converter, a larger radiator is needed for heat measurement, no position is reserved for additional measuring equipment in the design process of the converter, and a current probe in electric measurement is limited by bandwidth and power device packaging, so that the coaxial shunt is a good choice, but is invasive, and extra parasitic inductance is introduced and an original power loop of the converter is changed.

Disclosure of Invention

The invention aims to solve the technical problem of providing a method and a system for measuring the hard switching loss of a SiC MOSFET without a current sensor, which are used for measuring the hard switching loss of a device under the condition of not influencing the volume of a converter and a power loop.

In order to solve the technical problems, the technical scheme adopted by the invention is that the hard switching loss measurement method of the SiC MOSFET without the current sensor adopts a double-pulse test platform for measurement, the double-pulse test platform comprises a half-bridge circuit, two ends of the half-bridge circuit are connected with a direct current source, the half-bridge circuit comprises two SiC MOSFETs which are connected in series in an in-phase manner, the SiC MOSFETs of an upper tube of the half-bridge circuit are connected with a load inductor in parallel, and the method comprises the following steps:

the SiC MOSFET hard turn-off loss was calculated using the following:

The SiC MOSFET hard turn-on loss was calculated using:

Wherein t _{vr_off} is the voltage rise time when the down tube is turned off, V _dc is the direct current source voltage, t _{vr_off} is the voltage rise time when the down tube is turned off, t _{cf_off} is the current rapid fall time when the down tube is turned off, V _dc is the direct current bus voltage, I _load is the load current at the moment of switching, and Q _oss1 is the charge amount stored in the upper tube junction capacitor;

tcr_on is the current rapid rise time when the half-bridge circuit down tube is turned on, t _{rr_on} is the reverse recovery time, t _{vf_on} is the voltage rapid fall time when the half-bridge circuit down tube is turned on, and DeltaV _max is the maximum value of the voltage on the parasitic inductance of the loop when the drain-source current rapidly rises during the hard turn-on period. The invention also provides a SiC MOSFET hard switching loss measurement system without the current sensor, which comprises a memory, a processor and a computer program stored on the memory, wherein the processor executes the computer program to realize the steps of the method.

Compared with the prior art, the invention has the beneficial effects that the influence of the measuring equipment on the overall layout and design of the converter can be reduced, and the time for measurement can be reduced. The invention cancels current measurement based on a double pulse measurement method, and obtains a current waveform by analyzing the change characteristics of the voltage waveform. The drain-source voltage is very simple and convenient to measure, the layout and the volume of the converter are not influenced, and the measurement time is very short.

Drawings

FIG. 1 is a schematic diagram of an equivalent circuit of a dual pulse test platform;

FIG. 2 (a) is a simplified schematic diagram of a hard shutdown process;

FIG. 2 (b) is a simplified schematic diagram of a hard-on process;

FIG. 2 (c) is a hard off process waveform;

FIG. 2 (d) is a hard-on process waveform;

FIG. 3 (a) is a simplified schematic diagram of a hard-off waveform;

FIG. 3 (b) is a simplified schematic diagram of a hard-on waveform;

FIG. 4 is an actual voltage waveform and its fitting function;

Fig. 5 (a) shows a comparison between the method and the experimental result under the working condition of R _g＝1Ω,I_ds＝20A,V_ds =500 to 800 v;

Fig. 5 (b) shows the comparison of the proposed method with experimental results under the working condition of R _g＝1Ω,I_ds＝5～20A,V_ds =800V;

fig. 5 (c) shows the comparison of the proposed method with experimental results under the working condition of R _g＝4.7Ω,I_ds＝5～20A,V_ds =800V;

Fig. 5 (d) is a comparison of the method proposed after increasing the parasitic inductance of the power loop with the experimental result, where R _g＝1Ω,I_ds＝5～20A,V_ds =800V;

fig. 5 (e) is a graph with R _g＝1Ω,I_ds＝15～60A,V_ds =800V, and the method proposed after replacing the device under test is compared with the experimental result.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The working principle of the proposed method is analyzed based on a double pulse test circuit:

The equivalent circuit of the double pulse test platform is shown in fig. 1, and includes a SiC device S ₁、S₂, a device package lead inductance L _s1、L_s2、L_d1、L_d2, a device junction capacitance C _ds1、C_ds2, a decoupling capacitance C _de and its parasitic inductance L _de, a PCB line inductance L _PCB(Dev-Dec)、L_PCB(Dec-Bus), a load inductance L _load, and a dc source V _dc. For convenience, the sum of L _PCB(Dev-Dec)、L_de、L_d1 and L _s1 will be replaced with L _σ as in formula (1) below. The drain-source voltage and drain-source current of the device under test are designated v _ds2 and i _ds2. The principle of the double pulse test is that two pulse driving signals are sent to a tested tube S ₂, a first pulse charges a load inductor to reach the specified current, and the hard switching characteristics of the device under the specified voltage and current can be obtained by observing the first pulse turn-off time and the second pulse turn-on time.

L_σ＝L_PCB(Dev-Dec)+L_de+L_d1+L_s1 (1)

A simplified schematic diagram of the hard shutdown process is shown in fig. 2 (a), and the corresponding voltage-current waveform is shown in fig. 2 (c).

Before t ₁, the lower tube S ₂ is conducted, the direct current source charges the load inductor, the load current linearly rises, and the set current value is reached at the moment t ₁.

Between t ₁ and t ₂, the load current is split into two parts, one part still flowing through the channel of S ₂ and charging the junction capacitance C _ds2, and the other part flowing through the junction capacitance C _ds1 of S ₁, causing the voltage across it to drop. At time t ₂ v _ds2 reaches the bus voltage and the charge on C _ds1 is completely discharged.

Between t ₂ and t ₃, the channel current of the lower tube S ₂ gradually decreases until the current is 0, and the body diode of the upper tube S ₁ is conducted, and the current gradually increases to the load current. The larger current change rate causes a larger voltage component on the loop parasitic inductance. This voltage is applied to S ₂ together with the DC bus voltage, resulting in a voltage overshoot on v _ds2 of the magnitude of

After t ₃, the load current is completely converted to the body diode of S ₁, the junction capacitor C _ds2 and the parasitic inductance of the loop generate high-frequency resonance, and the resonance frequency is

It is also noted that the equivalent circuit between the two points measured by the voltage probe is a series connection of the package lead inductance L _d2、L_s2 and the junction capacitance C _ds2. At the resonant frequency f _r, the whole is capacitive. The drain-source current i _ds2 leads the drain-source voltage v _ds2 by ninety degrees.

A simplified schematic diagram of the hard-on process is shown in fig. 2 (b), and the corresponding voltage-current waveform is shown in fig. 2 (d).

Prior to t ₄, the load inductor current freewheels through the body diode of upper tube S ₁.

Between t ₄ and t ₅, the channel of the lower tube S ₂ is conducted, the load current is gradually transferred from the body diode of S ₁, and a larger additional voltage component is generated on the parasitic inductance of the loop and is offset with the voltage of the direct current bus, so that the voltage of v _ds2 is lower than the voltage of the bus, and the expression is the same as that of the expression (2). At time t ₅ the load current is completely diverted.

Between t ₅ and t ₆, the charge stored in the body diode of S ₁ is discharged to form a reverse recovery current, which flows through S ₂ along with the load current, while the voltage v _ds2 across S ₂ remains high. The reverse recovery ends at time t ₆.

Between t ₆ and t ₇, the junction capacitance C _ds2 of S ₂ discharges through the self channel while the decoupling capacitance C _de charges the junction capacitance C _ds1 of S ₁. v _ds2 drops rapidly, dropping to zero at time t ₇.

After t ₇, the DC source continues to charge the load inductance while resonating with the loop parasitic inductance along with parasitic capacitance C _ds1.

At this time, the equivalent circuit between the two points measured by the voltage probe is the series connection of the package lead inductance L _d2、L_s2 and the on-resistance R _ds(on), and the resonance frequency is very high and the on-resistance is very small, so that the whole is close to pure inductance. The drain-source voltage v _ds2 leads the drain-source current i _ds2 by ninety degrees.

Through the analysis of the above-described commutation process, it can be found that the voltage and current variations at each stage are correlated. The current waveform can be obtained by analyzing the voltage waveform.

The loss measurement method according to the embodiment of the present invention is described based on the above-described commutation process analysis:

A staged function fit is performed on the voltage waveform and the current waveform. To simplify the fitting function, the abscissa zero point of each stage is established at its own starting point.

A simplified schematic of the hard off waveform is shown in fig. 3 (a).

In the phases t ₁ to t ₂, the load current charges C _ds2 and C _ds1 discharges, v _ds2 increases approximately linearly, i _ds2 is equal to the load current minus the discharge current to C _ds1, which decreases linearly with a small rate of change, and the area of the purple shaded portion in fig. 3 (a) is equal to the amount of charge stored by C _ds1, which can be obtained from the data manual. The voltage and current fitting function expression and the loss are as follows

Where t _{vr_off} is the voltage rise time at turn-off, which can be approximately considered to be the time taken for V _ds2 to go from 5% to 100% V _dc.

In the phases t ₂ to t ₃, V _ds2 ignores the oscillating voltage, and the approximate dc-side voltage V _dc.i_ds2 decreases linearly to zero with a large rate of change. The voltage-current function expression and the loss are as follows

Where t _{cf_off} is the fast drop time of the channel current at turn-off, which can be considered the time taken to drop to zero from the end of t _{vr_off} to i _ds2. However, since the current waveform is not actually obtained, it is necessary to find the current zero-crossing point by the voltage characteristic. The above-mentioned loop parasitic inductance and junction capacitance C _ds2 resonate after time t ₃ (i.e., the channel is completely off). Therefore, the first valley of the voltage oscillation waveform is a half resonance period before, and the first valley is a zero crossing point of the corresponding current.

The hard turn-off loss is calculated as

A simplified schematic of the hard-on waveform is shown in fig. 3 (b).

At the stages t ₄ to t ₅, the load current rapidly transfers to the S ₂ channel, and i _ds2 rises approximately linearly. The voltage drop across the loop parasitic inductance is Δv (t). The voltage-current function expression and the loss are as follows

Where t _{cr_on} is the channel current fast rise time of S ₂ when on, it can be considered the time taken from V _dc where V _ds2 equals 95% to i _ds2 equals the load current. The moment i _ds2 reaches the load current also needs to be obtained by the voltage variation feature. Decoupling capacitors typically use ceramic or thin film capacitors with small parasitic inductances and are placed close to the half bridge. L _σ is therefore approximately equal to L _s1+L_d1. According to the principle of conservation of magnetic flux, the integral of DeltaV (t) over time is equal to the product of L _σ and I _load. Solving t _{cr_on} according to the simultaneous equation, as follows

In the stages t ₅ to t ₆, the body diode reverse bias of S ₁ is subjected to a small reverse voltage, releasing the charge stored in forward conduction, and the voltage of S ₂ remains at V _dc-ΔV_max anyway. At the stages t ₆ to t ₇, the reverse recovery of S ₁ is completed, the charge current of the junction capacitor C _ds1 and the load current flow through the channel of S ₂ in superposition, the charge on the junction capacitor C _ds2 is released through the internal channel of S ₂, and v _ds2 drops approximately linearly. Since the reverse recovery current is small, the phases t ₅ to t ₇ only consider charging the junction capacitance C _ds1 with current. From the actual waveform, it can be seen that the phase i _ds2 approximates to a sine wave with half period superimposed by the DC component, and the current fitting function expression is

The actual voltage waveform approximates to the upper bottom and waist of a right trapezoid, which is relatively close to a cubic function, as shown in fig. 4. In order to reduce the number of coefficients to be determined in the fitting function, the center of symmetry of the cubic function falls on the ordinate axis. The cubic function passes through two points (0, V _dc-ΔV_max) and (t _{rr_on}+t_{vf_on}, 0), and the slope of the cubic function is equal to zero at the time t _{rr_on}, so that the simultaneous equation (10) can be obtained. The undetermined coefficient is obtained as formula (11).

The loss expression from the stage t ₅ to the stage t ₇ is

Where t _{rr_on}、t_{vf_on} is the reverse recovery time and v _ds2 fast fall time, respectively. t _{rr_on} may be considered the time taken for a sudden drop from the end of t _{cr_on} to V _ds2 and t _{vf_on} may be considered the time taken for a sudden drop from V _ds2 to V _dc where V _ds2 is equal to 5%.

The hard turn-on loss is calculated as

It can be seen from the hard off and hard on loss calculation expressions that the variables V _dc and I _load are determined by the actual conditions, the variable Q _oss1 is provided by the device data manual, and the remaining other variables are obtained entirely from the voltage measurements without the need for current sensors.

As shown in fig. 5, the experimental result shows that the SiC MOSFET hard switching loss measurement method without using a current probe and without affecting the volume and layout of the converter can be used for measuring the hard switching loss of the device. The measurement error of the total loss is within 5 percent, thereby meeting the precision requirement.

Example 2

Embodiment 2 of the present invention provides a measurement system corresponding to embodiment 1 above, where the measurement system may be a processing device for a client, such as a mobile phone, a notebook computer, a tablet computer, a desktop computer, etc., to execute the method of the embodiment above.

The measuring system of the present embodiment includes a memory, a processor and a computer program stored on the memory, the processor executing the computer program on the memory to implement the steps of the method of embodiment 1 described above.

In some implementations, the memory may be a high-speed random access memory (RAM: random Access Memory), and may also include non-volatile memory (non-volatile memory), such as at least one disk memory.

In other implementations, the processor may be a Central Processing Unit (CPU), a Digital Signal Processor (DSP), or other general-purpose processor, which is not limited herein.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A hard switching loss measurement method of a SiC MOSFET without a current sensor adopts a double-pulse test platform for measurement, wherein the double-pulse test platform comprises a half-bridge circuit, two ends of the half-bridge circuit are connected with a direct current source, the half-bridge circuit comprises two SiC MOSFETs which are connected in series in an in-phase manner, and a pipe SiCMOSFET on the half-bridge circuit is connected with a load inductor in parallel, and the method is characterized by comprising the following steps:

the SiC MOSFET hard turn-off loss was calculated using the following:

The SiC MOSFET hard turn-on loss was calculated using:

Wherein t _{vr_off} is the voltage rise time at turn-off, V _dc is the dc source voltage,

Wherein t _{vr_off} is the voltage rising time when the lower tube is turned off, t _{cf_off} is the current rapid falling time when the lower tube is turned off, V _dc is the DC bus voltage, I _load is the load current at the moment of switching, and Q _oss1 is the charge amount stored by the upper tube junction capacitor;

t _{cr_on} is the current rapid rise time when the half-bridge circuit down tube is turned on, t _{rr_on} is the reverse recovery time, t _{vf_on} is the voltage rapid fall time when the half-bridge circuit down tube is turned on, and DeltaV _max is the maximum value of the voltage on the loop parasitic inductance when the drain-source current rapidly rises during the hard turn-on period.

2. The method for measuring hard switching loss of a SiC MOSFET without a current sensor according to claim 1, wherein t _{vr_off} is the time taken for v _ds2 to reach from 5% V _dc to 100% V _dc, and v _ds2 is the drain-source voltage of the lower tube.

3. The method for measuring hard switching loss of a SiC MOSFET without a current sensor according to claim 1 or 2, wherein t _{cf_off} is the time taken from the end of t _{vr_off} to the drop of the down tube drain-source current i _ds2 to zero.

4. A method for measuring hard switching loss of a SiC MOSFET without a current sensor according to any one of claims 1 to 3, wherein t _{rr_on} is the time taken from the end of t _{cr_on} to the beginning of the drop in drain-source voltage v _ds2 of the down tube, and t _{vf_on} is the time taken from the beginning of the drop in drain-source voltage v _ds2 of the down tube to v _ds2 being equal to 5% v _dc.

5. The method for measuring hard switching loss of a SiC MOSFET without a current sensor according to claim 1, wherein t _{cr_on} is the time taken for the drain-source voltage v _ds2 of the lower tube to be equal to 95% v _dc to the drain-source current i _ds2 of the lower tube to be equal to the load current.

6. A SiC MOSFET hard switching loss measurement system without a current sensor, comprising a memory, a processor and a computer program stored on the memory, characterized in that the processor executes the computer program to implement the steps of the method according to one of claims 1 to 5.