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CN119401813A - An intelligent power module with integrated adaptive dead zone function - Google Patents

An intelligent power module with integrated adaptive dead zone function Download PDF

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Publication number
CN119401813A
CN119401813A CN202411978156.7A CN202411978156A CN119401813A CN 119401813 A CN119401813 A CN 119401813A CN 202411978156 A CN202411978156 A CN 202411978156A CN 119401813 A CN119401813 A CN 119401813A
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CN
China
Prior art keywords
circuit
gate
input end
output end
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202411978156.7A
Other languages
Chinese (zh)
Inventor
李强
欧阳高勋
冯宇翔
谢荣才
区肇栋
区子平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Sanhua Vanadium Technology Co ltd
Foshan Voyin Technology Co ltd
Guangdong Huixin Semiconductor Co Ltd
Original Assignee
Guangdong Sanhua Vanadium Technology Co ltd
Foshan Voyin Technology Co ltd
Guangdong Huixin Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong Sanhua Vanadium Technology Co ltd, Foshan Voyin Technology Co ltd, Guangdong Huixin Semiconductor Co Ltd filed Critical Guangdong Sanhua Vanadium Technology Co ltd
Priority to CN202411978156.7A priority Critical patent/CN119401813A/en
Publication of CN119401813A publication Critical patent/CN119401813A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0048—Circuits or arrangements for reducing losses
    • H02M1/0054—Transistor switching losses
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H10W70/611—
    • H10W70/65—
    • H10W72/50—

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)

Abstract

The invention relates to the technical field of intelligent power modules, and provides an intelligent power module integrating a self-adaptive dead zone function, which comprises a shell, a circuit aluminum substrate arranged in the shell, an insulating layer arranged on the upper surface of the circuit aluminum substrate, circuit wiring formed on the upper surface of the insulating layer, a plurality of circuit elements arranged on the circuit wiring and a plurality of pins, wherein the circuit aluminum substrate is arranged on the shell; the circuit elements are electrically connected with the circuit wiring through metal wires, one ends of the pins are connected with the circuit wiring, the other ends of the pins extend out of the shell, and the circuit aluminum substrate is integrated with a self-adaptive dead zone circuit. The intelligent power module can reduce switching loss and realize higher efficiency, so that the intelligent power module improves stability and reliability.

Description

Intelligent power module integrating self-adaptive dead zone function
Technical Field
The invention relates to the technical field of intelligent power modules, in particular to an intelligent power module integrated with a self-adaptive dead zone function.
Background
The smart power module, IPM (Intelligent Power Module), is a power driven product that combines power electronics and integrated circuit technology. The intelligent power module integrates the power switch device and the high-voltage driving circuit and is internally provided with fault detection circuits such as overvoltage, overcurrent, overheat and the like. The intelligent power module receives the control signal of the MCU on one hand, drives the subsequent circuit to work, and sends the state detection signal of the system back to the MCU on the other hand. Compared with the traditional discrete scheme, the intelligent power module gains larger and larger markets by virtue of the advantages of high integration level, high reliability and the like, is particularly suitable for a frequency converter of a driving motor and various inverter power supplies, and is an ideal power electronic device for frequency conversion speed regulation, metallurgical machinery, electric traction, servo driving and frequency conversion household appliances.
The HVIC anti-pass dead time technology inside the conventional intelligent power module inserts a fixed dead time between the high and low voltage side outputs to prevent the high and low voltage side pass through, and the high and low voltage side input signals are signals with completely complementary logic and enter the fixed dead time generation module after being processed by the input logic module. And a certain dead zone is produced between HO and LO which are output after passing through the high-low voltage side channel, so that the direct connection problem caused by the simultaneous opening of the high-low voltage side power tube is avoided. In practical applications, the on and off time of the power tube will vary with the input voltage, temperature and load current, so the setting of the fixed dead time is considered according to the worst case through, and therefore the dead time often has a sufficiently long margin in general condition applications. Dead time is set too short, so that a through phenomenon can be caused along with the change of the application environment of the system, and the reliability of the system is affected. Dead time is set too long, so that a short current blank period appears in the circuit when the switching tube is switched, and voltage and power are in an idle state in the period, so that certain power loss is caused, the efficiency of the circuit and the quality of an output waveform are reduced, the power loss is increased, the switching tube is possibly damaged, and the stability of the circuit is affected.
Therefore, the intelligent power module has large power loss, low efficiency and poor output waveform quality during working, and can damage a switching tube to influence the stability of a circuit.
Disclosure of Invention
The invention provides an intelligent power module integrating a self-adaptive dead zone function, and aims to solve the problems that the existing intelligent power module is large in power loss, low in efficiency and poor in output waveform quality when working, and a switching tube is possibly damaged to influence circuit stability.
The embodiment of the invention provides an intelligent power module integrating a self-adaptive dead zone function, which comprises a shell, a circuit aluminum substrate arranged in the shell, an insulating layer arranged on the upper surface of the circuit aluminum substrate, circuit wiring formed on the upper surface of the insulating layer, a plurality of circuit elements and a plurality of pins, wherein the circuit elements are arranged on the circuit wiring, the circuit elements are electrically connected with the circuit wiring through metal wires, one ends of the pins are connected with the circuit wiring, and the other ends of the pins extend out of the shell, and the self-adaptive dead zone circuit is integrated on the circuit aluminum substrate.
Preferably, the circuit aluminum substrate has an uneven texture inside.
Preferably, the self-adaptive dead zone circuit comprises a first input stage circuit, a delay circuit, a second input stage circuit, a dynamic dead zone generating circuit, a pulse generating circuit, a level shifting circuit, a first amplifier, a negative pressure detection circuit, a low side delay circuit, a second amplifier, a current protection circuit, a fault output circuit, an undervoltage protection circuit and a fault logic control circuit, wherein the input end of the first input stage circuit is connected with the input end of the second input stage circuit and is commonly used for connecting a signal input end, the output end of the first input stage circuit and the output end of the second input stage circuit are respectively connected to the input end of the dynamic dead zone generating circuit, the output end of the dynamic dead zone generating circuit is respectively connected with the input end of the pulse generating circuit and the input end of the low side delay circuit, the output end of the pulse generating circuit is connected with the input end of the level shifting circuit, the output end of the level shifting circuit is connected with the input end of the first amplifier, the output end of the low side delay circuit is connected with the input end of the second amplifier, the output end of the first amplifier is connected with the output end of the undervoltage protection circuit, the output end of the first amplifier is connected with the input end of the low side delay circuit, the output end of the first amplifier is used for connecting the signal input end of the second amplifier, the output end of the first amplifier is connected with the fault circuit is connected with the input end of the fault circuit, the output end of the fault circuit is used for the fault protection circuit, the output end is connected with the input end of the fault circuit respectively, and the input end of the input circuit is connected with the input circuit respectively, and the output end of the undervoltage protection circuit is connected with the input end of the fault logic control circuit.
Preferably, the delay circuit comprises a first dynamic delay unit and a second dynamic delay unit, wherein the input end of the first dynamic delay unit and the input end of the second dynamic delay unit are connected and jointly serve as the input end of the delay circuit, and the output end of the first dynamic delay unit and the output end of the second dynamic delay unit serve as the output end of the delay circuit respectively.
Preferably, the dynamic dead zone generating circuit comprises a first NOT gate, a first NAND gate, a first NOR gate, a second NOT gate, a second NAND gate and a second NOR gate;
the input end of the first NOT gate is connected with the input end of the first dynamic delay unit, the output end of the first NOT gate is respectively connected with the first end of the first NOT gate and the first end of the first NOT gate, and the second end of the first NOT gate is used as the first input end of the dynamic dead zone generating circuit and is connected to the output end of the first dynamic delay unit;
The input end of the second NOT gate is connected with the input end of the second dynamic delay unit, the output end of the second NOT gate is respectively connected with the first end of the second NOT gate and the first end of the second NOT gate, and the second end of the second NOT gate is used as the second input end of the dynamic dead zone generating circuit and is connected to the output end of the second dynamic delay unit;
The output end of the first NAND gate is connected with the second end of the second NAND gate, the output end of the second NAND gate is connected with the second end of the first NAND gate, the output end of the first NAND gate is connected with the input end of the pulse generating circuit, and the output end of the second NAND gate is connected with the input end of the low-side delay circuit.
Preferably, the circuit structures of the first dynamic delay unit and the second dynamic delay unit are the same.
Preferably, the first dynamic delay unit comprises a trigger, a data selector, an up-down counter, a binary delay line, an AND gate, a third NAND gate, a third NOR gate, a fourth NOR gate and a third NOR gate;
The input end of the trigger is used for being connected with the output end of the negative pressure detection circuit, the output end of the trigger is connected with the X1 input end of the alternative data selector, the output end of the alternative data selector is connected with the control end of the up-down counter, the output end of the up-down counter is connected with the input end of the binary delay line, and the output end of the binary delay line is used as the output end of the first dynamic delay unit;
The output end of the third NAND gate is connected with the CLK port of the up-down counter, the input end of the third NAND gate is used for being connected with a signal input end, the output end of the third NAND gate is respectively connected with the first input end of the fourth NAND gate and the first input end of the third NAND gate, the output end of the fourth NAND gate is respectively connected with the second input end of the first NAND gate and the S input end of the alternative data selector, the output end of the third NAND gate is connected with the X0 input end of the alternative data selector, the input end of the AND gate is used for being connected with the signal input end, and the output end of the AND gate is connected with the second input end of the fourth NAND gate.
Preferably, the binary delay line comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube and a second capacitor;
the drain electrode of the first PMOS tube is used for being connected with the power supply, the grid electrode of the first PMOS tube is connected with the grid electrode of the first NMOS tube and is used as the input end of the binary delay line together, and the drain electrode of the first NMOS tube is respectively connected with the first end of the first resistor and the source electrode of the second NMOS tube and is used as the output end of the binary delay line;
The source electrode of the first NMOS tube is connected with the first end of the second capacitor and grounded, and the second end of the second capacitor is connected with the drain electrode of the first NMOS tube;
The drain electrode of the second NMOS tube is respectively connected with the second end of the first resistor, the first end of the second resistor and the source electrode of the third NMOS tube, the drain electrode of the third NMOS tube is respectively connected with the second end of the second resistor, the first end of the third resistor and the source electrode of the fourth NMOS tube, the drain electrode of the fourth NMOS tube is respectively connected with the second end of the third resistor, the first end of the fourth resistor and the source electrode of the fifth NMOS tube, the drain electrode of the fifth NMOS tube is respectively connected with the second end of the fourth resistor, the first end of the fifth resistor and the source electrode of the sixth NMOS tube, and the drain electrode of the sixth NMOS tube is respectively connected with the second end of the fifth resistor and the source electrode of the first PMOS tube;
the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube, the grid electrode of the fourth NMOS tube, the grid electrode of the fifth NMOS tube and the grid electrode of the sixth NMOS tube are respectively connected with the input end of the third NOR gate.
The CLK end of the D trigger is respectively connected with the CLK ends of the four JK triggers, the Reset end of the D trigger is respectively connected with the Reset ends of the four JK triggers, and the Q end of the D trigger and the Q end of the four JK triggers are respectively suspended;
The logic gate circuit comprises a fourth NAND gate, an OR gate and a fifth NAND gate;
The output end of the fourth NAND gate is respectively connected with the J end and the K end of the JK trigger, the first input end of the fourth NAND gate is connected with the output end of the OR gate, and the second input end of the fourth NAND gate is connected with the output end of the fifth NAND gate;
The first input end of the OR gate is connected with the first input end of the fifth NAND gate and connected to the D end of the D trigger, and the second input end of the OR gate is connected with the second input end of the fifth NAND gate and connected to the signal input end.
Compared with the prior art, the self-adaptive dead zone circuit has the beneficial effects that the shell, the circuit aluminum substrate arranged in the shell, the insulating layer arranged on the upper surface of the circuit aluminum substrate, the circuit wiring formed on the upper surface of the insulating layer, the circuit elements and the pins mounted on the circuit wiring are electrically connected with the circuit wiring through metal wires, one ends of the pins are connected with the circuit wiring, and the other ends of the pins extend out of the shell, wherein the circuit aluminum substrate is integrated with the self-adaptive dead zone circuit. Therefore, the intelligent power module can work in the optimal state by adjusting the dead time of the module in real time through the self-adaptive dead time circuit, the power loss of the system is reduced, the efficiency of the system circuit and the quality of output waveforms are improved, the switching device GaNFET has extremely low Qrr and extremely rapid switching, the switching loss can be reduced, the higher efficiency is realized, and the stability and the reliability of the intelligent power module are improved.
Drawings
The present invention will be described in detail with reference to the accompanying drawings. The foregoing and other aspects of the invention will become more apparent and more readily appreciated from the following detailed description taken in conjunction with the accompanying drawings. In the accompanying drawings:
fig. 1 is a schematic structural diagram of an intelligent power module integrated with an adaptive dead zone function according to an embodiment of the present invention;
fig. 2is a schematic structural diagram of a pin of an intelligent power module integrated with an adaptive dead zone function according to an embodiment of the present invention;
FIG. 3 is a top view of an intelligent power module integrated with adaptive dead zone functionality provided by an embodiment of the present invention;
FIG. 4 is a circuit diagram of an adaptive dead zone circuit provided by an embodiment of the present invention;
FIG. 5 is a circuit diagram of a dynamic dead zone generation circuit provided by an embodiment of the present invention;
FIG. 6 is a waveform diagram of each node of the dynamic dead zone generation circuit provided by an embodiment of the present invention;
FIG. 7 is a circuit diagram of a first dynamic delay circuit provided by an embodiment of the present invention;
FIG. 8 is a schematic diagram of the workflow of a dynamic delay unit provided by an embodiment of the present invention;
FIG. 9 is a circuit diagram of a binary delay line provided by an embodiment of the present invention;
FIG. 10 is a circuit diagram of an up-down counter provided by an embodiment of the present invention;
fig. 11 is a schematic diagram of simulation results of a dynamic delay unit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
Referring to fig. 1-11, an embodiment of the present invention provides an intelligent power module 22 integrated with a dead zone function, which includes a housing 31, an aluminum circuit substrate 23 disposed in the housing 31, an insulating layer 24 disposed on an upper surface of the aluminum circuit substrate 23, a circuit wiring 25 formed on an upper surface of the insulating layer 24, a plurality of circuit elements 27 mounted on the circuit wiring 25, and a plurality of pins 29, wherein the circuit elements 27 and the circuit wiring 25 are electrically connected through metal wires 28, one ends of the pins 29 are connected to the circuit wiring 25, and the other ends of the pins 29 extend out of the housing 31, and the aluminum circuit substrate 23 is integrated with the dead zone circuit. Thus, the intelligent power module 22 adjusts the dead time of the module in real time through the self-adaptive dead time circuit, so that the module works in an optimal state, the power loss of the system is reduced, the efficiency of the system circuit and the quality of output waveforms are improved, and the switching device GaNFET has extremely low Qrr and extremely rapid switching, so that the switching loss can be reduced, and higher efficiency is realized.
In this embodiment, the circuit aluminum substrate 23 has an uneven texture 26 inside.
In the embodiment, the intelligent power module 22 of which the switching device adopts the GaNFET has a structure comprising a circuit aluminum substrate 23, a circuit wiring 25 formed on an insulating layer 24 arranged on the surface of the circuit aluminum substrate 23, a rugged texture 26 arranged on the back surface of the circuit aluminum substrate 23, a circuit element 27 fixed on the circuit wiring 25, a metal wire 28 connecting the circuit element 27 and the circuit wiring 25, a pin 29 connected with the circuit wiring 25, and the rest part covered by a plating layer, wherein the whole of the intelligent power module 30 is sealed by a sealing resin 31.
The manufacturing method of the intelligent power module 22, wherein the switching device adopts GaNFET, is as follows:
forming the texture 26 on the back surface of the circuit board 23 by laser etching, polishing, or the like using an aluminum material having a proper size, providing the insulating layer 24 on the surface of the circuit board 23, forming a copper foil on the insulating layer 24, and forming the circuit wiring 25 by etching the copper foil;
Coating solder paste on specific positions of the circuit wiring 25;
forming a copper material into a proper shape and performing surface plating treatment as the leads 29, wherein specific positions of the leads 29 are connected by reinforcing ribs 33 in order to prevent the circuit element 27 from being electrostatically damaged in a subsequent processing step;
Placing the circuit element 27 and the pins 29 on a solder paste;
Solidifying the solder paste by reflow soldering, the circuit element 27 and the pins 29 being fixed on the circuit wiring 25;
cleaning the residual soldering flux on the circuit substrate 23 by spraying, ultrasonic and other cleaning modes;
A connection is formed between the circuit element 27 and the circuit wiring 25 by bonding wires;
if the circuit board 23 needs to be connected to the ground potential, the method further comprises a step of turning through the insulating layer 24 through a turning hole and forming connection between the ground potential of the circuit wiring 25 and the circuit board 23 through a bonding wire;
sealing the above elements by injection molding using a thermoplastic resin or transfer molding using a thermosetting resin;
Cutting out the reinforcing ribs 33 of the pins 29 and forming a desired shape;
the test qualifier becomes the internal integrated adaptive dead time circuit by performing the necessary tests with the test equipment and the switching device is a smart power module 22 employing a GaNFET.
In the embodiment, the self-adaptive dead zone circuit comprises a first input stage circuit 1, a delay circuit 2, a second input stage circuit 3, a dynamic dead zone generating circuit 4, a pulse generating circuit 5, a level shifting circuit 6, a first amplifier 7, a negative voltage detecting circuit 8, a low-side delay circuit 9, a second amplifier 10, a current protection circuit 11, a fault output circuit 12, an undervoltage protection circuit 13 and a fault logic control circuit 14; the input end of the first input stage circuit 1 is connected with the input end of the second input stage circuit 3 and is commonly used for connecting a signal input end, the output end of the first input stage circuit 1 and the output end of the second input stage circuit 3 are respectively connected to the input end of the dynamic dead zone generating circuit 4, the output end of the dynamic dead zone generating circuit 4 is respectively connected with the input end of the pulse generating circuit 5 and the input end of the low-side delay circuit 9, the output end of the pulse generating circuit 5 is connected with the input end of the level shifting circuit 6, the output end of the level shifting circuit 6 is connected with the input end of the first amplifier 7, the output end of the low-side delay circuit 9 is connected with the input end of the second amplifier 10, the output end of the first amplifier 7 and the input end of the second amplifier 10 are respectively connected to the signal output end, the input end of the current protecting circuit 11 is used for connecting ITRIP ports, the output end of the current protecting circuit 11 is connected with the input end of the fault logic control circuit 14, the output end of the fault control circuit 14 is connected with the input end of the first amplifier 10 and the input end of the second amplifier 10 respectively, the output end of the fault output circuit 12 is used for outputting a fault signal, the input end of the undervoltage protection circuit 13 is used for being connected with a power supply, and the output end of the undervoltage protection circuit 13 is connected with the input end of the fault logic control circuit 14.
The first input stage circuit 1 and the second input stage circuit 3 are the same and generally include an RC filter, a schmitt circuit, a filter, a level shift circuit, and the like, which are connected in order.
Thus, the state of the voltage at the Vs terminal is monitored by the step-type adaptive dead zone circuit by using the negative voltage detection circuit 8 to determine the adjustment direction of the delay time for generating the dead zone, and the delay signals HO' of LO and out_h are used as clocks for reading and latching the output signals of the negative voltage detection circuit 8, so that the dead time adjustment is performed in real time. The HVIC is operated with an optimal dead time, thereby improving the reliability of the HVIC.
The self-adaptive dead time circuit is composed of a dynamic dead time generating circuit 4, a delay circuit 2 and a VS negative pressure detecting circuit 8, wherein the state of the voltage at the Vs terminal is monitored by adopting the negative pressure detecting circuit 8 so as to determine the adjusting direction of the delay time used for generating dead time, and delay signals HO' of LO and OUT_H are used as clocks for reading and latching the output signals of the negative pressure detecting circuit 8, so that real-time dead time adjustment is carried OUT.
The first transistor Q1 and the second transistor Q2 are switching devices of a basic Buck converter, and the first inductor L1, the first capacitor C1, and the first resistor R1 are loads of the Buck converter.
In this embodiment, the delay circuit 2 includes a first dynamic delay unit 0304 and a second dynamic delay unit 0305, where an input end of the first dynamic delay unit 0304 and an input end of the second dynamic delay unit 0305 are connected and jointly serve as input ends of the delay circuit 2, and an output end of the first dynamic delay unit 0304 and an output end of the second dynamic delay unit 0305 are respectively used as output ends of the delay circuit 2.
In this embodiment, the dynamic dead zone generating circuit 4 includes a first NOT gate 0301, a first NAND gate 0302, a first NOR gate 0303, a second NOT gate 0306, a second NAND gate 0307, and a second NOR gate 0308;
The input end of the first NAND gate 0301 is connected with the input end of the first dynamic delay unit 0304, the output end of the first NAND gate 0301 is respectively connected with the first end of the first NAND gate 0302 and the first end of the first NOR gate 0303, and the second end of the first NAND gate 0302 is used as the first input end of the dynamic dead zone generating circuit 4 and is connected to the output end of the first dynamic delay unit 0304;
The input end of the second NOT gate 0306 is connected with the input end of the second dynamic delay unit 0305, the output end of the second NOT gate 0306 is respectively connected with the first end of the second NOT gate 0307 and the first end of the second NOT gate 0308, and the second end of the second NOT gate 0306 is used as the second input end of the dynamic dead zone generating circuit 4 to be connected with the output end of the second dynamic delay unit 0305;
The output end of the first nor gate 0302 is connected to the second end of the second nor gate 0308, the output end of the second nor gate 0307 is connected to the second end of the first nor gate 0303, the output end of the first nor gate 0303 is connected to the input end of the pulse generating circuit 5, and the output end of the second nor gate 0308 is connected to the input end of the low-side delay circuit 9.
Specifically, in_h is simultaneously connected to the input terminal of the first nor gate 0301 and the input terminal IN of the first dynamic delay cell 0304, and the output terminal of the first nor gate 0301 and one input terminal of the first nand gate 0302 are connected to the input terminal of the first nor gate 0303, denoted as a.
The output OUT of the first dynamic delay cell 0304 is connected to the other input of the first nand gate 0302, denoted C1.
The output of the first nor gate 0303 is out_h.
An output of the first NAND gate 0302 is connected to an input of a second NAND gate 0308, denoted A1.
In_l is simultaneously connected to the input of the second not gate 0306 and the input IN of the second dynamic delay element 0305, the output of the second not gate 0306, one input of the second nand gate 0307 being connected to the input of the second nor gate 0308, denoted B.
The output OUT of the second dynamic delay cell 0305 is connected to the other input of the second nand gate 0307, denoted C2.
An output of the second nand gate 0307 is connected to an input of the first nor gate 0303, denoted B1.
The output of the second nor gate 0308 is out_l.
The input end A of the first dynamic delay unit 0304 and the input end A of the second dynamic delay unit 0305 are connected with an output signal ND of the Vs negative pressure sampling detection circuit, the CLK input end of the first dynamic delay unit 0304 is connected with HO', and the CLK input end of the second dynamic delay unit 0305 is connected with LO.
The operation principle of the adaptive dead zone circuit will be described below with reference to waveforms of respective nodes shown in fig. 7. First, if there is overlap between the input signals of the two input terminals in_h and in_l of the chip, the dead zone circuit forces out_h and out_l to be zero IN the overlap region, so as to ensure that the output signals are normal, and a certain dead zone time is added. For more specific illustration, the input signals in_h and in_l are here two square wave signals which are interleaved with each other. The C1 signal is an output signal of in_h after passing through a dynamic delay unit, which delays only a falling edge of an input signal and outputs an inverted signal. Accordingly, the falling edge of in_h is delayed, outputted as an A1 signal, and used to control the on time of the low side channel. Similarly, B1 is a falling edge delay output signal of in_l for controlling the turn-on time of the high side channel. Finally, the inverted signal A and the inverted signal B1 of the IN_H or the non-post output signal turn on the high-voltage side power transistor Q1, and form dead time between the turn-off of the low-voltage side power device Q2 and the turn-on of the high-voltage side power device Q1, and the inverted signal B and the inverted signal A1 of the IN_L or the non-post output signal turn on the low-voltage side power device Q2, and form dead time between the turn-off of the high-voltage side power device Q1 and the turn-on of the low-voltage side power device Q2.
In this embodiment, the circuit structure of the first dynamic delay unit 0304 is the same as that of the second dynamic delay unit 0305.
In this embodiment, the first dynamic delay unit 0304 includes a flip-flop 12, a data selector 13, an up-down counter 14, a binary delay line 15, an AND gate AND1, a third NAND gate NAND1, a third NOR gate NOR1, a fourth NOR gate NOR2, AND a third NOR gate INV1;
The input end of the trigger 12 is used for connecting with the output end of the negative pressure detection circuit 8, the output end of the trigger 12 is connected with the X1 input end of the alternative data selector 13, the output end of the alternative data selector 13 is connected with the control end of the up-down counter 14, the output end of the up-down counter 14 is connected with the input end of the binary delay line 15, and the output end of the binary delay line 15 is used as the output end of the first dynamic delay unit 0304;
The output end of the third NOR gate INV1 is connected to the CLK port of the up-down counter 14, the input end of the third NOR gate NOR1 is used for connecting to a signal input end, the output end of the third NOR gate NOR1 is respectively connected to the first input end of the fourth NOR gate NOR2 AND the first input end of the third NOR gate NAND1, the output end of the fourth NOR gate NOR2 is respectively connected to the second input end of the first NAND gate 0302 AND the S input end of the second or first data selector 13, the output end of the third NAND gate NAND1 is connected to the X0 input end of the second or first data selector 13, the input end of the AND gate AND1 is used for connecting to the signal input end, AND the output end of the AND gate AND1 is connected to the second input end of the fourth NOR gate NOR 2.
Specifically, the stepped dynamic delay unit is a core component of the whole self-adaptive dead zone circuit, and the self-adaptation of dead zone time changing along with the change of working state is determined by the dynamic adjustment process. A detailed circuit diagram of the dynamic delay cell is shown in fig. 7, comprising a D flip-flop 12, a one-out-of-two data selector 13, a 5bit up-down counter 14, a binary delay line 15 and logic circuitry.
The input end of the D trigger 12 is an input end A of a dynamic delay unit, the input end A of the dynamic delay unit is connected with an output signal ND of a Vs negative pressure sampling detection circuit in the number shown in the figure 5, the output end Q of the D trigger 12 is connected with an input end X1 of a NOR-type data selector MUX1, the input CLK of the D trigger 12 is LO AND HO' in the number shown in the figure 5, the input ends of the 5 NOR-type gates NOR1 are respectively connected with Q0, Q1, Q2, Q3 AND Q4, the input ends of the 5 AND-type gates AND1 are respectively connected with Q0, Q1, Q2, Q3 AND Q4, the output end of the 5 NOR-type gates NOR1 AND one input end of the NOR-type gates NOR2 are connected with the input end of the NAND-type data selector MUX1, AND the output end of the 5 AND-type gates NOR2 AND one input end of the NAND-type data selector MUX1 are connected.
The output end of the NAND gate NAND1 is connected with the X0 input end of the alternative data selector MUX1, the output end OUT of the alternative data selector MUX1 is connected with the up/down of the up-down counter, the input end IN of the dynamic delay unit is connected with the input end of the NAND gate INV1 and the input end of the binary delay line, the output end of the NAND gate INV1 is connected with the CLK of the up-down counter, the output end of the up-down counter is connected with the binary delay line, and the output end of the binary delay line is the output end of the dynamic delay unit;
The workflow of the dynamic delay unit is described in detail in the workflow diagram of fig. 8, first, the up-down counter is reset after the chip is powered up, the output is 00000 so that all switches in the binary delay line are closed, and the dead time is set to the maximum value of the adjustment range. Therefore, the phenomenon that the circuit is directly connected due to the lack of initial judgment basis for VS voltage after normal power-on can be ensured. Then the circuit will determine whether the working state of the counter is 00000 or 11111, if the counter state is 00000, the logic circuit composed of NOR1, AND1, NOR2, NAND1 AND the one-out-of-two data selector MUX1 will force the input of the add-subtract control signal to be 0, so that the add-subtract counter will force 1 to be added, the circuit shields the input signal to directly read the delay of the binary delay line 15, AND forms dead time. Similarly, when the state of the counter is 11111, the logic circuit will force the up-down control signal 1 to be inputted, so that the up-down counter 14 will force the down-down signal 1, and the circuit will mask the input signal to directly read the delay of the binary delay line 15, and form dead time. The purpose of this function is to first avoid the up-down counter 14 jumping directly from 11111 to 00000 when a long dead time is required in circuit operation, which would drastically reduce the dead time causing circuit failure. Second, avoiding the need for a small dead zone in the operation of the circuit, the circuit jumps directly from the 00000 state to the 11111 state, thereby causing long-term reverse conduction losses. If the output value of the up-down counter 14 is not the highest value or the lowest value, the chip will enter a waiting state, and the value of the negative voltage detection circuit 8 is read when the rising edge of the clk signal arrives (the high voltage side channel delay in the chip is controlled by the LO and affects the low voltage side on-time; the low voltage side channel delay is provided by the delay signal of out_h and affects the on-time of the high voltage side channel). The voltage value of the VS end when the power tube is started can be used for judging whether the power device is in an anti-phase conduction stage. The main body portion of the negative pressure detection circuit 8 adopts the structure described in fig. 4, except that the negative pressure detection circuit 8 applied thereto is inverted in output and a small filter time is required to be added to prevent abnormality in the circuit state. The first stage is the dead zone stage that the high-voltage side power tube Q1 is to turn off and the low-voltage side power tube Q2 is to turn on, when the output of the negative pressure detection circuit 8 is zero, the power tube Q2 starts to freewheel, the Q2 is turned on later, the dead zone time is judged to be bigger, the signal can increase the value of the counter by 1 after entering the up-down counter, so that the dead zone time is reduced by one step, and similarly, if the output of the negative pressure detection circuit 8 is 1, the power tube Q2 is not in freewheel stage, VS is not reduced to zero, the high-voltage side power device Q1 is not completely turned off, and Q2 is turned on earlier. In this case, if the low-voltage side power transistor is turned on, the dead time is relatively small, the output value of the detection signal is reduced by one bit after entering the up-down counter, so that the dead time is increased by one step, and the second stage is a dead time stage in which the low-voltage side power transistor Q2 is to be turned off and the high-voltage side power transistor Q1 is to be turned on, and it is required to explain in advance that the delay time from out_h to HO' is the same as the delay time from out_h to HO, so that when the gate signal of Q1 is applied with the turn-on signal, if the negative pressure detection circuit 8 outputs 0, it is indicated that the turn-off of the low-voltage side power transistor Q2 is completed and the follow current stage is entered. At this time, it is determined that the dead time is longer, and the control signal causes the value of the up-down counter to be increased by 1, thereby controlling the binary delay line to decrease the dead time by one step. If the negative pressure detection circuit 8 outputs 1, there are two cases, one is that Q2 has not been completely turned off, and a first-gear dead zone needs to be increased. Another situation is that the circuit is operated in DCM mode, the low side power transistor is turned off and does not freewheel, and increasing dead time does not increase system losses.
In this embodiment, the binary delay line 15 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first PMOS transistor MP1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a second capacitor C2;
The drain electrode of the first PMOS transistor MP1 is configured to connect to the power supply VCC, the gate electrode of the first PMOS transistor MP1 is connected to the gate electrode of the first NMOS transistor MN1 and is used as the input end of the binary delay line, and the drain electrode of the first NMOS transistor MN1 is respectively connected to the first end of the first resistor R1 and the source electrode of the second NMOS transistor MN2 and is used as the output end of the binary delay line;
The source electrode of the first NMOS tube MN1 is connected with the first end of the second capacitor C2 and grounded, and the second end of the second capacitor C2 is connected with the drain electrode of the first NMOS tube MN 1;
The drain electrode of the second NMOS tube MN2 is respectively connected with the second end of the first resistor R1, the first end of the second resistor R2 and the source electrode of the third NMOS tube MN3, the drain electrode of the third NMOS tube MN3 is respectively connected with the second end of the second resistor R2, the first end of the third resistor R3 and the source electrode of the fourth NMOS tube MN4, the drain electrode of the fourth NMOS tube MN4 is respectively connected with the second end of the third resistor R3, the first end of the fourth resistor R4 and the source electrode of the fifth NMOS tube MN5, the drain electrode of the fifth NMOS tube MN5 is respectively connected with the second end of the fourth resistor R4, the first end of the fifth resistor R5 and the source electrode of the sixth NMOS tube MN6, and the drain electrode of the sixth NMOS tube MN6 is respectively connected with the second end of the fifth resistor R5 and the source electrode of the first PMOS tube MP 1;
The gate of the second NMOS transistor MN2, the gate of the third NMOS transistor MN3, the gate of the fourth NMOS transistor MN4, the gate of the fifth NMOS transistor MN5, and the gate of the sixth NMOS transistor MN6 are respectively connected to the input end of the third nor gate.
Specifically, the binary delay line 15 adopts an NMOS transistor as a control device for the short circuit of the resistor.
The input end IN is connected with the G poles of the MOS transistors MP1 and MN 1;
the D pole of the MOS tube MP1 is connected with a power supply VCC;
The S electrode of the MOS tube MP1 and the D electrode of the MOS tube MN6 are connected with one end of a resistor R5;
The S pole of the MOS tube MN6, the D pole of the MOS tube MN5 and the other end of the resistor R5 are connected with one end of the resistor R4;
The S pole of the MOS tube MN5, the D pole of the MOS tube MN4 and the other end of the resistor R4 are connected with one end of the resistor R3;
the S pole of the MOS tube MN4, the D pole of the MOS tube MN3 and the other end of the resistor R3 are connected with one end of the resistor R2;
The S pole of the MOS tube MN3, the D pole of the MOS tube MN2 and the other end of the resistor R2 are connected with one end of the resistor R1;
The S pole of the MOS tube MN2, the D pole of the MOS tube MN1 and the other end of the resistor R1 are connected with one end of the capacitor C and serve as an output end OUT;
the S electrode of the MOS tube MN1 is grounded to the other end of the capacitor C;
the G poles of the MOS tubes MN2, MN3, MN4, MN5 and MN6 are respectively connected with Q0, Q1, Q2, Q3 and Q4;
the reset function of the timer during power-on, MN 2-MN 6 are all turned off, and the time delay of the whole circuit to the IN signal falling edge can be expressed by the following formula:
Delaymax.=C*Vth.NAND(VCC/(R1+R2+R3+R4+R5));
Where C is the capacitance of the capacitor, vth, and NAND represents the threshold voltage of the NAND gate connected to the subsequent stage of the binary delay line. The resistance of the 5 controlled resistors increases exponentially. The delay shown in the above equation is also the maximum delay that can be provided by the binary delay line. When Q0-Q4 are all opened, the delay of the binary delay line is minimum:
Delaymin.=C*Vth.NAND/VCC;
With the increase of the output value of the binary up-down counter, the delay is reduced in a step-like manner. It should be noted that the delay circuit 2 delays only the falling edge of the IN signal, and the charge on C is rapidly released after the MN1 is turned on when the IN has a low level to a high level.
In this embodiment, the up-down counter 14 includes a D flip-flop 0801, four JK flip-flops (0802, 0803, 0804, 0805) and a plurality of logic gate circuits, wherein the CLK end of the D flip-flop 0801 is respectively connected with the CLK ends of the four JK flip-flops, the Reset end of the D flip-flop 0801 is respectively connected with the Reset ends of the four JK flip-flops, and the Q end of the D flip-flop 0801 and the Q end of the four JK flip-flops are respectively suspended;
the logic gate circuit includes a fourth NAND gate 0806, an OR gate 0807 and a fifth NAND gate 0808;
The output end of the fourth NAND gate 0806 is respectively connected with the J end and the K end of the JK trigger, the first input end of the fourth NAND gate 0806 is connected with the output end of the OR gate 0807, and the second input end of the fourth NAND gate 0806 is connected with the output end of the fifth NAND gate 0808;
A first input terminal of the or gate 0807 is connected to a first input terminal of the fifth nand gate 0808 and to a D terminal of the D flip-flop 0801, and a second input terminal of the or gate 0807 is connected to a second input terminal of the fifth nand gate 0808 and to the signal input terminal.
Specifically, CLK of the D flip-flop 0801 and CLK of the four JK flip-flops are connected together to external CLK;
The Reset of the D trigger 0801 and the Reset of the four JK triggers are connected together and connected with an external Reset;
Q of the D flip-flop 0801 and Q of the four JK flip-flops are Q0, Q1, Q2, Q3 and Q4 respectively;
input signal a is simultaneously coupled to one input of or gate 0807 and one input of nand gate 0808;
the other input of OR gate 0807, the other input of NAND gate 0808 is connected with D and/or Q of D flip-flop 0801;
the output of or gate 0807, one input of nand gate 0806, one input of or gate 0809 is connected to one input of nand gate 0810;
The output end of the NAND gate 0808 and the other input end of the NAND gate 0806 are connected with each other;
the output end of the NAND gate 0806 is connected with J and K of a JK trigger 0802;
the other input of OR gate 0809, the other input of NAND gate 0810 is connected to the/Q of JK flip-flop 0802;
the output of or gate 0809, one input of nand gate 0811 and one input of or gate 0813 are connected;
The output of NAND gate 0810, the other input of NAND gate 0811 being connected to one input of NAND gate 0814;
The other output of OR gate 0813, the other input of NAND gate 0814 being connected to the/Q of JK flip-flop 0803;
the output end of the NAND gate 0811 is connected with J and K of the JK trigger 0803;
The output of or gate 0813, one input of nand gate 0812 being connected to one input of or gate 0816;
The output of NAND gate 0814, the other input of NAND gate 0812 being connected to one input of NAND gate 0817;
The other input of OR gate 0816, the other input of NAND gate 0817 being connected to the/Q of JK flip-flop 0804;
the output end of the NAND gate 0815 is connected with J and K of the JK trigger 0805;
Reset is the Reset port of the D flip-flop, when the chip is started, the counter is Reset, when a equals 0, the value of the temporary counter is incremented by one bit at the clock signal, and when a=1, the value of the temporary counter is decremented by one bit at the clock signal. Its combination with logic effectively avoids a direct jump between 00000 and 11111. FIG. 11 shows simulation results of the entire dynamic delay unit, showing waveforms of the CLK signal, ND input signal, and Q4-Q0. It can be seen that the ND signal remains low after the start state counter is cleared, the counter is incremented, and when the value of the counter reaches a maximum, its state wanders between 11111 and 11110, and does not jump to 00000. Similarly, when the ND input signal goes high, the counter goes into a decrementing process. When the counter reaches the minimum value, the state of the counter wanders between 00000 and 00001, and the jump to the 11111 state is not increased. Along with the change of ND signals in the working process of the counter, the counter can realize the free up-down counting function and can not generate misoperation.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, article or apparatus that comprises the element.
While the embodiments of the present invention have been illustrated and described in connection with the drawings, what is presently considered to be the most practical and preferred embodiments of the invention, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various equivalent modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims (9)

1.一种集成自适应死区功能的智能功率模块，其特征在于，包括：壳体、设置于所述壳体内的电路铝基板、设置于所述电路铝基板的上表面的绝缘层、形成于所述绝缘层的上表面的电路布线、安装在所述电路布线上的多个电路元件以及多个引脚；多个所述电路元件与所述电路布线通过金属线电连接；多个所述引脚的一端连接所述电路布线，多个所述引脚的另一端延伸至所述壳体外；其中，所述电路铝基板上集成有自适应死区电路。1. An intelligent power module with integrated adaptive dead zone function, characterized in that it comprises: a shell, a circuit aluminum substrate arranged in the shell, an insulating layer arranged on the upper surface of the circuit aluminum substrate, a circuit wiring formed on the upper surface of the insulating layer, a plurality of circuit elements and a plurality of pins installed on the circuit wiring; a plurality of the circuit elements are electrically connected to the circuit wiring through metal wires; one end of a plurality of the pins is connected to the circuit wiring, and the other end of the plurality of the pins extends outside the shell; wherein an adaptive dead zone circuit is integrated on the circuit aluminum substrate. 2.如权利要求1所述的集成自适应死区功能的智能功率模块，其特征在于，所述电路铝基板的内部具有凹凸不平的纹理。2. The intelligent power module with integrated adaptive dead zone function as claimed in claim 1, characterized in that the interior of the circuit aluminum substrate has an uneven texture. 3.如权利要求1所述的集成自适应死区功能的智能功率模块，其特征在于，所述自适应死区电路包括：第一输入级电路、延时电路、第二输入级电路、动态死区产生电路、脉冲产生电路、电平移位电路、第一放大器、负压检测电路、低侧延时电路、第二放大器、电流保护电路、故障输出电路、欠压保护电路以及故障逻辑控制电路；所述第一输入级电路的输入端与所述第二输入级电路的输入端连接并共同用于连接信号输入端，所述第一输入级电路的输出端和所述第二输入级电路的输出端分别连接至所述动态死区产生电路的输入端，所述动态死区产生电路的输出端分别连接所述脉冲产生电路的输入端和所述低侧延时电路的输入端，所述脉冲产生电路的输出端连接所述电平移位电路的输入端，所述电平移位电路的输出端连接所述第一放大器的输入端，所述低侧延时电路的输出端连接所述第二放大器的输入端，所述第一放大器的输出端和所述第二放大器的输端分别连接至信号输出端上；所述电流保护电路的输入端用于连接ITRIP端口，所述电流保护电路的输出端连接所述故障逻辑控制电路的输入端，所述故障逻辑控制电路的输出端分别连接所述第一放大器的输入端、所述第二放大器的输入端以及所述故障输出电路的输入端，所述故障输出电路的输出端用于输出故障信号；所述欠压保护电路的输入端用于连接供电电源，所述欠压保护电路的输出端连接所述故障逻辑控制电路的输入端。3. The intelligent power module with integrated adaptive dead zone function as claimed in claim 1, characterized in that the adaptive dead zone circuit comprises: a first input stage circuit, a delay circuit, a second input stage circuit, a dynamic dead zone generating circuit, a pulse generating circuit, a level shifting circuit, a first amplifier, a negative voltage detection circuit, a low-side delay circuit, a second amplifier, a current protection circuit, a fault output circuit, an undervoltage protection circuit and a fault logic control circuit; the input end of the first input stage circuit is connected to the input end of the second input stage circuit and is commonly used to connect the signal input end, the output end of the first input stage circuit and the output end of the second input stage circuit are respectively connected to the input end of the dynamic dead zone generating circuit, the output end of the dynamic dead zone generating circuit is respectively connected to the input end of the pulse generating circuit and the input end of the low-side delay circuit, and the pulse generating circuit The output end of the circuit is connected to the input end of the level shift circuit, the output end of the level shift circuit is connected to the input end of the first amplifier, the output end of the low-side delay circuit is connected to the input end of the second amplifier, and the output end of the first amplifier and the input end of the second amplifier are respectively connected to the signal output end; the input end of the current protection circuit is used to connect to the ITRIP port, the output end of the current protection circuit is connected to the input end of the fault logic control circuit, the output end of the fault logic control circuit is respectively connected to the input end of the first amplifier, the input end of the second amplifier and the input end of the fault output circuit, and the output end of the fault output circuit is used to output a fault signal; the input end of the undervoltage protection circuit is used to connect to a power supply, and the output end of the undervoltage protection circuit is connected to the input end of the fault logic control circuit. 4.如权利要求3所述的集成自适应死区功能的智能功率模块，其特征在于，所述延时电路包括第一动态延时单元和第二动态延时单元；所述第一动态延时单元的输入端和所述第二动态延时单元的输入端连接并共同作为所述延时电路的输入端；所述第一动态延时单元的输出端和所述第二动态延时单元的输出端分别作为所述延时电路的输出端。4. The intelligent power module with integrated adaptive dead zone function as described in claim 3 is characterized in that the delay circuit includes a first dynamic delay unit and a second dynamic delay unit; the input end of the first dynamic delay unit and the input end of the second dynamic delay unit are connected and jointly serve as the input end of the delay circuit; the output end of the first dynamic delay unit and the output end of the second dynamic delay unit respectively serve as the output end of the delay circuit. 5.如权利要求4所述的集成自适应死区功能的智能功率模块，其特征在于，所述动态死区产生电路包括：第一非门、第一与非门、第一或非门、第二非门、第二与非门以及第二或非门；5. The intelligent power module with integrated adaptive dead zone function according to claim 4, characterized in that the dynamic dead zone generating circuit comprises: a first NOT gate, a first NAND gate, a first NOR gate, a second NOT gate, a second NAND gate and a second NOR gate; 所述第一非门的输入端连接所述第一动态延时单元的输入端，所述第一非门的输出端分别连接所述第一与非门的第一端和所述第一或非门的第一端，所述第一与非门的第二端作为所述动态死区产生电路的第一输入端连接至所述第一动态延时单元的输出端；The input end of the first NOT gate is connected to the input end of the first dynamic delay unit, the output end of the first NOT gate is respectively connected to the first end of the first NAND gate and the first end of the first NOR gate, and the second end of the first NAND gate is connected to the output end of the first dynamic delay unit as the first input end of the dynamic dead zone generating circuit; 所述第二非门的输入端连接所述第二动态延时单元的输入端，所述第二非门的输出端分别连接所述第二与非门的第一端和所述第二或非门的第一端，所述第二非门的第二端作为所述动态死区产生电路的第二输入端连接至所述第二动态延时单元的输出端；The input end of the second NOT gate is connected to the input end of the second dynamic delay unit, the output end of the second NOT gate is respectively connected to the first end of the second NAND gate and the first end of the second NOR gate, and the second end of the second NOT gate is connected to the output end of the second dynamic delay unit as the second input end of the dynamic dead zone generating circuit; 所述第一与非门的输出端连接所述第二或非门的第二端，所述第二与非门的输出端连接所述第一或非门的第二端，所述第一或非门的输出端连接所述脉冲产生电路的输入端，所述第二或非门的输出端连接所述低侧延时电路的输入端。The output end of the first NAND gate is connected to the second end of the second NOR gate, the output end of the second NAND gate is connected to the second end of the first NOR gate, the output end of the first NOR gate is connected to the input end of the pulse generating circuit, and the output end of the second NOR gate is connected to the input end of the low-side delay circuit. 6.如权利要求4所述的集成自适应死区功能的智能功率模块，其特征在于，所述第一动态延时单元与所述第二动态延时单元的电路结构相同。6 . The intelligent power module with integrated adaptive dead zone function according to claim 4 , wherein the circuit structure of the first dynamic delay unit is the same as that of the second dynamic delay unit. 7.如权利要求6所述的集成自适应死区功能的智能功率模块，其特征在于，所述第一动态延时单元包括：触发器、二选一数据选择器、加减计数器、二进制延时线、与门、第三与非门、第三或非门、第四或非门以及第三非门；7. The intelligent power module with integrated adaptive dead zone function according to claim 6, characterized in that the first dynamic delay unit comprises: a trigger, a two-select-one data selector, an up-down counter, a binary delay line, an AND gate, a third NAND gate, a third NOR gate, a fourth NOR gate and a third NOT gate; 所述触发器的输入端用于连接所述负压检测电路的输出端，所述触发器的输出端连接所述二选一数据选择器的X1输入端，所述二选一数据选择器的输出端连接所述加减计数器的控制端，所述加减计数器的输出端连接所述二进制延时线的输入端，所述二进制延时线的输出端作为所述第一动态延时单元的输出端；所述二进制延时线的输入端与所述第三非门的输入端连接并共同作为所述第一动态延时单元的输入端；The input end of the trigger is used to connect the output end of the negative voltage detection circuit, the output end of the trigger is connected to the X1 input end of the two-choice data selector, the output end of the two-choice data selector is connected to the control end of the add-subtract counter, the output end of the add-subtract counter is connected to the input end of the binary delay line, and the output end of the binary delay line serves as the output end of the first dynamic delay unit; the input end of the binary delay line is connected to the input end of the third NOT gate and serves as the input end of the first dynamic delay unit; 所述第三非门的输出端连接所述加减计数器的CLK端口，所述第三或非门的输入端用于连接信号输入端，所述第三或非门的输出端分别与所述第四或非门的第一输入端和所述第三与非门的第一输入端连接，所述第四或非门的输出端分别与所述第一与非门的第二输入端和所述二选一数据选择器的S输入端连接；所述第三与非门的输出端连接所述二选一数据选择器的X0输入端；所述与门的输入端用于连接所述信号输入端，所述与门的输出端连接所述第四或非门的第二输入端。The output end of the third NOT gate is connected to the CLK port of the up-down counter, the input end of the third NOR gate is used to connect to the signal input end, the output end of the third NOR gate is respectively connected to the first input end of the fourth NOR gate and the first input end of the third NAND gate, the output end of the fourth NOR gate is respectively connected to the second input end of the first NAND gate and the S input end of the two-to-one data selector; the output end of the third NAND gate is connected to the X0 input end of the two-to-one data selector; the input end of the AND gate is used to connect to the signal input end, and the output end of the AND gate is connected to the second input end of the fourth NOR gate. 8.如权利要求7所述的集成自适应死区功能的智能功率模块，其特征在于，所述二进制延时线包括：第一电阻、第二电阻、第三电阻、第四电阻、第五电阻、第一PMOS管、第一NMOS管、第二NMOS管、第三NMOS管、第四NMOS管、第五NMOS管、第六NMOS管以及第二电容；8. The intelligent power module with integrated adaptive dead zone function according to claim 7, characterized in that the binary delay line comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor and a second capacitor; 所述第一PMOS管的漏极用于连接所述供电电源，所述第一PMOS管的栅极与所述第一NMOS管的栅极连接并共同作为所述二进制延时线的输入端，所述第一NMOS管的漏极分别连接所述第一电阻的第一端和所述第二NMOS管的源极并作为所述二进制延时线的输出端；The drain of the first PMOS tube is used to connect to the power supply, the gate of the first PMOS tube is connected to the gate of the first NMOS tube and serves as the input end of the binary delay line, and the drain of the first NMOS tube is respectively connected to the first end of the first resistor and the source of the second NMOS tube and serves as the output end of the binary delay line; 所述第一NMOS管的源极连接所述第二电容的第一端并接地，所述第二电容的第二端连接所述第一NMOS管的漏极；The source of the first NMOS transistor is connected to the first end of the second capacitor and is grounded, and the second end of the second capacitor is connected to the drain of the first NMOS transistor; 所述第二NMOS管的漏极分别连接所述第一电阻的第二端、所述第二电阻的第一端以及所述第三NMOS管的源极；所述第三NMOS管的漏极分别连接所述第二电阻的第二端、所述第三电阻的第一端以及所述第四NMOS管的源极；所述第四NMOS管的漏极分别连接所述第三电阻的第二端、所述第四电阻的第一端以及所述第五NMOS管的源极；所述第五NMOS管的漏极分别连接所述第四电阻的第二端、所述第五电阻的第一端以及所述第六NMOS管的源极；所述第六NMOS管的漏极分别连接所述第五电阻的第二端以及所述第一PMOS管的源极；The drain of the second NMOS tube is respectively connected to the second end of the first resistor, the first end of the second resistor and the source of the third NMOS tube; the drain of the third NMOS tube is respectively connected to the second end of the second resistor, the first end of the third resistor and the source of the fourth NMOS tube; the drain of the fourth NMOS tube is respectively connected to the second end of the third resistor, the first end of the fourth resistor and the source of the fifth NMOS tube; the drain of the fifth NMOS tube is respectively connected to the second end of the fourth resistor, the first end of the fifth resistor and the source of the sixth NMOS tube; the drain of the sixth NMOS tube is respectively connected to the second end of the fifth resistor and the source of the first PMOS tube; 所述第二NMOS管的栅极、所述第三NMOS管的栅极、所述第四NMOS管的栅极、所述第五NMOS管的栅极以及所述第六NMOS管的栅极分别连接所述第三或非门的输入端。The gate of the second NMOS tube, the gate of the third NMOS tube, the gate of the fourth NMOS tube, the gate of the fifth NMOS tube and the gate of the sixth NMOS tube are respectively connected to the input end of the third NOR gate. 9.如权利要求7所述的集成自适应死区功能的智能功率模块，其特征在于，所述加减计数器包括：D触发器、四个JK触发器以及多个逻辑门电路；所述D触发器的CLK端分别与四个所述JK触发器的CLK端连接，所述D触发器的Reset端分别与四个所述JK触发器的Reset端连接，所述D触发器的Q端四个所述JK触发器的Q端分别悬置；9. The intelligent power module with integrated adaptive dead zone function according to claim 7, characterized in that the up-down counter comprises: a D flip-flop, four JK flip-flops and a plurality of logic gate circuits; the CLK terminal of the D flip-flop is respectively connected to the CLK terminals of the four JK flip-flops, the Reset terminal of the D flip-flop is respectively connected to the Reset terminals of the four JK flip-flops, and the Q terminals of the D flip-flop and the Q terminals of the four JK flip-flops are respectively suspended; 所述逻辑门电路包括：第四与非门、或门以及第五与非门；The logic gate circuit includes: a fourth NAND gate, an OR gate and a fifth NAND gate; 所述第四与非门的输出端分别连接所述JK触发器的J端和K端；所述第四与非门的第一输入端连接所述或门的输出端，所述第四与非门的第二输入端连接所述第五与非门的输出端；The output end of the fourth NAND gate is connected to the J end and the K end of the JK flip-flop respectively; the first input end of the fourth NAND gate is connected to the output end of the OR gate, and the second input end of the fourth NAND gate is connected to the output end of the fifth NAND gate; 所述或门的第一输入端与所述第五与非门的第一输入端连接并连接至所述D触发器的D端，所述或门的第二输入端与所述第五与非门的第二输入端连接并连接至所述信号输入端。The first input terminal of the OR gate is connected to the first input terminal of the fifth NAND gate and connected to the D terminal of the D flip-flop, and the second input terminal of the OR gate is connected to the second input terminal of the fifth NAND gate and connected to the signal input terminal.
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