CN119364818A - Power device and method for manufacturing the same - Google Patents
Power device and method for manufacturing the same Download PDFInfo
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- CN119364818A CN119364818A CN202411390071.7A CN202411390071A CN119364818A CN 119364818 A CN119364818 A CN 119364818A CN 202411390071 A CN202411390071 A CN 202411390071A CN 119364818 A CN119364818 A CN 119364818A
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Abstract
The application discloses a power device and a preparation method thereof, wherein the preparation method comprises the following steps of providing an epitaxial layer doped with a first conductive material, forming a well region in the epitaxial layer, and forming an active region in the well region; the method comprises the steps of arranging a first shielding part above one side of an epitaxial layer, doping the epitaxial layer uncovered by the first shielding part with a first conductive material to form a first region, etching the first region to obtain a second region, doping the bottom wall of the second region with a second conductive material to form a shielding region, and forming a thick oxygen structure in the second region, wherein the doping concentration of the first region is larger than that of the epitaxial layer. The application can improve the conduction performance and the reliability of the power device.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a power device and a preparation method thereof.
Background
As a common power device, a Metal-Oxide-semiconductor field effect transistor (MOSFET) has two structural forms, i.e., a planar type and a trench type. Wherein the gate of the planar MOSFET is located on the top surface of the power device and is disposed parallel to the substrate.
Compared with the trench MOSFET, the planar MOSFET has the advantages of simple structure, simple preparation process, strong voltage resistance and the like, but the conduction performance and reliability of the planar MOSFET are required to be further improved.
Disclosure of Invention
The embodiment of the application provides a power device and a preparation method thereof, wherein a shielding region is introduced into a JFET region of a planar power device, so that the conduction performance and reliability of the power device are improved.
In a first aspect, an embodiment of the present application provides a method for manufacturing a power device, where the method includes:
providing an epitaxial layer doped with a first conductive material, forming a well region in the epitaxial layer, and forming an active region in the well region;
A first shielding part is arranged above one side of the epitaxial layer, and the epitaxial layer which is not covered by the first shielding part is doped with a first conductive material to form a first region, wherein the doping concentration of the first region is larger than that of the epitaxial layer;
etching the first region to obtain a second region, and doping a second conductive material into the bottom wall of the second region to form a shielding region;
A thick oxygen structure is formed in the second region in contact with the first region and the shielding region.
In some embodiments, the step of forming a well region within the epitaxial layer and forming an active region within the well region includes:
The epitaxial layer is provided with a first part and a second part, a first mask sub-part is arranged above one side of the first part, and a well region is formed by doping a second conductive material into the first part;
A second mask sub-portion is additionally arranged above the first portion, a third mask sub-portion is arranged above the second portion, the epitaxial layer is doped with a first conductive material, and a stop ring is formed in the second portion while an active region is formed in the well region.
In some embodiments, the step of etching the first region to obtain a second region, doping the bottom wall of the second region with a second conductive material to form a shielding region includes:
A second shielding part is arranged above one side of the first part, the second shielding part at least covers part of the first area, and the first part which is not covered by the second shielding part is etched to obtain a second area;
A third shielding portion is disposed over the second portion, a second conductive material is doped to a bottom wall of the second region and the second portion not covered by the third shielding portion, and a junction termination structure is formed in the second portion while a shielding region is formed in the first region.
In some embodiments, the junction termination structure is formed by an ion implantation process, the junction termination structure having a doping concentration that is less than the doping concentration of the well region.
In some embodiments, the power device fabrication method further comprises:
And arranging a sacrificial layer above the junction terminal structure, and etching the sacrificial layer to form a shallow slot structure, wherein the distance h between the shallow slot structure and the junction terminal structure is kept unchanged or reduced along the direction away from the first part.
In some embodiments, the step of forming a thick oxygen structure within the second region in contact with the first region and the shielding region comprises:
Epitaxially growing an oxide layer in the second region and the epitaxial layer;
and a fourth shielding part is arranged above the oxide layer, the oxide layer which is not covered by the fourth shielding part is etched, a thick oxygen structure which is contacted with the first area and the shielding area is formed in the second area, and a passivation layer is formed above the second area.
In some embodiments, the orthographic projection of the second region onto the epitaxial layer coincides with the orthographic projection of the shielding region onto the epitaxial layer, or falls within the orthographic projection of the shielding region onto the epitaxial layer.
In some embodiments, the step of doping the epitaxial layer not covered by the first shielding portion with the first conductive material to form the first region includes performing a high temperature annealing process on the first region.
In some embodiments, the power device fabrication method further comprises:
The well region is doped with the second conductive material to form a heavily doped region, and the doping concentration of the heavily doped region is greater than that of the well region.
In a second aspect, an embodiment of the present application provides a power device, which is prepared by using the method for preparing a power device according to any one of the previous embodiments, where the power device includes an epitaxial layer, a well region located in the epitaxial layer, a guide region located in the epitaxial layer, a shielding region located in the guide region, and a thick oxygen structure located in the guide region, the well region is located on a first surface of the epitaxial layer, the guide region is located on the first surface of the epitaxial layer and between two adjacent well regions, an ion doping concentration of the guide region is greater than an ion doping concentration of the epitaxial layer, the shielding region is in contact with the epitaxial layer, two sides of the shielding region along the first direction are in contact with the guide region, and the thick oxygen structure is located above the shielding region, where the epitaxial layer and the guide region are of a first conductivity type, and the well region and the shielding region are of a second conductivity type.
According to the preparation method of the power device, the first region with higher ion doping concentration is formed in the epitaxial layer, so that the on-resistance of the power device in the epitaxial layer is reduced. According to the preparation method, the shielding region with opposite conductivity types is formed in the first region so as to adjust the electric field distribution of the first region, meanwhile, the thick oxygen structure is arranged above the shielding region, the gate oxide layer is protected in cooperation with the shielding region, the probability of breakdown of the gate oxide layer above the first region is reduced, and the reliability of the power device is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to designate like parts throughout the accompanying drawings. In the drawings:
Fig. 1 is a schematic structural diagram of a power device according to some embodiments of the present application;
fig. 2 is a schematic structural diagram of a power device according to some embodiments of the present application;
fig. 3 is a schematic structural diagram of a power device according to some embodiments of the present application;
Fig. 4 is a schematic flow chart of a method for manufacturing a power device according to some embodiments of the present application;
fig. 5 is a schematic flow chart of a power device manufacturing method according to some embodiments of the present application;
Fig. 6 is a schematic flow chart of a power device manufacturing method according to some embodiments of the present application;
fig. 7 is a schematic flow chart of a power device manufacturing method according to some embodiments of the present application;
Fig. 8a to 8h are schematic process structures of a method for manufacturing a power device according to some embodiments of the application.
Reference numerals in the specific embodiments are as follows:
10. first part, 100, cell area, 101, first area, 102, second area, 110, epitaxial layer, 120, well area, 121, active area, 122, heavy doping area, 130, diversion area, 140, shielding area, 150, thick oxygen structure;
20. the second part, 200, a terminal area, 210, an expansion area, 220, a slope groove, 230, a stop ring, 240 and a passivation layer;
310. 320 parts of gate oxide layer, 330 parts of gate electrode, 330 parts of isolation dielectric layer, 340 parts of source electrode, 350 parts of drain electrode;
a first direction X and a second direction Y.
Detailed Description
Embodiments of the technical scheme of the present application will be described in detail below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present application, and thus are merely examples, and are not intended to limit the scope of the present application.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs, the terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the application, and the terms "comprising" and "having" and any variations thereof in the description of the application and the claims and the above description of the drawings are intended to cover non-exclusive inclusions.
In the description of embodiments of the present application, the technical terms "first," "second," and the like are used merely to distinguish between different objects and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated, a particular order or a primary or secondary relationship. In the description of the embodiments of the present application, the meaning of "plurality" is two or more unless explicitly defined otherwise.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
In the description of the embodiment of the present application, the term "and/or" is merely an association relationship describing the association object, and indicates that three relationships may exist, for example, a and/or B, and may indicate that a exists alone, while a and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
In the description of the embodiments of the present application, the term "plurality" means two or more (including two), and similarly, "plural sets" means two or more (including two), and "plural sheets" means two or more (including two).
In the description of the embodiments of the present application, the orientation or positional relationship indicated by the technical terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are based on the orientation or positional relationship shown in the drawings, and are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the embodiments of the present application.
In the description of the embodiments of the present application, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "fixed" and the like are to be construed broadly and include, for example, fixed connection, detachable connection, or integral therewith, mechanical connection, electrical connection, direct connection, indirect connection via an intermediary, communication between two elements, or interaction between two elements. The specific meaning of the above terms in the embodiments of the present application will be understood by those of ordinary skill in the art according to specific circumstances.
In order to solve the problems in the prior art, the embodiment of the application provides a power device and a preparation method thereof, and the power device provided by the embodiment of the application is first described below.
Referring to fig. 1, an embodiment of the present application provides a power device, which includes an epitaxial layer 110, a well region 120, and a guiding region 130, wherein the well region 120 is formed by extending a first surface of the epitaxial layer 110 into the epitaxial layer 110, the guiding region 130 is disposed in two adjacent well regions 120 along a first direction, and the guiding region 130 is formed by extending the first surface of the epitaxial layer 110 into the epitaxial layer 110. The guiding region 130 and the epitaxial layer 110 are of the first conductivity type, the ion doping concentration of the guiding region 130 is greater than that of the epitaxial layer 110, and the well region 120 is of the second conductivity type.
It is understood that the first conductivity type is opposite to the second conductivity type, i.e., the first conductivity type is one of N-type ion doping or P-type ion doping, and the second conductivity type is the other of N-type ion entanglement or P-type ion doping. Illustratively, the first conductivity type is N-type ion doping and the second conductivity type is P-type ion doping.
Therefore, the diversion area 130 is introduced into the JFET area special for the planar power device, the diversion area 130 with higher ion doping concentration has lower resistivity, and the on-resistance of the planar power device is reduced.
Further, the power device further includes a shielding region 140 located in the guiding region 130, the shielding region 140 is set to be of a second conductivity type opposite to the guiding region 130, the shielding region 140 is disposed in contact with the epitaxial layer 110, and two sides of the shielding region 140 along the first direction are disposed in contact with the guiding region 130.
Therefore, the shielding region 140 can at least partially counteract the significant increase of the electric field intensity of the gate oxide layer 310 caused by the arrangement of the flow guiding region 130, reduce the probability of breakdown of the gate oxide layer 310 above the flow guiding region 130, and improve the voltage-withstanding performance of the planar power device.
Still further, the power device further includes a thick oxygen structure 150 located in the guiding region 130, and the thick oxygen structure 150 is disposed above the shielding region 140 along the second direction.
Optionally, the thick oxygen structure 150 is flush with the first surface of the epitaxial layer 110 to facilitate the preparation of the post gate oxide 310.
Alternatively, the thick oxygen structure 150 is made of a silicon dioxide material.
Alternatively, the thick oxygen structure 150 is made of an insulating oxide material that is not conformal to the gate oxide layer 310.
Thus, the thick oxygen structure 150 can cooperate with the shielding region 140 to attenuate an increase in the electric field of the gate oxide layer 310 due to the provision of the flow guiding region 130. After the thick oxygen structure 150 is introduced, the ion doping concentration of the shielding region 140 can be reduced appropriately, so that the negative influence of the shielding region 140 on the conduction performance of the power device is reduced while the same protection effect is maintained.
Alternatively, the power device is a vertical double-diffused metal-Oxide-Semiconductor field effect Transistor (Vertical Double Diffusion Metal-Oxide-Semiconductor FIELD EFFETCT Transistor, VDMOS) or an insulated gate bipolar Transistor (Insulate-Gate Bipolar Transistor, IGBT).
Further alternatively, the VDMOS includes a silicon-based VDMOS and a silicon carbide-based VDMOS.
Referring to fig. 1, according to some embodiments of the present application, the power device further includes a heavily doped region 122 located in the well region 120, the heavily doped region 122 is of the second conductivity type, and the ion doping concentration of the heavily doped region 122 is greater than the ion doping concentration of the well region 120.
Optionally, the heavily doped region 122 is disposed in contact with the active region 121 within the well region 120, and the depth of the heavily doped region 122 is greater than or equal to the depth of the active region 121 along the second direction.
Optionally, heavily doped region 122 is formed by extending a first surface of epitaxial layer 110 into well region 120.
Therefore, the resistance of the well region 120 is adjusted to reduce the voltage drop of the well region 120, improve the latch-up effect in the power device and improve the reliability of the power device.
According to some embodiments of the present application, the guiding region 130 is disposed at a midpoint between two adjacent well regions 120, i.e. a midpoint of the guiding region 130 coincides with a midpoint of a JFET region formed between two adjacent well regions 120 in the first direction.
Optionally, in the second direction, the depth of the guiding region 130 is smaller than the depth of the well region 120.
Optionally, the guiding region 130 is disposed in contact with the well region 120.
Optionally, the guiding region 130 is spaced apart from the well region 120 by the epitaxial layer 110.
Further optionally, the length of the guiding region 130 in the first direction has a ratio of greater than or equal to 70% of the JFET region length. Illustratively, the length of the steering region 130 has a 5/7 ratio of the length of the JFET region.
According to some embodiments of the present application, the ion doping concentration of the shielding region 140 is less than the ion doping concentration of the well region 120.
Optionally, the bottom of the shielding region 140 is flush with the bottom of the flow guiding region 130.
Optionally, in the second direction, the depth of the shielding region 140 is greater than the depth of the thick oxygen structure 150.
Optionally, in the first direction, the width of the shielding region 140 has a ratio of greater than 30% to less than 1 in the width of the guiding region 130. Illustratively, the width of the shielding region 140 is 40% of the width of the flow directing region 130.
According to some embodiments of the present application, the orthographic projection of the thick oxygen structure 150 onto the shielding region 140 falls within the shielding region 140, i.e. the width of the thick oxygen structure 150 is smaller than or equal to the width of the shielding region 140 in the first direction. Illustratively, the width of the thick oxygen structure 150 is equal to the width of the shielding region 140.
Optionally, in the second direction, the depth of the thick oxygen structure 150 is greater than the depth of the gate oxide layer 310 between the gate electrode 320 and the epitaxial layer 110.
Referring to fig. 2, according to some embodiments of the present application, the epitaxial layer 110 includes a cell region 100 and a termination region 200, and the termination region 200 of the epitaxial layer 110 is formed with a junction termination structure of the second conductivity type, and the ion doping concentration of the junction termination structure is lower than that of the well region 120.
Optionally, referring to the figure, the junction termination structure includes at least two extension regions 210, the at least two extension regions 210 being disposed in contact along a first direction. In the adjacent two extension regions 210, the depth of the extension region 210 near the cell region 100 in the second direction is greater than the depth of the extension region 210 far from the cell region 100 in the second direction.
Therefore, the breakdown resistance of the terminal part of the power device is improved, the area of the power device is reduced, the on-resistance of the unit area of the power device is reduced, and the on-performance is improved.
Referring to fig. 2 or 3, according to some embodiments of the application, the power device further includes a shallow trench structure formed over the junction termination structure along the second direction.
Optionally, the shallow trench structure includes a sloped trench 220, wherein a side of the sloped trench 220 closer to the cell region 100 is higher than a side of the sloped trench away from the cell region 100.
Optionally, the shallow trench structure includes at least two ramp trenches 220, and a depth of a ramp trench 220 adjacent to the cell region 100 in the second direction is smaller than a depth of a ramp trench 220 distant from the cell region 100 in the second direction in adjacent two ramp trenches 220.
Alternatively, the slope grooves 220 are equal in number to the expansion areas 210 and are provided in one-to-one correspondence.
Further alternatively, the ramp slot 220 is disposed at a middle position of the extension region 210 in the second direction.
Further alternatively, in the second direction, the ramp slot 220 is disposed in alignment with an edge of the extension region 210.
Therefore, the ion implantation distribution area of the junction terminal structure is further adjusted through the shallow slot structure, and an ion concentration gradient is formed to relieve the electric field concentration phenomenon at the main junction and improve the reverse blocking capability of the power device.
According to some embodiments of the present application, the power device further comprises a passivation layer 240, the passivation layer 240 being disposed over the termination region 200 epitaxial layer 110 along the first direction.
Optionally, passivation layer 240 is a layer of insulating material.
Optionally, passivation layer 240 is consistent with the material of thick oxygen structure 150.
According to some embodiments of the present application, the power device further includes a stop ring 230, the stop ring 230 being of the first conductivity type, the stop ring 230 being disposed at an outer edge of the termination region 200 of the epitaxial layer 110.
Optionally, the ion doping concentration of the stop ring 230 is greater than the ion doping concentration of the epitaxial layer 110.
Optionally, in a second direction, the stop ring 230 is spaced apart from the junction termination structure by the epitaxial layer 110.
On the other hand, the embodiment of the present application further provides a method for manufacturing a power device, which may be used to manufacture the power device shown in fig. 1 to 3, referring to fig. 4 and fig. 8a to 8h, where the method for manufacturing a power device includes:
s100, providing an epitaxial layer 110 doped with a first conductive material, forming a well region 120 in the epitaxial layer 110, and forming an active region 121 in the well region 120;
S200, arranging a first shielding part above one side of the epitaxial layer 110, and doping the epitaxial layer 110 uncovered by the first shielding part with a first conductive material to form a first region 101, wherein the doping concentration of the first region 101 is greater than that of the epitaxial layer 110;
s300, etching the first region 101 to obtain a second region 102, and doping a second conductive material into the bottom wall of the second region 102 to form a shielding region 140;
s400, a thick oxygen structure 150 is formed in the second region 102 in contact with the first region 101 and the shielding region 140.
According to the embodiment of the application, the first region 101 with higher ion doping concentration is formed in the epitaxial layer 110 to reduce the on-resistance of the power device at the epitaxial layer 110, then the second region 102 is etched in the first region 101 and the shielding region 140 below the second region 102 and the thick oxygen structure 150 inside the second region 102 are respectively formed, so that the increase of the local electric field intensity caused by the high doping concentration of the first region 101 is regulated, the probability of breakdown of the gate oxide layer 310 above the first region 101 is reduced, the on-performance of the power device is improved, and the reliability of the power device is improved.
It is understood that the first conductive material is of opposite conductivity type to the second conductive material. Illustratively, the first conductive material is an N-type conductive ion and the second conductive material is a P-type conductive ion.
Referring to fig. 5, fig. 8a, and fig. 8c, in a method for manufacturing a power device according to some embodiments of the present application, step S100 includes:
s110, providing a substrate doped with a first conductive material, and growing an epitaxial layer 110 above the substrate;
S130, the epitaxial layer 110 is provided with a first part 10 and a second part 20, a first mask sub-part is arranged above one side of the first part 10, and a well region 120 is formed by doping a second conductive material into the first part 10;
S150, a second mask sub-portion is added above the first portion 10, a third mask sub-portion is provided above the second portion 20, the epitaxial layer 110 is doped with the first conductive material, and the stop ring 230 is formed in the second portion 20 while the active region 121 is formed in the well region 120.
Optionally, in step S130, the first portion 10 is doped with a second conductive material by an ion implantation process or a diffusion process.
Optionally, in step S130, the first portion 10 is used to prepare the cellular region 100, and the second portion 20 is used to prepare the terminal region 200.
Optionally, in step S150, the epitaxial layer 110 is doped with a first conductive material by an ion implantation process.
Referring to fig. 8b, in the method for manufacturing a power device according to some embodiments of the present application, step S100 further includes:
And S140, adding a fourth mask sub-part above the first part 10, and doping the well region 120 with the second conductive material to form a heavily doped region 122, wherein the doping concentration of the heavily doped region 122 is greater than that of the well region 120.
Optionally, in step S140, the well region 120 is doped with a second conductive material by an ion implantation process or a diffusion process.
According to some embodiments of the present application, step S200 further comprises performing a high temperature annealing process on the first region 101.
Referring to fig. 6 and fig. 8d to fig. 8e, in a method for manufacturing a power device according to some embodiments of the present application, step S300 includes:
s310, arranging a second shielding part above one side of the first part 10, wherein the second shielding part at least covers part of the first region 101, and etching the first part 10 which is not covered by the second shielding part to obtain a second region 102;
s330, a third shielding portion is disposed above the second portion 20, and the bottom wall of the second region 102 and the second portion 20 uncovered by the third shielding portion are doped with a second conductive material, so that a junction termination structure is formed in the second portion 20 while the shielding region 140 is formed in the first region 101.
Optionally, in step S310, the etching process includes at least one of plasma etching and reactive ion etching.
Optionally, in step S330, the front projection of the shielding region 140 on the epitaxial layer 110 coincides with the front projection of the second region 102 on the epitaxial layer 110, or the front projection of the second region 102 on the epitaxial layer 110 falls within the front projection of the shielding region 140 on the epitaxial layer 110.
Optionally, in step S330, the second portion 20 is doped with a second conductive material by an ion implantation process.
Optionally, in step S330, the extension region 210 of the junction termination structure far from the first portion 10 is formed simultaneously with the shielding region 140, or the extension region 210 of the junction termination structure near to the first portion 10 is formed simultaneously with the shielding region 140.
Optionally, in step S330, the third shielding portion is photoresist.
Thus, a shielding region 140 of the second conductivity type is formed within the first region 101, while other regions within the first region 101 form the guiding region 130 of the first conductivity type.
According to some embodiments of the application, in the method for manufacturing a power device, step S300 further includes:
and S320, etching the second part 20 for a plurality of times to obtain a step-shaped injection window.
Referring to fig. 2, 6 and 8f, according to some embodiments of the present application, step S300 further includes:
and S350, arranging a sacrificial layer above the junction terminal structure, and etching the sacrificial layer to form a shallow slot structure, wherein the distance h between the shallow slot structure and the junction terminal structure is kept unchanged or reduced along the direction away from the first part 10.
Optionally, in step S350, a reverse step sacrificial layer is formed by multiple depositions over the junction termination structure.
Optionally, in step S350, a sacrificial layer with a uniform thickness is disposed above the junction termination structure, and the sacrificial layer is etched multiple times to form a shallow trench structure with a reverse step shape.
Referring to fig. 7 and 8g, step S400 includes:
s410, epitaxially growing an oxide layer in the second region 102 and the epitaxial layer 110;
s430, a fourth shielding portion is disposed above the oxide layer, the oxide layer uncovered by the fourth shielding portion is etched, and a passivation layer 240 is formed above the second portion 20 while forming a thick oxygen structure 150 in the second region 102 in contact with the first region 101 and the shielding region 140.
Optionally, in step S410, an oxide layer is grown within the second region 102 by a high temperature wet oxidation process.
Referring to fig. 8h, according to some embodiments of the present application, the power device manufacturing method further includes:
S500, a gate oxide layer 310, a gate electrode 320, an isolation dielectric layer 330, a source electrode 340 are formed over the first surface of the epitaxial layer 110, and a drain electrode 350 is formed under the substrate.
Alternatively, in step S500, the gate oxide layer 310 is formed by a low-temperature dry oxidation process.
Optionally, in step S500, the gate 320 is formed by a process of depositing polysilicon and etching.
Optionally, in step S500, the isolation dielectric 330 is formed by a deposition process.
Optionally, forming the source electrode 340 includes etching the isolation dielectric layer 330, forming a contact hole and exposing at least a portion of the active region 121, and preparing the source electrode 340 within the contact hole to electrically connect the source electrode 340 with the active region 121 in step S500.
It should be noted that the above embodiments are only used to illustrate the technical solution of the present application, but not to limit the technical solution of the present application, and although the detailed description of the present application is given with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present application, and all the modifications or substitutions are included in the scope of the claims and the specification of the present application. In particular, the technical features mentioned in the respective embodiments may be combined in any manner as long as there is no structural conflict. The present application is not limited to the specific embodiments disclosed herein, but encompasses all technical solutions falling within the scope of the claims.
Claims (10)
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| CN202411390071.7A CN119364818A (en) | 2024-09-30 | 2024-09-30 | Power device and method for manufacturing the same |
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| CN202411390071.7A CN119364818A (en) | 2024-09-30 | 2024-09-30 | Power device and method for manufacturing the same |
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