CN119277813A - Semiconductor structure and manufacturing method - Google Patents
Semiconductor structure and manufacturing method Download PDFInfo
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- CN119277813A CN119277813A CN202411390018.7A CN202411390018A CN119277813A CN 119277813 A CN119277813 A CN 119277813A CN 202411390018 A CN202411390018 A CN 202411390018A CN 119277813 A CN119277813 A CN 119277813A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 36
- 238000000034 method Methods 0.000 claims abstract description 102
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000004140 cleaning Methods 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 157
- 239000011241 protective layer Substances 0.000 claims description 81
- 239000000463 material Substances 0.000 claims description 52
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 10
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- 238000000206 photolithography Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims 2
- 230000000717 retained effect Effects 0.000 abstract 1
- 238000002161 passivation Methods 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 238000002955 isolation Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003574 free electron Substances 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000002035 prolonged effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Abstract
本发明提供了一种半导体结构及制造方法，通过在包括有用于制作具有第一耐压能力的晶体管的第一区域和用于制作具有第二耐压能力的晶体管的第二区域的半导体衬底表面生成覆盖层；在所述覆盖层表面形成第一图形化保护层，在所述第一图形化保护层的暴露的区域执行第一掺杂制程；去除所述第一图形化保护层，保留所述覆盖层；在所述覆盖层表面形成第二图形化保护层，在所述第二图形化保护层的暴露的区域执行第二掺杂制程；去除所述第二图形化保护层，保护有源区表面在离子化金属等离子体掺杂和清洗过程中不暴露于空气中而不被侵蚀，可有效保护有源区整体高度的均匀性，提高设备的稳定性，提升器件良率及可靠性，延长使用寿命。
The present invention provides a semiconductor structure and a manufacturing method, wherein a covering layer is generated on the surface of a semiconductor substrate including a first region for manufacturing a transistor with a first withstand voltage capability and a second region for manufacturing a transistor with a second withstand voltage capability; a first patterned protection layer is formed on the surface of the covering layer, and a first doping process is performed on an exposed region of the first patterned protection layer; the first patterned protection layer is removed and the covering layer is retained; a second patterned protection layer is formed on the surface of the covering layer, and a second doping process is performed on an exposed region of the second patterned protection layer; and the second patterned protection layer is removed to protect the surface of an active region from being exposed to air and corroded during ionized metal plasma doping and cleaning, thereby effectively protecting the uniformity of the overall height of the active region, improving the stability of the equipment, increasing the device yield and reliability, and extending the service life.
Description
Technical Field
The present disclosure relates to semiconductor devices, and particularly to a semiconductor structure and a method for manufacturing the same.
Background
In the fabrication of the active region, in the process of fabricating the gate structure, a low Doped drain (Lightly Doped Drain, abbreviated as LDD) process is performed on the transistor for fabricating the transistor with low voltage resistance, and then a High Doped (HD) process is performed on the transistor for fabricating the transistor with High voltage resistance. The low-doped drain process and the high-doped process also comprise a photoetching process and an ion implantation process, and wet cleaning is required, so that the active region can be subjected to multiple wet cleaning. However, the wet cleaning solution contains weakly basic substances (such as ammonium hydroxide, with a chemical formula of NH 4 OH) which consume the oxide layer exposed above the active region, and when the oxide layer is completely consumed, the active region is exposed and naturally oxidized and consumed by the next wet cleaning, so that the surface of the active region is continuously eroded. And thus the height of the active region located under the polysilicon is different from that of the surrounding region, affecting the stability of the device.
How to provide a method for manufacturing an active region, which can protect the active region from being corroded in the doping process, is a problem to be solved.
Disclosure of Invention
The invention aims to provide a semiconductor structure and a manufacturing method thereof, which can protect an active region from being corroded in a doping process.
In order to solve the problems, the invention provides an active region manufacturing method, which comprises the steps of providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, the first region is used for manufacturing a transistor with first voltage endurance, the second region is used for manufacturing a transistor with second voltage endurance, a first gate electrode is formed on the surface of the first region, a first gate oxide layer is arranged at the bottom of the first gate electrode, a second gate electrode is formed on the surface of the second region, a second gate oxide layer is arranged at the bottom of the second gate electrode, a covering layer is generated on the surface of the semiconductor substrate, a first patterned protective layer is formed on the surface of the covering layer, a first doping process is performed on the exposed region of the first patterned protective layer, the first patterned protective layer is removed, a second patterned protective layer is formed on the surface of the covering layer, a second doping process is performed on the exposed region of the second patterned protective layer, the exposed region of the first patterned protective layer is located in the first region, the second patterned protective layer is located in the exposed region of the second patterned protective layer, or the exposed region of the second patterned protective layer is located in the exposed region of the first patterned protective layer.
In some embodiments, the first region surface is formed with a first gate oxide material layer that is continuously distributed, the second region surface is formed with a second gate oxide material layer that is continuously distributed, and before the step of forming the cover layer on the semiconductor substrate surface, the method further comprises removing the first gate oxide material layer and the second gate oxide material layer that are exposed on the semiconductor substrate surface, wherein the first gate oxide material layer remaining at the bottom of the first gate electrode forms the first gate oxide layer, and the second gate oxide material layer remaining at the bottom of the second gate electrode forms the second gate oxide layer.
In some embodiments, wet etching is used to remove the first gate oxide material layer and the second gate oxide material layer exposed on the surface of the semiconductor substrate.
In some embodiments, the material of the first gate electrode and the second gate electrode is polysilicon.
In some embodiments, the material of the capping layer is silicon oxide.
In some embodiments, chemical vapor deposition is used to create a capping layer on the surface of the semiconductor substrate.
In some embodiments, the exposed region of the first patterned protection layer is a region on two sides of the first gate electrode in the first region, the exposed region of the second patterned protection layer is a region on two sides of the second gate electrode in the second region, or the exposed region of the first patterned protection layer is a region on two sides of the second gate electrode in the second region, and the exposed region of the second patterned protection layer is a region on two sides of the first gate electrode in the first region.
In some embodiments, the material of the first patterned protective layer and the second patterned protective layer is photoresist.
In some embodiments, the first patterned protective layer and the second patterned protective layer are removed separately using a wet cleaning process.
In some embodiments, the removing the second patterned protective layer further comprises removing the capping layer to expose the semiconductor substrate surface, a first gate structure including the first gate electrode and the first gate oxide layer at the bottom thereof, and a second gate structure including the second gate electrode and the second gate oxide layer at the bottom thereof.
In some embodiments, the step of removing the second patterned protection layer further includes forming a sidewall on a side of the first gate structure and a side of the second gate structure.
In some embodiments, the material of the side wall is silicon oxide or silicon nitride.
In some embodiments, the first doping process is a lightly doped drain process and the second doping process is a highly doped process.
In some embodiments, the lightly doped drain process and the highly doped process further comprise a photolithography process and an ionized metal plasma process.
In order to solve the above problems, the present invention also provides a semiconductor structure manufactured by the semiconductor structure manufacturing method.
According to the technical scheme, the covering layer is generated on the surface of the semiconductor substrate, which comprises the first area for manufacturing the transistor with the first voltage endurance capability and the second area for manufacturing the transistor with the second voltage endurance capability, the first patterned protective layer is formed on the surface of the covering layer, the first doping process is performed on the exposed area of the first patterned protective layer, the first patterned protective layer is removed, the covering layer is reserved, the second patterned protective layer is formed on the surface of the covering layer, the second doping process is performed on the exposed area of the second patterned protective layer, the second patterned protective layer is removed, the surface of the active area is protected from being exposed to air and not being corroded in the ionized metal plasma doping and cleaning process, the uniformity of the overall height of the active area can be effectively protected, the stability of the device is improved, the yield and the reliability of the device are improved, and the service life is prolonged.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;
FIG. 2 is a schematic view of a semiconductor substrate device according to an embodiment of the present invention;
FIG. 3 is a schematic view of a device formed by a step of removing an exposed oxide layer on a surface of a semiconductor substrate according to an embodiment of the present invention;
FIG. 4 is a schematic view of a device structure formed by a step of forming a capping layer according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a device structure formed by performing a first doping process on exposed areas of a first patterned passivation layer according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a device structure formed by removing a first patterned passivation layer according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a device structure formed by performing a second doping process on exposed areas of a second patterned passivation layer according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a device structure formed by removing the second patterned passivation layer according to an embodiment of the present invention;
Fig. 9 is a schematic view of a device structure formed by a step of forming a sidewall on a side surface of a first gate structure and a second gate structure according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1 to 9, fig. 1 is a flowchart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;
Fig. 3 is a schematic device structure diagram of a step of removing an exposed oxide layer on a surface of a semiconductor substrate according to an embodiment of the present invention, fig. 4 is a schematic device structure diagram of a step of forming a capping layer according to an embodiment of the present invention, fig. 5 is a schematic device structure diagram of a step of performing a first doping process on an exposed region of a first patterned protection layer according to an embodiment of the present invention, fig. 6 is a schematic device structure diagram of a step of removing a first patterned protection layer according to an embodiment of the present invention, fig. 7 is a schematic device structure diagram of a step of performing a second doping process on an exposed region of a second patterned protection layer according to an embodiment of the present invention, fig. 8 is a schematic device structure diagram of a step of removing a second patterned protection layer according to an embodiment of the present invention, and fig. 9 is a schematic device structure diagram of a step of forming a sidewall on a side surface of a first gate structure and a second gate structure according to an embodiment of the present invention.
The method for manufacturing the semiconductor structure comprises the steps of providing a semiconductor substrate, providing a first region and a second region, wherein the first region is used for manufacturing a transistor with first voltage endurance capability, the second region is used for manufacturing a transistor with second voltage endurance capability, a first gate electrode is formed on the surface of the first region, a first gate oxide layer is arranged at the bottom of the first gate electrode, a second gate electrode is formed on the surface of the second region, a second gate oxide layer is arranged at the bottom of the second gate electrode, a covering layer is generated on the surface of the semiconductor substrate, forming a first patterned protective layer on the surface of the covering layer, executing a first doping process on the exposed region of the first patterned protective layer, removing the first patterned protective layer, keeping the covering layer, the exposed region of the first patterned protective layer is located in the first region, the exposed region of the second patterned protective layer is located in the second region, or the exposed region of the second patterned protective layer is located in the second region, forming a second patterned protective layer is located in the exposed region, removing the second patterned protective layer is located in the exposed region, and removing the first patterned protective layer is formed in the exposed region.
Referring to step S11 and fig. 3, a semiconductor substrate 11 is provided, the semiconductor substrate 11 includes a first region 111 and a second region 112, the first region 111 is used for manufacturing a transistor having a first voltage withstand capability, the second region 112 is used for manufacturing a transistor having a second voltage withstand capability, a first gate electrode 13 is formed on a surface of the first region 111, a first gate oxide layer 12 is formed at a bottom of the first gate electrode 13, a second gate electrode 15 is formed on a surface of the second region 112, and a second gate oxide layer 14 is formed at a bottom of the second gate electrode 15. In this embodiment, the first voltage withstand capability is 5V, the second voltage withstand capability is 1.5V, the materials of the first gate oxide layer 12 and the second gate oxide layer 14 are both silicon oxide (SiO 2), and the materials of the first gate electrode 13 and the second gate electrode 15 are polysilicon. The semiconductor substrate 11 further includes shallow trench isolation 110 (Shallow Trench Isolation, STI for short). The shallow trench isolation 110 is filled with silicon oxide for isolation of active devices.
Referring to fig. 2, in this embodiment, before forming the device structure of the semiconductor substrate shown in fig. 3, a first gate oxide material layer 120 that is continuously distributed is formed on the surface of the first region 111, and a second gate oxide material layer 140 that is continuously distributed is formed on the surface of the second region 112, where the materials of the first gate oxide material layer 120 and the second gate oxide material layer 140 are both silicon oxide. Accordingly, before the next step is performed, the method further comprises removing the first gate oxide material layer 120 and the second gate oxide material layer 140 exposed on the surface of the semiconductor substrate 11, forming the first gate oxide layer 12 by the first gate oxide material layer 120 remaining at the bottom of the first gate electrode 13, and forming the second gate oxide layer 14 by the second gate oxide material layer 140 remaining at the bottom of the second gate electrode 15. And further a device structure of the semiconductor substrate as shown in fig. 3.
The present embodiment uses wet etching to remove the first gate oxide material layer 120 and the second gate oxide material layer 140 exposed on the surface of the semiconductor substrate 11 shown in fig. 2.
Referring to step S12 and fig. 4, a cover layer 16 is generated on the surface of the semiconductor substrate 11. As shown in fig. 4, the cover layer 16 is a completely continuous thin film layer, and the cover layer 16 covers the exposed area of the surface of the semiconductor substrate 11, the surface of the first gate electrode 13, and the surface of the second gate electrode 15.
Before this step is performed, the first gate oxide material layer 120 and the second gate oxide material layer 140 exposed on the surface of the semiconductor substrate 11 have been removed, so that the newly generated capping layer 16 completely and uniformly covers the surface of the active region.
In this embodiment, the material of the cover layer 16 is silicon oxide, and may be formed on the surface of the semiconductor substrate 11 by chemical vapor deposition.
The active region may undergo multiple wet cleans during the doping process. However, the weakly basic material mixed in the wet cleaning solution consumes the exposed oxide layer over the active region, and the thickness of the oxide layer in the active region itself is insufficient to protect the active region. When the oxide layer is completely consumed, the active region is exposed and naturally oxidized and consumed by the next wet cleaning, so that the surface of the active region is continuously eroded. This step regenerates an oxide layer on the surface of the semiconductor substrate 11 that meets the thickness requirements, thereby protecting the active region during the doping process.
Referring to step S13 and fig. 5, a first patterned passivation layer 17 is formed on the surface of the capping layer 16, and a first doping process is performed on the exposed region of the first patterned passivation layer 17. The first doping process includes a photolithography process, the material of the first patterned protective layer 17 is photoresist, and the first patterned protective layer 17 is obtained by imprinting a silicon wafer and photolithography.
In this embodiment, the exposed region of the first patterned protective layer 17 is located in the second region 112. As shown in fig. 5, the exposed area of the first patterned protection layer 17 is the area on both sides of the second gate electrode 15 in the second area 112, and the area covered by the first patterned protection layer 17 is the protected area. The withstand voltage of the second gate electrode 15 is 1.5V, and a first doping process is performed in the regions on both sides of the second gate electrode 15.
In another embodiment, the exposed area of the first patterned passivation layer 17 is located in the first area 111, and the exposed area of the first patterned passivation layer 17 is the area on both sides of the first gate electrode 13 in the first area 111, i.e. a first doping process is performed on the area on both sides of the first gate electrode 13.
In this embodiment, the first doping process is a lightly doped drain (Lightly Doped Drain, abbreviated as LDD) process.
The lightly doped drain process includes an ionized metal plasma (Ionized METAL PLASMA, abbreviated as IMP) process, and by means of plasma implantation, the lightly doped drain process can generate a lightly doped region in the exposed region of the first patterned protection layer 17, and the peak electric field intensity near the drain is reduced by the lightly doped region, so that the hot carrier effect is reduced. N-type doping is required to increase the number of free electrons of negative charge when making N-type transistors, N-LDD process is performed, P-type doping is required to increase the number of positive holes when making P-type transistors, and P-LDD process is performed.
Referring to step S14, the first patterned protective layer 17 is removed, and the cover layer 16 is left. The first patterned protective layer 17 is removed using a photoresist removal (PR Strip) process. In this embodiment, a wet cleaning process is used to remove the first patterned passivation layer 17.
The schematic device structure after removing the first patterned protective layer 17 is shown in fig. 6, where the semiconductor structure in fig. 6 is similar to the semiconductor structure in fig. 4, and the surface of the semiconductor substrate 11, the surface of the first gate electrode 13, and the surface of the second gate electrode 15 remain the cover layer 16. In this embodiment, the ionized metal plasma process and the photoresist removing process in the first doping process consume part of the cover layer 16, and compared with fig. 6 and 5, the thickness of the cover layer 16 in fig. 6 is significantly reduced, but the cover layer 16 can still completely cover the surface of the semiconductor substrate 11, the surface of the first gate electrode 13 and the surface of the second gate electrode 15, so as to protect the surface of the semiconductor substrate 11, the surface of the first gate electrode 13 and the surface of the second gate electrode 15.
Referring to step S15 and fig. 7, a second patterned passivation layer 18 is formed on the surface of the cover layer 16, and a second doping process is performed on the exposed region of the second patterned passivation layer 18.
The second doping process includes a photolithography process, the material of the second patterned protective layer 18 is photoresist, and the second patterned protective layer 18 is obtained by imprinting a silicon wafer and photolithography. In this embodiment, the exposed area of the second patterned protection layer 18 is located in the first area 111, the exposed area of the second patterned protection layer 18 is an area on two sides of the first gate electrode 13 in the second area 111, and the area covered by the second patterned protection layer 18 is a protected area. The withstand voltage of the first gate electrode 13 is 5V, and a second doping process is performed in the regions on both sides of the first gate electrode 13.
In another embodiment, the exposed area of the second patterned passivation layer 18 is located in the second area 112, and the exposed area of the second patterned passivation layer 18 is the area on both sides of the second gate electrode 15 in the second area 112, i.e. a second doping process is performed on the area on both sides of the second gate electrode 15.
In this embodiment, the second Doping process is a High Doping (HD) process.
The high doping process includes an ionized metal plasma process, which may create highly doped regions in the exposed regions of the second patterned protective layer 18 by plasma implantation. N-type doping is needed to increase the number of free electrons of negative charges when manufacturing N-type transistors, and P-type doping is needed to increase the number of positive charges when manufacturing P-type transistors, and P-HD processing is performed.
Referring to step S16 and fig. 8, the second patterned protective layer 18 is removed. The second patterned protective layer 18 is removed using a photoresist removal (PR Strip) process. In this embodiment, a wet cleaning process is used to remove the second patterned protective layer 18.
As shown in fig. 8, after the second patterned protective layer 18 is removed, the surface of the semiconductor substrate 11, the surface of the first gate structure including the first gate electrode 13 and the first gate oxide layer 12 at the bottom thereof, and the surface of the second gate structure including the second gate electrode 15 and the second gate oxide layer 14 at the bottom thereof are further covered with the remaining covering layer 16. In the present embodiment, the remaining cover layer 16 cannot entirely cover the surface of the semiconductor substrate 11, the first gate structure, and the second gate structure. In some embodiments, the remaining capping layer 16 still completely covers the semiconductor substrate 11 surface, the first gate structure surface, and the second gate structure surface, but the thickness of the capping layer 16 becomes thinner.
Correspondingly, this step further includes removing the capping layer 16 to expose the surface of the semiconductor substrate 11, a first gate structure including the first gate electrode 13 and the first gate oxide layer 12 at the bottom thereof, and a second gate structure including the second gate electrode 15 and the second gate oxide layer 14 at the bottom thereof, so that the device structure after the doping process is completed returns to fig. 3. In this embodiment, a wet etch is used to remove the remaining cap layer 16.
In this embodiment, the semiconductor structure is manufactured by the semiconductor structure manufacturing method by performing the doping process twice, and in some embodiments, the semiconductor structure is manufactured by the semiconductor structure manufacturing method by performing the doping process more than twice, and the cover layer 16 is removed after the last doping process is completed.
In this embodiment, referring to fig. 9, after step S16 is performed, a sidewall 19 is further formed on the sides of the first gate structure and the second gate structure. That is, after doping is completed and the capping layer 16 is removed, sidewalls 19 are formed on the sides of the first gate structure and the second gate structure on the basis of the device structure shown in fig. 3. Wherein the first gate structure comprises the first gate electrode 13 and the first gate oxide layer 12, and the second gate structure comprises the second gate electrode 15 and the second gate oxide layer 14. The material of the side wall 19 is silicon oxide or silicon nitride.
Based on the same inventive concept, the invention also provides a semiconductor structure.
Referring to fig. 3 to 8, the semiconductor structure is manufactured by a semiconductor structure manufacturing method, and the manufacturing process has the technical characteristics of the semiconductor structure manufacturing method. The method specifically comprises the steps of providing a semiconductor substrate 11, providing the semiconductor substrate 11, wherein the semiconductor substrate 11 comprises a first area 111 and a second area 112, the first area 111 is used for manufacturing a transistor with first voltage endurance capability, the second area 112 is used for manufacturing a transistor with second voltage endurance capability, a first gate electrode 13 is formed on the surface of the first area 111, a first gate oxide layer 12 is arranged at the bottom of the first gate electrode 13, a second gate electrode 15 is formed on the surface of the second area 112, a second gate oxide layer 14 is arranged at the bottom of the second gate electrode 15, a covering layer 16 is generated on the surface of the semiconductor substrate 11, referring to the step S13, a first patterned protective layer 17 is formed on the surface of the covering layer 16, a first doping process is performed on the exposed area of the first patterned protective layer 17, the step S14 is removed, the covering layer 17 is reserved, a second patterned protective layer 18 is formed on the surface of the covering layer 16, a second patterned protective layer 18 is formed on the exposed area of the second patterned protective layer 18, the second patterned protective layer 17 is performed on the exposed area of the second patterned protective layer 18, the second patterned protective layer is formed on the exposed area of the first patterned protective layer 17, and the second patterned protective layer 18 is positioned on the exposed area of the first patterned protective layer 17, and the second patterned protective layer 17 is positioned on the exposed area of the exposed area 111.
In this embodiment, the exposed area of the first patterned protection layer 17 is located in the second area 112, the exposed area of the first patterned protection layer 17 is the area on two sides of the second gate electrode 15 in the second area 112, and the exposed area of the second patterned protection layer 18 is the area on two sides of the first gate electrode 13 in the second area 111.
Referring to fig. 2, in this embodiment, before forming the device structure of the semiconductor substrate shown in fig. 3, a first gate oxide material layer 120 that is continuously distributed is formed on the surface of the first region 111, and a second gate oxide material layer 140 that is continuously distributed is formed on the surface of the second region 112, where the materials of the first gate oxide material layer 120 and the second gate oxide material layer 140 are both silicon oxide. Accordingly, the step further includes removing the first gate oxide material layer 120 and the second gate oxide material layer 140 exposed on the surface of the semiconductor substrate 11, where the first gate oxide material layer 120 remaining at the bottom of the first gate electrode 13 forms the first gate oxide layer 12, and the second gate oxide material layer 140 remaining at the bottom of the second gate electrode 15 forms the second gate oxide layer 14.
According to the technical scheme, the covering layer is generated on the surface of the semiconductor substrate, which comprises the first area for manufacturing the transistor with the first voltage endurance capability and the second area for manufacturing the transistor with the second voltage endurance capability, the first patterned protective layer is formed on the surface of the covering layer, the first doping process is performed on the exposed area of the first patterned protective layer, the first patterned protective layer is removed, the covering layer is reserved, the second patterned protective layer is formed on the surface of the covering layer, the second doping process is performed on the exposed area of the second patterned protective layer, the second patterned protective layer is removed, the surface of the active area is protected from being exposed to air and not being corroded in the ionized metal plasma doping and cleaning process, the uniformity of the overall height of the active area can be effectively protected, the stability of the device is improved, the yield and the reliability of the device are improved, and the service life is prolonged.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprise," "include," or any other variation thereof, are intended to cover a non-exclusive inclusion. In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be comprehended within the scope of the present invention.
Claims (15)
1. A method of fabricating a semiconductor structure, comprising:
Providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, the first region is used for manufacturing a transistor with first voltage withstand capability, the second region is used for manufacturing a transistor with second voltage withstand capability, a first gate electrode is formed on the surface of the first region, a first gate oxide layer is arranged at the bottom of the first gate electrode, a second gate electrode is formed on the surface of the second region, and a second gate oxide layer is arranged at the bottom of the second gate electrode;
generating a covering layer on the surface of the semiconductor substrate;
Forming a first patterned protective layer on the surface of the covering layer, and executing a first doping process on the exposed area of the first patterned protective layer;
removing the first patterned protective layer and reserving the covering layer;
Forming a second patterned protective layer on the surface of the covering layer, and executing a second doping process on the exposed area of the second patterned protective layer, wherein the exposed area of the first patterned protective layer is positioned in the first area, the exposed area of the second patterned protective layer is positioned in the second area, or the exposed area of the first patterned protective layer is positioned in the second area and the exposed area of the second patterned protective layer is positioned in the first area;
And removing the second patterned protective layer.
2. The method of claim 1, wherein the first region surface is formed with a continuous distribution of a first gate oxide material layer, the second region surface is formed with a continuous distribution of a second gate oxide material layer, and the step of forming a cap layer on the semiconductor substrate surface is preceded by removing the first gate oxide material layer and the second gate oxide material layer exposed on the semiconductor substrate surface, wherein the first gate oxide material layer remaining on the bottom of the first gate electrode forms the first gate oxide layer, and wherein the second gate oxide material layer remaining on the bottom of the second gate electrode forms the second gate oxide layer.
3. The method of claim 2, wherein the first and second gate oxide material layers exposed at the surface of the semiconductor substrate are removed using a wet etch.
4. The method of claim 1, wherein the material of the first gate electrode and the second gate electrode is polysilicon.
5. The method of claim 1, wherein the material of the capping layer is silicon oxide.
6. The method of claim 1, wherein chemical vapor deposition is used to form a capping layer on the surface of the semiconductor substrate.
7. The method of claim 1, wherein the first patterned protective layer exposes regions of the first region that are on either side of the first gate electrode and the second patterned protective layer exposes regions of the second region that are on either side of the second gate electrode, or
The exposed area of the first patterned protective layer is the area at two sides of the second gate electrode in the second area, and the exposed area of the second patterned protective layer is the area at two sides of the first gate electrode in the first area.
8. The method of claim 1, wherein the material of the first patterned protective layer and the second patterned protective layer is photoresist.
9. The method of claim 8, wherein the first patterned protective layer and the second patterned protective layer are removed separately using a wet cleaning process.
10. The method of claim 1, wherein said removing said second patterned protective layer further comprises removing said cap layer to expose said semiconductor substrate surface, a first gate structure comprising said first gate electrode and said first gate oxide layer at its bottom, and a second gate structure comprising said second gate electrode and said second gate oxide layer at its bottom.
11. The method of claim 10, wherein the step of removing the second patterned protective layer further comprises forming a sidewall on a side of the first gate structure and the second gate structure.
12. The method of claim 11, wherein the sidewall material is silicon oxide or silicon nitride.
13. The method of claim 1, wherein the first doping process is a lightly doped drain process and the second doping process is a highly doped process.
14. The method of claim 13, wherein the lightly doped drain process and the highly doped process further comprise a photolithography process and an ionized metal plasma process.
15. A semiconductor structure, characterized in that, the semiconductor structure is manufactured by the manufacturing method of the semiconductor structure according to any one of claims 1 to 14.
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| CN202411390018.7A CN119277813A (en) | 2024-09-30 | 2024-09-30 | Semiconductor structure and manufacturing method |
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