CN119277814B

CN119277814B - A GaN-based monolithic integrated CMOS circuit

Info

Publication number: CN119277814B
Application number: CN202411312259.XA
Authority: CN
Inventors: 周靖贵; 周琦; 张波; 唐磊; 高欢; 杨宁; 黄启航; 马滦熙; 刘文正
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2024-09-20
Filing date: 2024-09-20
Publication date: 2025-09-30
Anticipated expiration: 2044-09-20
Also published as: CN119277814A

Abstract

The present invention belongs to the field of power semiconductor technology, and in particular relates to a GaN-based monolithic integrated CMOS circuit. The circuit of the present invention replaces the traditional AlGaN barrier layer with a fixed Al component with a linearly gradient Al component, specifically a linearly gradient AlGaN barrier layer that decreases linearly from bottom to top. The 3DHG induced by the polarization difference of the linearly gradient AlGaN barrier layer plus the 2DHG formed at the heterojunction interface between the GaN channel and the linearly gradient AlGaN barrier increase the overall concentration of the hole gas, thereby improving the on-current density of p-FETs. The structure of the present invention helps to improve the on-current density of p-FETs, increase the P/N channel compatibility, reduce the on-current mismatch of p-/n-FETs in monolithic integration, and promote the development of CMOS-based all-GaN monolithic power integrated ICs.

Description

GaN-based monolithic integrated CMOS circuit

Technical Field

The invention belongs to the technical field of power semiconductors, and particularly relates to a GaN-based monolithic integrated CMOS circuit.

Background

Compared with the traditional Si-based device, the GaN power device has remarkable advantages in electron saturation speed, forbidden bandwidth and critical breakdown electric field, and for example, the 2DEG with high concentration and high mobility at the AlGaN/GaN heterojunction becomes the unique characteristic of the GaN power device. The monolithic integration based on the on-chip GaN CMOS not only enables the circuit design to be simple, but also reduces the influence of parasitic inductance, and the most energy-saving and efficient integrated topological structure with low static power consumption and strong noise immunity of the whole power switch system is realized. GaN-based P-channel Field Effect Transistors (FETs) offer the possibility of on-chip CMOS. However, due to factors such as low hole mobility at normal temperature of GaN, difficulty in being greatly improved, high ohmic contact resistivity of drain electrode and source electrode of the device and the like, the on-state current density of GaN p-FETs is far lower than that of corresponding n-FETs, and the on-state current density of GaN p-FETs is a main obstacle for realizing CMOS monolithic integration currently.

Therefore, to solve this problem, increasing the on-current density of p-FETs is the most effective method from the standpoint of increasing the hole concentration. At present, the GaN-based P/N double-channel stacked heterojunction epitaxial structure for increasing the hole concentration based on increasing the heterojunction polarization intensity can cause the problems of N-FETs device threshold voltage degradation, conduction current density reduction, leakage current increase, poor P/N channel performance compatibility, overhigh P/N channel cooperative regulation coupling degree and the like.

Disclosure of Invention

Aiming at the problems, in order to realize the enhancement type GaN P-FETs with high on-current density, and monolithically integrate the CMOS device with the enhancement type N-FETs on the same epitaxial structure, and avoid the degradation of the threshold voltage of the N-FETs and the improvement of the P/N channel compatibility, the invention provides a GaN-based epitaxial structure and a monolithically integrated CMOS circuit.

The invention adopts the technical scheme that:

A monolithic integrated CMOS circuit based on GaN base, including p-FETs and n-FETs, the shared structure of p-FETs and n-FETs is a substrate 01, III nitride buffer layer 02, gaN channel layer 03 and AlGaN barrier layer 04 that are laminated and set up sequentially along the vertical direction, wherein Al composition in AlGaN barrier layer 04 is linear gradual change, gradual change mode is gradually decreasing from bottom to top, and AlGaN barrier layer of p-FETs and AlGaN barrier layer of n-FETs are isolated each other;

The AlGaN barrier layer of the P-FETs is transversely provided with a 3DHG which is induced by polarization due to gradual change of polarization intensity, the upper surface of the AlGaN barrier layer is provided with a GaN channel layer 05, a 2DEG is formed at the interface of the AlGaN barrier layer of the P-FETs and the GaN channel layer 05, the upper surface of the GaN channel layer 05 is provided with a P-type heavily doped GaN layer 06, the two ends of the upper surface of the P-type heavily doped GaN layer 06 are respectively provided with P-FETs source ohmic metal 07 and P-FETs drain ohmic metal 08, wherein the P-FETs drain ohmic metal 08 is positioned at one side close to the n-FETs, a groove gate structure is arranged between the P-FETs source ohmic metal 07 and the P-FETs drain ohmic metal 08, the groove gate structure comprises a gate medium 13 and a first gate metal 09, the gate medium 13 is positioned in a groove formed on the upper surface of the P-type heavily doped GaN layer 06, the lower part of the first gate metal 09 is wrapped and the two sides of the first gate medium 09 are respectively contacted with the P-FETs source ohmic metal 07 and the P-FETs drain ohmic metal 08;

The upper surface of the AlGaN barrier layer structure of the n-FETs is also provided with a GaN channel layer 05, the upper surface of the GaN channel layer 05 is provided with a P-type heavily doped GaN layer 06, different from the P-FETs, the partial upper layer of the AlGaN barrier layer of the n-FETs, the two sides of the GaN channel layer 05 and the P-type heavily doped GaN layer 06 are etched, only partial regions of the middle grid are reserved, the interface between the AlGaN barrier layer of the n-FETs and the GaN channel layer 03 is formed, the two sides of the upper surface of the AlGaN barrier layer of the n-FETs are respectively provided with an n-FETs drain electrode ohmic metal 10 and an n-FETs source electrode ohmic metal 1, wherein the n-FETs drain electrode ohmic metal 10 is positioned at one side close to the P-FETs, and the upper surface of the P-type heavily doped GaN layer 06 of the n-FETs is provided with a second grid metal 12 to form a plane grid;

The p-FETs source ohmic metal 07 is a high-level signal port of the CMOS circuit, the n-FETs source ohmic metal 1 is a low-level signal port of the CMOS circuit, the first gate metal 09 and the second gate metal 12 are connected to be an input level signal port of the CMOS circuit, and the p-FETs drain ohmic metal (8) and the n-FETs drain ohmic metal 10 are connected to be an output level signal port of the CMOS circuit.

Further, the substrate 01 is made of one of Si, sapphire and SiC.

Further, the p-FETs source ohmic metal 07 and the p-FETs drain ohmic metal 08 are made of any one of Pd/Au/Ni, ni/Au, pd/Ni.

Further, the first gate metal 09 is made of any one of Ti/Au, W/Au, ni/Au, mo/Au, and Ru.

Further, the gate dielectric 13 is any one of an oxide layer and an insulating layer.

Further, the n-FETs drain ohmic metal 10 and the n-FETs source ohmic metal 1 are made of any one of Ti/Au, ti/Al/Ni/Au and Ti/Al.

Further, the contact between the second gate metal 12 and the P-type heavily doped GaN layer 06 is an ohmic contact, and the material used for the second gate metal 12 is Ni/Au.

The invention has the beneficial effects that based on a commercial enhancement type p-GaN gate HEMTs epitaxial structure, the AlGaN barrier layer with the traditional fixed Al component is replaced by the linear gradual change AlGaN barrier layer with the Al component linearly decreasing from bottom to top, the 3DHG induced by the polarization difference of the linear gradual change AlGaN barrier layer is added with the 2DHG formed by the intersection interface of the GaN channel and the linear gradual change AlGaN barrier heterojunction, so that the overall concentration of hole gas is increased, and the on current density of the p-FETs is further improved. Meanwhile, the 3DHG widens the spatial distribution of the P channel and improves the conductivity of the barrier layer. The graded AlGaN barrier layer can also be helpful for the depletion of the concentration of the AlGaN/GaN heterojunction interface 2DEG by the P-type heavily doped GaN, so that the threshold voltage of the n-FETs is increased. In the preparation process of the N-FETs P-GaN gate, the P-type heavily doped GaN layer, the GaN channel layer and part of the linear graded AlGaN barrier layer in all gate drain/gate source regions are etched, so that the 2DEG depleted by the P-type heavily doped 2DHG and 3DHG can be recovered, the linear graded AlGaN barrier layer is etched to different depths, the 2DEG concentration in the N-FETs gate drain/gate source regions is different, and an adjustable N channel is realized. The adjustability of the conduction characteristic of the N channel is beneficial to improving the compatibility of the P/N channel, reducing the conduction current mismatch degree of P-/N-FETs in monolithic integration and promoting the development of the full GaN monolithic power integrated IC based on CMOS.

Drawings

Fig. 1 is a schematic diagram of an epitaxial structure of a device according to the present invention.

Fig. 2 shows the trend of the Al composition in the linear graded AlGaN barrier layer according to the present invention.

FIG. 3 is a schematic diagram of the structure of the device according to the present invention after etching the P-FETs gate recess in the P-FETs region, etching the P-type heavily doped GaN layer, gaN channel layer and partial linear graded AlGaN barrier layer in the n-FETs gate drain/gate source region, and etching the isolation region of the P-FETs and n-FETs device.

Fig. 4 is a schematic diagram of the complete structure of the GaN-based CMOS device based on the graded AlGaN barrier layer and the tunable N-channel monolithically integrated epitaxial structure according to the present invention.

Fig. 5 is a schematic diagram of a CMOS circuit topology according to the present invention.

Detailed Description

The technical scheme of the present invention is described in detail below in conjunction with the accompanying drawings.

The preparation method of the GaN-based monolithic integrated CMOS circuit provided by the invention is that an epitaxial structure shown in fig. 1 is prepared firstly, and the epitaxial structure is obtained from bottom to top along the [0001] growth direction in fig. 1, and the epitaxial structure comprises a substrate 01, a III-nitride buffer layer 02 positioned above the substrate 01, a GaN channel layer 03 positioned above the III-nitride buffer layer 02, a linear graded AlGaN barrier layer 04 positioned above the GaN channel layer, a GaN channel layer 05 positioned above the linear graded AlGaN barrier layer 04, and a P-type heavily doped GaN layer 06 positioned above the GaN channel layer 05.

The GaN channel layer 05, the linear graded AlGaN barrier layer 04 and the GaN channel layer 03 form a multidimensional heterojunction, a 2DHG is formed at the heterojunction interface of the GaN channel layer 05 and the linear graded AlGaN barrier layer 04, a 3DHG is formed in the linear graded AlGaN barrier layer 04, and a 2DEG is formed at the heterojunction interface of the linear graded AlGaN barrier layer 04 and the GaN channel layer 03. The trend of the Al composition in the linear graded AlGaN barrier layer is shown in fig. 2.

The surface of the CMOS device is provided with a p-FETs device region, an isolation region formed by etching or ion implantation between the p-FETs and the n-FETs and an n-FETs device region in sequence from left to right along the transverse direction. Wherein the P-type heavily doped GaN layer 06, gaN channel layer 05 and part of the linear graded AlGaN barrier layer 04 of the n-FETs region drain/gate source region are etched away. As shown in fig. 3.

The surface of the P-FETs device is provided with a source structure formed by a P-type heavily doped GaN layer 06 and source metal 07 in sequence from left to right in the transverse direction, and the source ohmic metal 07 is contacted with the top of the P-type heavily doped GaN layer 06. The drain electrode structure is composed of a P-type heavily doped GaN layer 06 in the drain electrode region of the P-FETs and drain electrode metal 08, and the other end of the drain electrode ohmic metal 08, which is far away from the upper surface of the P-FETs of the source electrode structure, is contacted with the top of the P-type heavily doped GaN layer 06. The P-FETs gate structure etches away part or all of the P-type heavily doped GaN layer 06 outside the drain and source regions, or etches away part or all of the P-type heavily doped GaN layer 06 in the gate region, on the P-type heavily doped GaN layer 06 or GaN channel layer 05 between the source structure and the drain structure, the gate structure includes a gate dielectric 13 deposited on the gate metal 09 deposited on the gate recess and on the surface of the P-type heavily doped GaN layer 06 or GaN channel layer 05 between the drain and the source.

The surface of the n-FETs device is sequentially provided with a drain structure formed by a part of linear gradient AlGaN barrier layer 04 of a drain region of the n-FETs and drain metal 10 from left to right along the transverse direction, and the drain ohmic metal 10 is contacted with the top of the part of linear gradient AlGaN barrier layer 04 left after etching. The source electrode structure is composed of a linear gradient AlGaN barrier layer 04 at the source electrode region part of the n-FETs and source electrode metal 11, wherein the other end of the source electrode ohmic metal 11, which is far away from the upper surface of the n-FETs of the drain electrode structure, is contacted with the top of the linear gradient AlGaN barrier layer 04 at the part which is left after etching. The n-FETs P-GaN gate structure is located between the n-FETs source and drain structures and includes gate metal 12 deposited on the P-type heavily doped GaN layer 06.

In the CMOS device, the p-FETs source metal 07 is used as a CMOS circuit to be connected with a high-level signal VDD end, the n-FETs source metal 11 is used as a grounding or low-level signal GND end of the CMOS circuit, the p-FETs drain metal 08 and the n-FETs drain metal 10 are connected together to be used as output level signal ends of the CMOS circuit, and the p-FETs gate metal 09 and the n-FETs gate metal 12 are connected together to be used as input level signal ends of the CMOS circuit, as shown in FIG. 5.

The working principle of the GaN-based epitaxial structure and the monolithic integrated CMOS circuit provided by the invention is as follows:

The current commercial enhancement type P-GaN gate HEMTs epitaxial structure has the problems of poor P-FETs conduction characteristic, high P-/N-FETs current mismatch degree, large device area difference, poor P/N channel cooperative regulation and control capability and compatibility and the like. Fig. 4 is a schematic structural diagram of a device according to the present invention, in which a 3DHG generated by a linear graded AlGaN barrier layer makes the P channel distributed not only at the 2DHG of the heterojunction interface between the GaN channel layer and the linear graded AlGaN barrier layer, but also across the linear graded AlGaN barrier layer in the 3 DHG. And from the point of improving the overall concentration of hole carriers and the width of a P channel, the enhanced P-FETs with high on-current density is realized. In the N-FETs based on the p-GaN gate structure, the linearly graded AlGaN is helpful for the p-GaN gate to deplete the concentration of the N-channel 2DEG below, and increases the gate control capability and threshold voltage of the N-FETs. And etching away part of the linear gradient AlGaN barrier layer in the N-FETs gate drain/gate source region, wherein the Al component of the linear gradient AlGaN barrier layer linearly decreases from bottom to top, so that the reserved part of high Al component is beneficial to the recovery of the concentration of 2DEG, and the adjustability of the N channel transport capacity is realized. Therefore, the CMOS inverter with small current mismatch degree and high P/N channel compatibility is integrated on the same epitaxial structure in a single chip mode.

Claims

1. A GaN-based monolithic integrated CMOS circuit, characterized in that it includes p-FETs and n-FETs, wherein the p-FETs and n-FETs have a common structure of a substrate (01), a group III nitride buffer layer (02), a GaN channel layer (03), and an AlGaN barrier layer (04) stacked in sequence in a vertical direction, wherein the Al component in the AlGaN barrier layer (04) is linearly gradient, and the gradient is gradually reduced from bottom to top, and the AlGaN barrier layer of the p-FETs and the AlGaN barrier layer of the n-FETs are isolated from each other;

A 3DHG induced by polarization intensity gradient is distributed across the AlGaN barrier layer of the p-FETs, a GaN channel layer (05) is provided on the upper surface of the AlGaN barrier layer, a 2DEG is formed at the interface between the AlGaN barrier layer of the p-FETs and the GaN channel layer (05), and a P-type heavily doped GaN layer (06) is provided on the upper surface of the GaN channel layer (05); and a p-FETs source ohmic metal (07) and a p-FETs drain ohmic metal (08) are provided at both ends of the upper surface of the P-type heavily doped GaN layer (06), wherein The p-FETs drain ohmic metal (08) is located on a side close to the n-FETs; a groove gate structure is provided between the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08), the groove gate structure comprising a gate dielectric (13) and a first gate metal (09); the gate dielectric (13) is located in a groove formed on the upper surface of the P-type heavily doped GaN layer (06), wraps the lower part of the first gate metal (09), and contacts the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08) on both sides respectively;

The upper surface of the AlGaN barrier layer structure of the n-FETs also has a GaN channel layer (05), and the upper surface of the GaN channel layer (05) has a P-type heavily doped GaN layer (06); different from the p-FETs, part of the upper layer of the AlGaN barrier layer of the n-FETs, the GaN channel layer (05) and both sides of the P-type heavily doped GaN layer (06) are etched away, leaving only a portion of the middle gate area; a 2DEG is formed at the interface between the AlGaN barrier layer and the GaN channel layer (03) of the n-FETs, and both sides of the upper surface of the AlGaN barrier layer of the n-FETs have an n-FETs drain ohmic metal (10) and an n-FETs source ohmic metal (11), wherein the n-FETs drain ohmic metal (10) is located on the side close to the p-FETs; a second gate metal (12) is provided on the upper surface of the P-type heavily doped GaN layer (06) of the n-FETs to form a planar gate;

The p-FETs source ohmic metal (07) is a high-level signal port of the CMOS circuit, the n-FETs source ohmic metal (11) is a low-level signal port of the CMOS circuit, the first gate metal (09) and the second gate metal (12) are connected to form an input-level signal port of the CMOS circuit, and the p-FETs drain ohmic metal (08) and the n-FETs drain ohmic metal (10) are connected to form an output-level signal port of the CMOS circuit.

2. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that the material used for the substrate (01) is one of Si, sapphire and SiC.

3. A GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that the material used for the p-FETs source ohmic metal (07) and the p-FETs drain ohmic metal (08) is any one of Pd/Au/Ni, Ni/Au, and Pd/Ni.

4. A GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that the material used for the first gate metal (09) is any one of Ti/Au, W/Au, Ni/Au, Mo/Au, and Ru.

5. The GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that the gate dielectric (13) is any one of an oxide layer and an insulating layer.

6. A GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that the material used for the n-FETs drain ohmic metal (10) and the n-FETs source ohmic metal (11) is any one of Ti/Au, Ti/Al/Ni/Au, and Ti/Al.

7. A GaN-based monolithic integrated CMOS circuit according to claim 1, characterized in that the contact between the second gate metal (12) and the P-type heavily doped GaN layer (06) is an ohmic contact, and the material used for the second gate metal (12) is Ni/Au.