[go: up one dir, main page]

CN119250013A - Method, device and medium for layout processing - Google Patents

Method, device and medium for layout processing Download PDF

Info

Publication number
CN119250013A
CN119250013A CN202411317175.5A CN202411317175A CN119250013A CN 119250013 A CN119250013 A CN 119250013A CN 202411317175 A CN202411317175 A CN 202411317175A CN 119250013 A CN119250013 A CN 119250013A
Authority
CN
China
Prior art keywords
layout
attribute
splitting
decision tree
target
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202411317175.5A
Other languages
Chinese (zh)
Inventor
请求不公布姓名
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Manufacturing EDA Co Ltd
Original Assignee
Advanced Manufacturing EDA Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Manufacturing EDA Co Ltd filed Critical Advanced Manufacturing EDA Co Ltd
Priority to CN202411317175.5A priority Critical patent/CN119250013A/en
Publication of CN119250013A publication Critical patent/CN119250013A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/70Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70491Information management, e.g. software; Active and passive control, e.g. details of controlling exposure processes or exposure tool monitoring processes
    • G03F7/70508Data handling in all parts of the microlithographic apparatus, e.g. handling pattern data for addressable masks or data transfer to or from different components within the exposure apparatus
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605Workpiece metrology
    • G03F7/706835Metrology information management or control
    • G03F7/706837Data analysis, e.g. filtering, weighting, flyer removal, fingerprints or root cause analysis
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/20Design optimisation, verification or simulation
    • G06F30/27Design optimisation, verification or simulation using machine learning, e.g. artificial intelligence, neural networks, support vector machines [SVM] or training a model
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00Computing arrangements using knowledge-based models
    • G06N5/01Dynamic search techniques; Heuristics; Dynamic trees; Branch-and-bound
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/30Computing systems specially adapted for manufacturing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Geometry (AREA)
  • Data Mining & Analysis (AREA)
  • Software Systems (AREA)
  • Computational Linguistics (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Medical Informatics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

根据本公开的示例实施例提供了用于版图处理的方法、设备和介质。在该方法中,确定分别与多个参考版图对应的多个参考拆分策略。每个参考版图由对应的参考拆分策略进行拆分所得到的拆分质量满足预定条件。该方法还包括确定多个参考版图的相应属性信息,属性信息包括多个版图属性的属性值。该方法还包括基于多个参考拆分策略和多个参考版图的相应属性信息,确定用于版图拆分的决策树模型。决策树模型包括多个属性节点和多个策略节点。每个属性节点对应于一个版图属性的属性值。每个策略节点对应于一个参考拆分策略。以此方式,可以利用根据参考拆分策略得到的决策树模型来对版图的拆分策略进行预测,从而找到适当的版图拆分方式。

According to an example embodiment of the present disclosure, a method, device and medium for layout processing are provided. In the method, multiple reference splitting strategies corresponding to multiple reference layouts are determined. The splitting quality obtained by splitting each reference layout by the corresponding reference splitting strategy meets a predetermined condition. The method also includes determining the corresponding attribute information of the multiple reference layouts, and the attribute information includes the attribute values of multiple layout attributes. The method also includes determining a decision tree model for layout splitting based on the multiple reference splitting strategies and the corresponding attribute information of the multiple reference layouts. The decision tree model includes multiple attribute nodes and multiple strategy nodes. Each attribute node corresponds to the attribute value of a layout attribute. Each strategy node corresponds to a reference splitting strategy. In this way, the decision tree model obtained according to the reference splitting strategy can be used to predict the splitting strategy of the layout, so as to find an appropriate layout splitting method.

Description

Method, apparatus and medium for layout processing
The application is a divisional application of China patent application 202410885914.4 with the application date of 2024, 7 and 2, entitled "method, apparatus and Medium for layout processing".
Technical Field
Embodiments of the present disclosure relate generally to the field of integrated circuits and, more particularly, relate to methods, apparatuses, and media for layout processing.
Background
A circuit layout (which may be simply referred to as a layout) is a series of graphs converted from a designed and simulated optimized circuit, and includes physical information data related to devices such as integrated circuit dimensions, topology definitions of various layers, and the like. The integrated circuit manufacturer manufactures a mask from this data. The layout pattern on the mask determines the size of the on-chip device or the connection physical layer.
As technology nodes of integrated circuit fabrication processes decrease, distances between target patterns in an integrated circuit decrease, and densities of layout patterns on a mask corresponding to the target patterns increase. Due to the resolution limit of lithography, for a layout with dense layout patterns, it is difficult to use a single mask for lithographic imaging. For this reason, the fabrication of a precursor process using multiple exposure lithography (Multiple Patterning Lithography) has been proposed. The multiple exposure photoetching process is to split the layout pattern onto a plurality of different masks, and finally form a complete wafer pattern through the iterative process of multiple exposure and etching.
Disclosure of Invention
In a first aspect of the present disclosure, a method for layout processing is provided. The method includes determining a plurality of reference split policies that respectively correspond to a plurality of reference layouts. And splitting each reference layout by a corresponding reference splitting strategy to obtain splitting quality meeting a preset condition. The method further includes determining corresponding attribute information for the plurality of reference layouts, the attribute information including attribute values for the plurality of layout attributes. The method further includes determining a decision tree model for layout splitting based on the plurality of reference splitting policies and the respective attribute information of the plurality of reference layouts. The decision tree model includes a plurality of attribute nodes and a plurality of policy nodes. Each attribute node corresponds to an attribute value of a layout attribute. Each policy node corresponds to a reference split policy.
In a second aspect of the present disclosure, a method for layout splitting is provided. The method includes obtaining a decision tree model including a plurality of attribute nodes and a plurality of policy nodes. Each attribute node corresponds to an attribute value of one of the plurality of layout attributes, and each policy node corresponds to one of the plurality of reference split policies. The method further includes determining a target split strategy for the target layout using the decision tree model based on target attribute values for a plurality of layout attributes of the target layout.
In some embodiments, determining a target split policy for the target layout includes determining a target path corresponding to target attribute values of a plurality of layout attributes from a decision tree model and a target policy node to which the target path points, and determining a reference split policy indicated by the target policy node as the target split policy.
In some embodiments, the layout splitting method further comprises splitting the target layout based on a target splitting strategy, determining a performance index of the decision tree model based on a splitting result of the splitting of the target layout, and updating the decision tree model by adjusting the structure of the decision tree model if the performance index is determined to be lower than a threshold.
In some embodiments, updating the decision tree model by adjusting the structure of the decision tree model includes deleting at least one attribute node on a branch of the decision tree model or adjusting a branch of the decision tree model including at least one attribute node and at least one policy node on the branch.
In some embodiments, the decision tree model is constructed by determining a plurality of reference splitting policies corresponding to a plurality of reference layouts, respectively, each reference layout being split by the corresponding reference splitting policy such that a split quality satisfies a predetermined condition, and determining the decision tree model based on the plurality of reference splitting policies and attribute values of a plurality of layout attributes of the plurality of reference layouts.
In a third aspect of the present disclosure, an electronic device is provided. The electronic device includes a processor, and a memory coupled to the processor. The memory has instructions stored therein that, when executed by the processor, cause the electronic device to perform a method according to the first or second aspect of the present disclosure.
In a fourth aspect of the present disclosure, a computer-readable storage medium is provided. The computer readable storage medium has a computer program stored thereon. The computer program, when executed by a processor, implements the method according to the first or second aspect of the present disclosure.
As will be appreciated from the following description, according to an embodiment of the present disclosure, a decision tree model for layout splitting is generated based on a plurality of reference splitting policies corresponding to a plurality of reference layouts and attribute values of respective layout attributes of the plurality of reference layouts. The attribute nodes of the decision tree model correspond to attribute values of a layout attribute. The policy node corresponds to a reference split policy. By utilizing the decision tree model obtained in the method, the splitting strategy of the layout to be split can be predicted. In this way, an optimized layout splitting result can be obtained, thereby improving the multiple exposure lithography result. Other benefits will be described below in connection with the corresponding embodiments.
It should be understood that what is described in this summary is not intended to limit the critical or essential features of the embodiments of the disclosure nor to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of embodiments of the present disclosure will become more apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, wherein like or similar reference numerals designate like or similar elements, and wherein:
FIG. 1 illustrates a schematic diagram of an example environment in which embodiments of the present disclosure can be implemented;
FIG. 2 illustrates a flow chart of a method for layout processing according to some embodiments of the present disclosure;
FIG. 3 illustrates a schematic diagram of a decision tree model, according to some embodiments of the present disclosure;
FIG. 4 illustrates a flowchart of a method of determining a split strategy for a target layout using a decision tree model, according to some embodiments of the present disclosure;
FIG. 5 illustrates a flow chart of a process of determining a split policy of a target layout using a decision tree model and updating the decision tree model in accordance with some embodiments of the present disclosure, and
Fig. 6 illustrates a block diagram of an electronic device in which one or more embodiments of the disclosure may be implemented.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure have been shown in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustration purposes only and are not intended to limit the scope of the present disclosure.
In describing embodiments of the present disclosure, the term "comprising" and its like should be taken to be open-ended, i.e., including, but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like, may refer to different or the same object. Other explicit and implicit definitions are also possible below.
As mentioned briefly above, it is difficult to use a single mask for lithographic imaging for layout with dense layout patterns due to the resolution limitations of lithography. For example, design layers with minimum pitches below 78nm cannot be lithographically imaged using a single mask due to the resolution limitations of 193 nanometer (nm) Deep Ultraviolet (DUV) lithography. With the continued advancement of technology nodes, starting with nodes such as 16nm, chip manufacturers use multiple exposure techniques for advanced process fabrication.
One approach to multiple exposure is to abstract the components of the corresponding layers of the chip layout and the distances between the components into a logical map. The splitting method is abstracted into a graph dyeing method. The solution of the graph staining technique is strongly related to the complexity of the formed graph. The figure staining problem is a difficult problem in determining the existence of solutions. Current graph staining algorithms are directed at finding a viable staining solution at an approximate level by making a limited number of attempts as fast as possible.
In order to achieve the goal of quickly searching for a dyeing scheme and a layout splitting scheme, path selection needs to be made according to the distribution characteristics of the map abstracted from the layout. Because the manufacturing process and the layers of the chip layout are different, the graphs have larger difference. Therefore, a single layout splitting path selection scheme is difficult to accommodate various types of layout requirements. Such limitations may lead to significant differences in splitting performance across different layouts, and even effective splitting results may not be obtained when severe.
To this end, embodiments of the present disclosure propose a method for layout processing. According to an embodiment of the present disclosure, a decision tree model is utilized for layout splitting. For example, a decision tree model may be utilized to generate a target split policy for a target layout. The decision tree model is obtained based on layout attribute values of a plurality of reference layouts and a plurality of reference splitting strategies corresponding to the plurality of reference layouts. The decision tree model includes a plurality of attribute nodes and a plurality of policy nodes. Each attribute node corresponds to an attribute value of a layout attribute. Each policy node corresponds to a reference split policy. In this way, the decision tree model obtained according to the reference splitting strategy can be utilized to predict the splitting strategy of the layout, so that a proper layout splitting mode can be found.
As an example, in the splitting process of the target layout, based on the attribute value of the layout attribute of the target layout, the policy node pointed to by the attribute node matched with the target layout and the reference splitting policy of the policy node can be found from the decision tree model. The reference splitting strategy determination mode is simple and quick, and can adapt to different attributes of different layouts. Therefore, layout splitting time can be saved, and multiple exposure efficiency can be improved.
Various example implementations of this scheme will be described in detail below with reference to the accompanying drawings.
Referring initially to FIG. 1, a schematic diagram of an example environment 100 in which embodiments of the present disclosure can be implemented is shown. The example environment 100 may generally include an electronic device 110.
As shown in fig. 1, the electronic device 110 obtains a plurality of reference layouts 102-1, 102-2, and a plurality of reference split policies 104-1, 102-4, corresponding to the plurality of reference layouts 102-1, 102-2. The reference layout 102-1, 102-2, may be referred to herein as reference layout 102 alone, or collectively referred to as a reference layout 102. The reference layout 102 may be a one-level layout in a layout, also referred to as a one-level mask layout. Reference split policies 104-1, 102-4, may be referred to as reference split policy 104 alone, or collectively referred to as reference split policy 104. The reference splitting strategies of the reference layouts can be splitting strategies with better splitting results tested previously. It should be appreciated that although not shown, each reference layout 102 may have one or more reference patterns thereon. These reference patterns may be the same or different. The reference patterns may be arbitrarily distributed on the reference layout. The scope of the present disclosure is not limited in this respect.
The electronic device 110 may determine the decision tree model 120 based on the plurality of reference layouts 102 and the plurality of reference splitting policies 104. The decision tree model is also referred to herein as a decision forest model. Several examples regarding determining the decision tree model 120 will be described below in connection with fig. 2-3.
Next, the electronic device 110 may utilize the decision tree model 120 to determine a prediction of a splitting policy for the target layout 142 (also referred to as a layout to be split), i.e., the target splitting policy 144. Using the target split policy 144, the electronic device 110 may split the target layout 142. Alternatively, or in addition, in some example embodiments, the electronic device 110 may also transmit the decision tree model 120 to other layout processing devices. The layout processing device may utilize the decision tree model 120 to predict a splitting policy for a layout to be split. It should be appreciated that, although not shown, one or more target patterns may be included on target layout 142. In this context, a target pattern refers to a pattern that is expected to be obtained on a wafer after photolithography. Several examples regarding determining the target split policy 144 of the target layout 142 using the decision tree model 120 will be described below in connection with fig. 4 and 5.
In some embodiments, the electronic device 110 may also interact with a client (not shown). For example, electronic device 110 may receive an input message from a client and output a feedback message to the client. In some embodiments, an input message from a client may specify reference graph 102 and/or specify a reference split policy 104 corresponding to reference graph 102. Electronic device 110 may select reference graph 102 and reference split policy 104 corresponding to reference graph 102 based on the input message from the client for determining decision tree model 120.
In the example environment 100, the electronic device 110 and the electronic device 110 may be any type of device having computing capabilities, including a terminal device or a server device. The terminal device may be any type of mobile terminal, fixed terminal, or portable terminal, including a mobile handset, desktop computer, laptop computer, notebook computer, netbook computer, tablet computer, media computer, multimedia tablet, personal Communication System (PCS) device, personal navigation device, personal Digital Assistant (PDA), audio/video player, digital camera/camcorder, positioning device, television receiver, radio broadcast receiver, electronic book device, game device, or any combination of the preceding, including accessories and peripherals for these devices, or any combination thereof. The server devices may include, for example, computing systems/servers, such as mainframes, edge computing nodes, computing devices in a cloud environment, and so forth.
It should be understood that the structure and function of environment 100 are described for illustrative purposes only and are not meant to suggest any limitation as to the scope of the disclosure. The various layouts and figures therein shown in fig. 1 are merely exemplary and are not intended to limit the scope of the present disclosure. Example embodiments according to the present disclosure will be described in detail below with reference to the accompanying drawings.
Several embodiments of determining the decision tree model 120 and utilizing the decision tree model 120 to determine the target split policy 144 for the target layout 142 are described next. Fig. 2 illustrates a flow chart of a method 200 for layout processing according to some embodiments of the present disclosure. In some embodiments, the method 200 may be performed by the electronic device 110 as shown in fig. 1. It should be understood that method 200 may also include additional blocks not shown and/or may omit certain block(s) shown, the scope of the present disclosure not being limited in this respect.
At block 210, the electronic device 110 determines a plurality of reference split policies 104 corresponding to the plurality of reference layouts 102, respectively. The splitting quality of each reference layout 102, which is split by the corresponding reference splitting policy 104, satisfies a predetermined condition. That is, a split policy that can obtain a split quality satisfying a predetermined condition is taken as the reference split policy 104 of the reference layout 102. In this context, a splitting policy of a layout refers to a rule or method that indicates how to split the layout. The reference layout 102 may be split into any number of layout parts, e.g., two or more layout parts, using the reference splitting policy 104. In the following embodiments, for convenience of description, description will be given taking an example of dividing a layout into two layout parts.
As an example, the split policy of the layout may indicate a direction of the split of the layout, e.g., from left to right, from top to bottom, from top left to bottom right, etc. As another example, a split policy of a layout may indicate a layout split location. For example, splitting from a middle position of the layout may be indicated. As another example, splitting at layout positions with a certain feature (e.g., an elongated pattern) may be indicated. The layout splitting strategy can also be a combination of the layout splitting direction and the layout splitting position. The split strategy described above is merely exemplary and not limiting. The splitting policy of the layout can be arbitrarily set. The scope of the disclosure is not limited in this respect.
In some embodiments, the predetermined condition of the split quality may indicate that the split time of the layout does not exceed a threshold time. The threshold time may be preset or set by the user. That is, the splitting time for splitting the reference layout 102 by the reference splitting policy 104 is short. Additionally, or alternatively, in some embodiments, the predetermined condition may indicate that the split layout pattern distribution ratio is within a predetermined range. For example, the predetermined condition may indicate that the pattern occupancy within the first portion of the split layout is relatively close to the pattern occupancy within the second portion of the layout. That is, the layout pattern occupation ratios in the plurality of split portions obtained by splitting the reference layout 102 by the reference splitting policy 104 are relatively close. As another example, in some examples, the predetermined condition may indicate that splitting the reference layout 102 via the reference splitting policy 104 may result in a correct splitting result. It should be understood that the various predetermined conditions listed above are merely exemplary and are not intended to limit the present solution. More or fewer suitable predetermined conditions may be employed depending on the actual requirements. The scope of the disclosure is not limited in this respect.
In some embodiments, the electronic device 110 may collect various reference layouts 102. For example, individual reference layouts of a vendor may be collected. For the collected reference layout 102, multiple splitting attempts may be made using any suitable splitting tool. The optimal resolution scheme with the best resolution quality among the multiple resolution attempts may be used as the reference resolution policy 104. The resolution policies may also be ordered according to resolution quality. The top-ranked predetermined number of split policies is referred to as the reference split policy 104. For example, N split strategies that can obtain a correct split result and that take the shortest time may be used as reference split strategies, where N is a natural number equal to or greater than 1. Alternatively, in some embodiments, a plurality of split policies that satisfy the predetermined condition may each be used as the reference split policy 104. The respective reference split policies 104 thus determined for the plurality of reference layouts 102 may be used to determine the decision tree model 120.
Alternatively, in some embodiments, the electronic device 110 may receive the plurality of reference layouts 102 and the plurality of reference split policies 104 corresponding to the plurality of reference layouts 102 from a client or other device. These reference splitting policies may be splitting policies that are set empirically by a user, for example, and that enable splitting results to satisfy predetermined conditions.
At block 220, the electronic device 110 determines corresponding attribute information for the plurality of reference layouts 102. The attribute information includes attribute values of a plurality of layout attributes. That is, the electronic device 110 may determine respective attribute values for a plurality of layout attributes of the respective reference layout 102.
Layout attributes may include process nodes (also referred to as technology nodes or process nodes) of the layout, which may have values of 28nm, 14nm, 12nm, 10nm, 7nm, 5nm, and so on. Layout attributes may also include layout types, such as types of layers of the layout, e.g., metal layer 0 (M0), M0G, M C, metal layer 1 (M1), metal layer 2 (M2), via layer 0 (V0), via layer 1 (V1), and so forth. The layout properties may also include objects to which the layout is to be supplied, e.g. different customers or different devices. The layout attributes may also include graphic information of the layout, such as information on the size, shape, distribution, etc. of the graphics in the layout. The electronic device 110 may collect layout pattern information, such as pattern size, shape, distribution, etc., of the reference layout 102. The electronic device 110 may perform feature selection and feature processing on the graphical information or other feature information. This information may also be part of the attribute information of the reference layout 102. It should be appreciated that the layout attributes may include one or more of the attributes described above, and that the layout attributes may also include any other suitable attributes. These layout attributes may have other suitable attribute values. The scope of the disclosure is not limited in this respect.
At block 230, the electronic device 110 determines a decision tree model 120 for layout splitting based on the plurality of reference split policies 104 and the respective attribute information of the plurality of reference layouts 102. The decision tree model 120 includes a plurality of attribute nodes and a plurality of policy nodes. Each attribute node corresponds to an attribute value of one of the plurality of layout attributes. Each policy node corresponds to one of a plurality of reference split policies.
In some embodiments, the decision tree model 120 may include multiple levels of attribute nodes. Each hierarchy may correspond to a layout attribute. Electronic device 110 may generate these attribute nodes layer by layer. The attribute nodes of the highest level (also referred to as the first level) are also referred to as the root or parent nodes of the decision tree model 120. For example, the electronic device 110 may arbitrarily select the first layout attribute from the plurality of layout attributes as the layout attribute of the first hierarchy. Alternatively, in some embodiments, the electronic device 110 may select the first layout attribute from a set of layout attributes to be partitioned based on respective information gain metrics of the set of layout attributes. The information gain metric for a layout attribute may be used to measure the degree of information complexity reduction caused by the layout attribute.
In particular, the information gain metric for a layout attribute may be determined based on a ratio between the information gain value for the layout attribute and the respective eigenvalues of a set of layout attributes. The information gain value of the layout attribute represents the degree of information complexity reduction caused by the layout attribute. The respective eigenvalues of a set of layout attributes are proportional to the number of attribute values of the corresponding layout attribute.
As an example, the information gain value of the layout attribute may be determined using information entropy. For example, equation (1) may be employed to determine the information entropy of the plurality of reference layouts 102:
Where D represents a set of multiple reference layouts 102, ent (D) represents the information entropy of set D, p k represents the duty cycle of the kth class of samples in set D, and y represents the number of sample types. For example, the samples may be classified according to various layout attributes. The information entropy may represent the degree of confusion (i.e., uncertainty) for a sample set.
Assuming that the layout attribute a has V possible values a 1,a2,......,aV, if a is used to divide the set D, V branch nodes (i.e., attribute nodes) are generated, where the V-th branch node includes all samples of D that have a value a v on the layout attribute a, denoted as D v. The information entropy of D v can be calculated according to equation (1). The weight may be given to different branch nodes in consideration of the difference in the number of samples included in the branch nodesThe greater the number of samples, i.e. the greater the number of samples with the attribute value, the greater the impact of the branching node.
According to the determined information entropy, the information gain value of the layout attribute can be determined by adopting the formula (2):
In which Gain (D, a) represents the information Gain value of the layout attribute a. Ent (D) may represent the degree of confusion for set D, The degree of confusion of the set D after the division using the layout attribute a can be reflected. That is, the information gain value of the layout attribute a may represent a decrease in the degree of confusion of the set D by the division of the layout attribute a, that is, an increased amount of information, and thus is referred to as an information gain value. In general, the larger the information gain, the greater the purity improvement obtained by dividing using the layout property a.
In some embodiments, the information gain value itself may be employed as the information gain metric to select the first layout attribute from a set of layout attributes. For example, the layout attribute with the largest information gain value may be selected as the first layout attribute corresponding to the highest first level.
Alternatively, in some embodiments, the ratio between the information gain value and the natural value of the layout attribute may be used as the information gain metric to select the first layout attribute. For example, the eigenvalues of the layout properties may be calculated using equation (3):
Where IV (a) represents the eigenvalue of the layout attribute a. The larger the number of possible values of the layout property a (i.e., the larger V), the larger the value of IV (a) is typically.
Using the eigenvalue IV (a) and the information Gain value Gain (D, a), the information Gain metric for layout attribute a can be determined using equation (4):
Wherein Gain-ratio (D, a) represents the information Gain metric of the layout attribute a. Electronic device 110 may select the first layout attribute based on respective information gain metrics of a set of layout attributes. For example, the layout attribute with the largest information gain metric may be selected as the first layout attribute of the highest hierarchy. By selecting the layout attribute by using the information gain metric determined by the formula (4), the influence of the number of samples corresponding to the layout attribute on the selection result can be reduced. The method can avoid the influence caused by unbalanced number of the collected attribute samples of each layout of the reference layout.
Several examples of determining a first layout attribute of a first hierarchy based on an information gain metric are described above. It should be understood that the above list of formulas (1) to (4) is merely exemplary and is not intended to be limiting in any way. Any suitable calculation or selection method may be employed to select nodes of the various levels of the decision tree model 120.
Taking the first layout attribute as a layout type, e.g., a layer type as an example, the electronic device 110 may determine at least one attribute node of the first hierarchy based on the layer type. For example, electronic device 110 may generate attribute nodes corresponding to types of M0 type, M0C type, V0 type, and the like. These attributes are associated with the reference layout 102 corresponding to the M0 type, M0C type, V0 type, respectively.
FIG. 3 shows a schematic diagram of an example decision tree model 120, according to an embodiment of the disclosure. For purposes of illustration, in the example embodiment of FIG. 3, a layout type or layer type will be described as an example of a first layout attribute. As shown in FIG. 3, according to the first layout attribute of layer type 310, attribute nodes corresponding to different layer types may be generated, such as attribute node 312 corresponding to M0 type, attribute node 314 corresponding to M0C type, attribute node 316 corresponding to V0 type, and so forth.
After constructing a certain attribute node (e.g., a first attribute node of a first hierarchy), electronic device 110 may iteratively perform operations to generate at least one node of a next hierarchy of first attribute nodes in decision tree model 120. Next, a process of iteratively generating at least one node of a next hierarchy of the first attribute node will be described in detail.
In some embodiments, the electronic device 110 may select a target layout attribute from a set of layout attributes based on respective information gain metrics of the set of layout attributes to be partitioned. The set of layout attributes to be partitioned is at least a portion of the plurality of layout attributes and does not include the layout attribute corresponding to the first attribute node. For example, where an attribute node of a layout attribute, layer type 310, as enumerated above, has been constructed, a set of layout attributes may include layout attributes other than layer types. That is, a set of layout attributes may include the process node of the layout and the object to which the layout is to be supplied.
It is assumed that the target layout attribute is a process node based on the information gain metric of the process node of the layout and the information gain metric of the object to which the layout is to be supplied. Next, the electronic device 110 may generate at least one second attribute node in the decision tree model 120 corresponding to the at least one attribute value based on the at least one attribute value possessed by the target layout attribute. The at least one second attribute node is the next level of the first attribute node. For example, the next hierarchy of attribute nodes 312 may include attribute nodes 322, 324, and 326. These attribute nodes 322, 324, and 326 may each correspond to different process node values, such as 14nm, 7nm, 10nm, etc. The electronic device 110 may remove the target layout attribute from the set of layout attributes to update the set of layout attributes to be partitioned.
Similarly, the information gain value of the layout attribute calculated by the expression (1) and the expression (2) may be employed to select the target layout attribute. As another example, the information gain metrics calculated by equations (1) through (4) may also be employed to select the target layout attribute. And are not described in detail herein. By iteratively performing the above process, individual attribute nodes of the decision tree model 120 can be constructed.
A plurality of attribute nodes of the decision tree model 120 corresponding to attribute values of different layout attributes are constructed above by calculating information gain metrics. It should be appreciated that any other suitable existing decision tree construction method or decision tree construction method that will occur in the future may be employed to construct the various attribute nodes of the decision tree model 120. Embodiments of the disclosure are not limited in this respect.
In some embodiments, electronic device 110 may determine whether the constructed attribute node may be partitioned. For example, an attribute node cannot be partitioned if the reference split policies 104 corresponding to each reference layout 102 associated with that attribute node are the same. As another example, if the attribute values of the layout attributes of each reference layout associated with a certain attribute node that have not been partitioned are the same, the attribute node cannot be partitioned. For another example, if a reference layout associated with a certain attribute node does not exist in the plurality of reference layouts, the attribute node cannot be divided.
In some embodiments, if electronic device 110 determines that a certain attribute node may continue to be partitioned, then the construction of the next level of attribute nodes may continue in the manner described above. For example, with respect to attribute node 322, electronic device 110 may determine that attribute node 322 may continue to be partitioned, and may construct the next level of attribute nodes in a similar manner. For example, attribute node 332 and attribute node 334 for the layout attribute, which is the object to which the layout is supplied. Conversely, if a certain attribute node, such as a third attribute node, cannot be partitioned, electronic device 110 may generate a policy node for the next level of the third attribute node. As shown in fig. 3, the attribute node 324 cannot be partitioned, and the electronic device 110 may construct a policy node 346 of a next level of the attribute node 324. Similarly, policy node 342 for the next level of attribute node 332, policy node 344 for the next level of attribute node 334, and so on may be constructed. Policy nodes may also be referred to herein as leaf nodes, which no longer have nodes of the next hierarchy.
Next, a process of constructing the policy node will be described in detail. In some embodiments, the electronic device 110 may determine a path of the third attribute node to a root node in the decision tree model 120. The root node does not have nodes of the previous level. For example, taking the first hierarchy listed above as an attribute node corresponding to a certain layer type, the attribute node may be the root node of the third attribute node. Each attribute node of the determined path defines an attribute value for at least one of the plurality of layout attributes. In the example of fig. 3, a path of attribute node 324 to its root node, i.e., attribute node 312, may be determined. The path includes an attribute value (i.e., M0 layer) corresponding to the layout attribute of attribute node 312 and an attribute value (i.e., 7nm process node) corresponding to the layout attribute of attribute node 324.
Electronic device 110 may determine a first reference split policy of the plurality of reference split policies 104 that corresponds to the path. That is, a reference split policy 104 of the plurality of reference split policies 104 corresponding to the reference layout 102 having M0 layers and 7nm process nodes may be determined to be the first reference split policy corresponding to the path. The electronic device 110 may generate a reference policy node of a next level of third attribute nodes, the reference policy node indicating that the first reference split policy is used for a layout having attribute values of the at least one layout attribute. In this way, rules definitions can be established for rules forming the optimal split path based on the optimal split path analysis as policy nodes for the decision tree model 120.
In the above manner, the various nodes of the decision tree model 120 may be constructed. In some embodiments, the decision tree model 120 may be partitioned into multiple decision trees (also referred to as subtrees), namely subtrees 350, 360, and 370, according to a highest hierarchy. That is, for a first layout attribute, such as a layer type, a corresponding subtree may be separately constructed for predicting a target split policy of a target layout of the layer type. These subtrees constitute the decision tree model 120. Thus, the decision tree model 120 is also referred to herein as a decision tree forest or decision forest.
Alternatively, in some embodiments, for an attribute value of a certain layout attribute, a subtree corresponding to the attribute value may be constructed as a decision tree model for a layout having the attribute value. For example, a decision tree model may be built for an attribute value having a process node of 7 nm. That is, reference layouts with 7nm process nodes and some other layout attributes (e.g., layer type, object supplied, etc.) may be collected. By using the reference layout aiming at 7nm and the corresponding reference splitting strategy, a decision tree model aiming at the layout of 7nm can be constructed by adopting the similar method. That is, different decision tree models can be respectively constructed for layouts with attribute values of a certain class of layout attributes to respectively predict splitting strategies.
It should be understood that the decision tree model 120 illustrated in FIG. 3 is merely illustrative and not limiting. The number of nodes, node connection relationships, etc. in fig. 3 may be any other number of nodes and have any other suitable connection relationships.
Several examples of constructing decision tree model 120 are described above in connection with fig. 2 and 3. It should be understood that the order of the blocks shown in fig. 2 is exemplary and that the order of the individual blocks of fig. 2 may be adjusted. For example, the order of blocks 210 and 220 may be interchanged. As another example, blocks 210 and 220 may be performed in parallel. Embodiments of the present disclosure are not limited herein.
In some embodiments, the electronic device 110 may also evaluate and adjust the constructed decision tree model 120. As an example, the electronic device 110 may determine a target split policy for the test layout using the decision tree model 120 based on attribute values of a plurality of layout attributes of the test layout. The test layout may be one or more test layouts in a pre-collected test set. The test set also stores a reference splitting policy corresponding to the test layout. And splitting the test layout by using a reference splitting strategy to obtain a test result meeting the preset condition.
The electronic device 110 may determine a performance index of the decision tree model 120 based on a comparison between the determined target split policy and a reference split policy for the test layout. The electronic device 110 may utilize a set of test layouts to test the performance of the decision tree model 120. For example, the performance of decision tree model 120 may be evaluated from employing, as performance metrics, appropriate metrics such as accuracy, precision, recall, F1 value (F1 value is a harmonic mean of precision and recall), and the like.
In some embodiments, if the performance index of the decision tree model 120 is below a threshold, the electronic device 110 may update the decision tree model 120 by adjusting the structure of the decision tree model 120. The threshold value may be any suitable value that is preset. For example, electronic device 110 may delete at least one attribute node on a branch of decision tree model 120. As another example, electronic device 110 can adjust a branch of decision tree model 120 that includes at least one attribute node and at least one policy node thereon. For example, the branch may be deleted, or a new attribute node may be added to the branch, and so on. Branches or nodes to be adjusted or deleted may be selected based on the test results. For example, if the resulting target split policy does not provide good split results for multiple test layouts having a certain attribute value for a certain layout attribute, then the attribute node for that attribute value for that layout attribute may be deleted.
In some embodiments, pruning operations may also be performed on the constructed decision tree model 120 in order to prevent overfitting. I.e. to delete some unnecessary nodes of the decision tree model 120 or to adjust branches of the nodes, etc.
Through the above model evaluation and adjustment, model pruning and other operations, it can be ensured that the constructed decision tree model 120 can provide a more accurate target splitting strategy for various layouts. Thus, the subsequent layout splitting and the multiple exposure can be ensured.
As submitted above, in some embodiments, the constructed decision tree model 120 may be used to predict a target split strategy of a target layout. A flowchart of a method 400 of layout splitting processing using the decision tree model 120 according to some embodiments of the present disclosure is described below with reference to fig. 4. The method 400 may be performed by the electronic device 110. It should be understood that method 400 may also include additional blocks not shown and/or may omit certain block(s) shown, the scope of the present disclosure not being limited in this respect.
At block 410, the electronic device 110 obtains the decision tree model 120. The decision tree model 120 includes a plurality of attribute nodes and a plurality of policy nodes. Each attribute node corresponds to an attribute value of one of the plurality of layout attributes. Each policy node corresponds to one of a plurality of reference split policies. For example, the decision tree model 120 may be as shown in FIG. 3. The attribute nodes and policy nodes of the decision tree model 120 have been described above in connection with fig. 2 and 3, and will not be described in detail herein.
Decision tree model 120 may be constructed by electronic device 110 using method 200 or other suitable method. Alternatively, the decision tree model 120 may be received by the electronic device 110 from another device, which may employ the method 200 or other methods to construct the decision tree model 120. Specifically, the electronic device 110 or another device may determine a plurality of reference split policies 104 corresponding to the plurality of reference layouts 102, respectively. The splitting quality of each reference layout 102, which is split by the corresponding reference splitting policy 104, satisfies a predetermined condition. The electronic device 110 or another device may determine the decision tree model 120 based on the attribute values of the plurality of layout attributes of the plurality of reference split policies 104 and the plurality of reference layouts 102.
At block 420, the electronic device 110 determines a target split policy 144 for the target layout 142 using the decision tree model 120 based on the target attribute values for the plurality of layout attributes that the target layout 142 has.
In some embodiments, the electronic device 110 may determine a target path corresponding to target attribute values of a plurality of layout attributes and a target policy node to which the target path points from the decision tree model 120. The electronic device 110 may determine the reference split policy indicated by the target policy node as the target split policy 144. In particular, the electronic device 110 may determine a target path corresponding to target attribute values of a plurality of layout attributes and a target policy node to which the target path points from the decision tree model 120. For example, assuming that attribute node 312 corresponds to M0 level, attribute node 322 corresponds to 14nm, and attribute node 332 corresponds to object A in FIG. 3, for M0 level, 14nm process node, target layout 142 to be supplied to object A, a target split policy indicated by policy node 342 may be employed. As an example, the policy may indicate that graphics of the elongated shapes in the target layout 142 are to be preferentially split.
In some embodiments, the electronic device 110 may split the target layout 142 based on the target split policy 144. By employing the decision tree model 120 constructed with the reference layout and the reference splitting policy, the splitting policy of the layout having attribute values of various layout attributes can be predicted. The decision tree model 120 can adapt to various layouts with different attributes or types, and can obtain more effective splitting results for various layouts. For different input layouts, different splitting schemes are selected according to the prediction results of the decision tree model 120, so that a better splitting result can be obtained.
In some embodiments, the electronic device 110 may determine the performance metrics of the decision tree model 120 based on the splitting results of splitting the target layout 142. For example, the performance index of the decision tree model 120 may be determined based on the time spent splitting, the graph duty ratio of the different layout parts split, etc. If the split takes longer, the performance index is lower. If the pattern occupation ratio difference of the different split layout parts is large, the performance index is low. If the performance index is determined to be below the threshold, the electronic device 110 may update the decision tree model 120 by adjusting the structure of the decision tree model 120. For example, at least one attribute node on a branch of the decision tree model 120 may be deleted. As another example, a branch of the decision tree model 120 may be adapted, the branch including at least one attribute node and at least one policy node thereon.
By adjusting the decision tree model 120 using split result feedback, the performance of the decision tree model 120 can be continuously improved, so that the decision tree model is continuously adapted to more types of layouts with different attributes. With the continued investment of such a decision tree model 120, the likelihood of predicting an optimal split strategy increases gradually.
FIG. 5 illustrates a flow chart of a process 500 for determining a target split policy 144 for a target layout 142 using a decision tree model 120 and updating the decision tree model 120 in accordance with some embodiments of the present disclosure. As shown in FIG. 5, at block 510, the electronic device 110 may pre-process the target layout 142 (also referred to as a new sample). For example, the electronic device 110 may obtain target attribute values for a plurality of layout attributes of the target layout 142. These layout attributes may be the same as the plurality of layout attributes employed to construct decision tree model 120. As another example, the electronic device 110 may perform other preprocessing on the target layout 142.
At block 520, the electronic device 110 may determine a target split policy 144 for the target layout 142 using the constructed (also referred to as trained) decision tree model 120 based on the target attribute values of the plurality of layout attributes that the target layout 142 has. That is, the decision tree model 120 may predict the splitting policy of the target layout 142. In particular, the electronic device 110 may determine a target path corresponding to target attribute values of a plurality of layout attributes and a target policy node to which the target path points from the decision tree model 120. For example, assuming that attribute node 312 corresponds to M0 level, attribute node 322 corresponds to 14nm, and attribute node 332 corresponds to object A in FIG. 3, for M0 level, 14nm process node, target layout 142 to be supplied to object A, a target split policy indicated by policy node 342 may be employed. For example, the policy may indicate that graphics of the elongated shapes in the target layout 142 are to be preferentially split. At block 530, the electronic device 110 may split the target layout 142 based on the target split policy 144.
By employing the decision tree model 120 constructed with the reference layout and the reference splitting policy, the splitting policy of the layout having attribute values of various layout attributes can be predicted. The decision tree model 120 can adapt to various layouts with different attributes or types, and can obtain more effective splitting results for various layouts. For different input layouts, different splitting schemes are selected according to the prediction results of the decision tree model 120, so that a better splitting result can be obtained.
In some embodiments, the splitting result obtained by splitting the target layout 142 according to the target splitting policy 144 may be fed back to the electronic device 110. The electronic device 110 may further optimize or adjust the decision tree model based on the feedback. Specifically, as shown in fig. 5, at block 540, the electronic device 110 may determine a performance index of the decision tree model 120 based on the splitting result of splitting the target layout 142 according to the target splitting policy 144. For example, the performance index of the decision tree model 120 may be determined based on the time spent splitting, the graph duty ratio of the different layout parts split, etc. If the split takes longer, the performance index is lower. If the pattern occupation ratio difference of the different split layout parts is large, the performance index is low. As another example, if the target layout 142 cannot be successfully split according to the target split policy 144, the performance index is low.
At block 550, electronic device 110 may determine whether the performance index is below a threshold. The threshold value may be any suitable value that is preset. If the performance index of the decision tree model 120 is below the threshold, the electronic device 110 may update the decision tree model 120 by adjusting the structure of the decision tree model 120 at block 560. For example, at least one attribute node on a branch of the decision tree model 120 may be deleted. As another example, a branch of the decision tree model including at least one attribute node and at least one policy node may be adjusted.
By adjusting the decision tree model 120 using split result feedback, the performance of the decision tree model 120 can be continuously improved, so that the decision tree model is continuously adapted to more types of layouts with different attributes. With the continued investment of such a decision tree model 120, the likelihood of predicting an optimal split strategy increases gradually.
It should be appreciated that the method 200, method 400, and process 500 may be used in combination. That is, the decision tree model 120 may be constructed by the electronic device 110 using the method 200. The electronic device 110 may in turn employ the decision tree model 120 to split the target layout using a method or employ the process 500 to split the target layout and update the decision tree model 120. In other embodiments, method 200 and method 400 or process 500 may be implemented by different arrangements. For example, the decision tree model 120 may be constructed by the electronic device 110 using the method 200. The electronic device 110 may transmit the constructed decision tree model 120 to other devices, such as layout processing devices. The layout processing device may utilize the received decision tree model 120 to predict a split strategy for the target layout.
Fig. 6 illustrates a block diagram of a server or electronic device 600 in which one or more embodiments of the disclosure may be implemented. The electronic device 600 may be used, for example, to implement the electronic device 110 shown in fig. 1. It should be understood that the electronic device 600 illustrated in fig. 6 is merely exemplary and should not be construed as limiting the functionality and scope of the embodiments described herein.
As shown in fig. 6, the electronic device 600 is in the form of a general-purpose electronic device. The components of electronic device 600 may include, but are not limited to, one or more processors 610 or processing units, memory 620, storage 630, one or more communication units 640, one or more input devices 650, and one or more output devices 660. The processing unit may be a real or virtual processor and is capable of performing various processes according to programs stored in the memory 620. In a multiprocessor system, multiple processing units execute computer-executable instructions in parallel to increase the parallel processing capabilities of electronic device 600.
The electronic device 600 typically includes a number of computer storage media. Such a medium may be any available medium that is accessible by electronic device 600, including, but not limited to, volatile and non-volatile media, removable and non-removable media. The memory 620 may be volatile memory (e.g., registers, cache, random Access Memory (RAM)), non-volatile memory (e.g., read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory), or some combination thereof. Storage device 630 may be a removable or non-removable media and may include machine-readable media such as flash drives, magnetic disks, or any other media that may be capable of storing information and/or data (e.g., training data for training) and may be accessed within electronic device 600.
The electronic device 600 may further include additional removable/non-removable, volatile/nonvolatile storage media. Although not shown in fig. 6, a magnetic disk drive for reading from or writing to a removable, nonvolatile magnetic disk (e.g., a "floppy disk") and an optical disk drive for reading from or writing to a removable, nonvolatile optical disk may be provided. In these cases, each drive may be connected to a bus (not shown) by one or more data medium interfaces. Memory 620 may include a computer program product 625 having one or more program modules configured to perform the various methods or acts of the various embodiments of the disclosure.
The communication unit 640 enables communication with other electronic devices through a communication medium. Additionally, the functionality of the components of the electronic device 600 may be implemented in a single computing cluster or in multiple computing machines capable of communicating over a communication connection. Thus, the electronic device 600 may operate in a networked environment using logical connections to one or more other servers, a network Personal Computer (PC), or another network node.
The input device 650 may be one or more input devices such as a mouse, keyboard, trackball, etc. The output device 660 may be one or more output devices such as a display, speakers, printer, etc. The electronic device 600 may also communicate with one or more external devices (not shown), such as storage devices, display devices, etc., with one or more devices that enable a user to interact with the electronic device 600, or with any device (e.g., network card, modem, etc.) that enables the electronic device 600 to communicate with one or more other electronic devices, as desired, via the communication unit 640. Such communication may be performed via an input/output (I/O) interface (not shown).
According to an exemplary implementation of the present disclosure, a computer-readable storage medium is provided, on which one or more computer instructions are stored, wherein the one or more computer instructions are executed by a processor to implement the method described above.
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable medium having the instructions stored therein includes an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various implementations of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The foregoing description of implementations of the present disclosure has been provided for illustrative purposes, is not exhaustive, and is not limited to the implementations disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various implementations described. The terminology used herein was chosen in order to best explain the principles of each implementation, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand each implementation disclosed herein.

Claims (15)

1. A layout splitting method, comprising:
Generating a plurality of attribute nodes of a decision tree model for layout splitting for a plurality of layout attributes, each attribute node corresponding to an attribute value of one of the plurality of layout attributes;
Generating a plurality of policy nodes of the decision tree model, each policy node corresponding to a reference splitting policy indicating how to split the layout into at least two layout parts, and
And determining a target splitting strategy aiming at the target layout by utilizing the decision tree model based on the target attribute values of the plurality of layout attributes of the target layout.
2. The layout splitting method of claim 1, wherein generating a plurality of attribute nodes of the decision tree model for layout splitting comprises iteratively performing, for a first attribute node that has been generated:
Selecting a target layout attribute from a group of layout attributes to be divided based on respective information gain metrics of the group of layout attributes, wherein the group of layout attributes are at least one part of the plurality of layout attributes and do not comprise first layout attributes corresponding to the first attribute nodes;
Generating at least one second attribute node corresponding to the at least one attribute value in the decision tree model based on at least one attribute value possessed by the target layout attribute, the at least one second attribute node being a next level of the first attribute node, and
And removing the first layout attribute from the group of layout attributes to update the group of layout attributes to be divided.
3. The layout splitting method according to claim 2, wherein the information gain metric of the target layout attribute is determined based on a ratio between an information gain value of the target layout attribute and an intrinsic value of each of the set of layout attributes, the information gain value of the target layout attribute representing a degree of information complexity reduction caused by the target layout attribute, the intrinsic value of each of the set of layout attributes being proportional to a number of attribute values of the corresponding layout attribute.
4. The layout splitting method of claim 2, wherein generating the plurality of policy nodes of the decision tree model comprises:
Determining that a third attribute node of the constructed attribute nodes cannot be partitioned;
Determining a path from the third attribute node to a root node in the decision tree model, the root node not having a node of a previous level, each attribute node of the path defining an attribute value of at least one of the plurality of layout attributes;
Determining a first reference splitting policy corresponding to the path from a plurality of reference splitting policies respectively corresponding to a plurality of reference layouts, the first reference layout corresponding to the first reference splitting policy of the plurality of reference layouts having attribute values of layout attributes defined by respective attribute nodes of the path, and
Generating a reference policy node of a next level to the third attribute node, the reference policy node indicating use of the first reference splitting policy for a layout having attribute values of the at least one layout attribute.
5. The layout splitting method of claim 4, wherein the third attribute node is determined to be unable to be partitioned based on at least one of:
the reference split policies corresponding to the respective reference layouts associated with the third attribute node are the same,
The attribute values of the layout attributes of the respective reference layout associated with the third attribute node that have not been divided are the same,
The reference layout associated with the third attribute node does not exist in the plurality of reference layouts.
6. The layout splitting method according to claim 4, wherein splitting quality of the first reference layout obtained by splitting the first reference layout by the corresponding first reference splitting policy satisfies a predetermined condition.
7. The layout splitting method according to claim 6, wherein the predetermined condition is indicative of at least one of:
The layout splitting time does not exceed a threshold time,
The distribution proportion of the split layout pattern is in a preset range.
8. The layout splitting method according to claim 1, wherein determining a target splitting policy for the target layout comprises:
Determining a target path corresponding to target attribute values of the plurality of layout attributes and a target policy node pointed to by the target path from the decision tree model, and
And determining the reference splitting strategy indicated by the target strategy node as the target splitting strategy.
9. The layout splitting method according to claim 1, further comprising:
splitting the target layout based on the target splitting strategy;
Determining a performance index of the decision tree model based on a splitting result of the splitting of the target layout, and
If the performance index is determined to be below a threshold, the decision tree model is updated by adjusting the structure of the decision tree model.
10. The layout splitting method according to claim 1, further comprising:
determining a target splitting strategy for the test layout by utilizing the decision tree model based on attribute values of the plurality of layout attributes of the test layout;
determining a performance index of the decision tree model based on a comparison between the target split strategy and a reference split strategy for the test layout, and
If the performance index can be below a threshold, the decision tree model is updated by adjusting the structure of the decision tree model.
11. The layout splitting method according to claim 9 or 10, wherein updating the decision tree model by adjusting the structure of the decision tree model comprises:
Deleting at least one attribute node on a branch of the decision tree model, or
And adjusting branches of the decision tree model, wherein the branches comprise at least one attribute node and at least one strategy node.
12. The layout splitting method of claim 1, wherein the plurality of layout attributes comprises at least one of:
the object to which the layout is to be supplied,
The process nodes of the layout are defined,
Layout type.
13. The layout splitting method according to claim 1, wherein the layout splitting strategy comprises at least one of:
The direction of splitting the layout is divided,
Layout splitting positions.
14. An electronic device, comprising:
at least one processing unit, and
At least one memory coupled to the at least one processing unit and storing instructions for execution by the at least one processing unit, which when executed by the at least one processing unit, cause the electronic device to perform the method of any one of claims 1 to 13.
15. A computer readable storage medium, having stored thereon a computer program, characterized in that the computer program is executable by a processor to implement the method according to any of claims 1 to 13.
CN202411317175.5A 2024-07-02 2024-07-02 Method, device and medium for layout processing Pending CN119250013A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202411317175.5A CN119250013A (en) 2024-07-02 2024-07-02 Method, device and medium for layout processing

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202410885914.4A CN118428313B (en) 2024-07-02 2024-07-02 Method, apparatus and medium for layout processing
CN202411317175.5A CN119250013A (en) 2024-07-02 2024-07-02 Method, device and medium for layout processing

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN202410885914.4A Division CN118428313B (en) 2024-07-02 2024-07-02 Method, apparatus and medium for layout processing

Publications (1)

Publication Number Publication Date
CN119250013A true CN119250013A (en) 2025-01-03

Family

ID=92307439

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202410885914.4A Active CN118428313B (en) 2024-07-02 2024-07-02 Method, apparatus and medium for layout processing
CN202411317175.5A Pending CN119250013A (en) 2024-07-02 2024-07-02 Method, device and medium for layout processing

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN202410885914.4A Active CN118428313B (en) 2024-07-02 2024-07-02 Method, apparatus and medium for layout processing

Country Status (1)

Country Link
CN (2) CN118428313B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN120235223B (en) * 2025-05-30 2025-08-19 华院计算技术(上海)股份有限公司 Method, system, equipment and medium for determining process node of continuous casting blank inclusion

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105488413A (en) * 2015-06-19 2016-04-13 哈尔滨安天科技股份有限公司 Malicious code detection method and system based on information gain
CN106407883B (en) * 2016-08-10 2019-12-27 北京工业大学 Complex form and identification method for handwritten numbers in complex form
US12045555B2 (en) * 2018-01-31 2024-07-23 Asml Netherlands B.V. Method to label substrates based on process parameters
US11003826B1 (en) * 2019-04-29 2021-05-11 Xilinx, Inc. Automated analysis and optimization of circuit designs
US10885259B2 (en) * 2019-08-30 2021-01-05 Intel Corporation Random forest model for prediction of chip layout attributes
CN117148682A (en) * 2022-05-24 2023-12-01 中芯国际集成电路制造(上海)有限公司 Layout splitting method, system, equipment and storage medium
CN117631441A (en) * 2022-08-18 2024-03-01 中芯国际集成电路制造(上海)有限公司 Mask layout splitting method, system, equipment and storage medium
KR20240030985A (en) * 2022-08-31 2024-03-07 한국과학기술원 Method and apparatus for determining refragmentation for optical proximity correction using machine learning classifier
CN115859899B (en) * 2023-02-06 2023-05-16 北京大学 Method for migrating multiple-driving-capability integrated circuit standard unit layout
CN117332745B (en) * 2023-11-22 2024-02-13 全芯智造技术有限公司 Method, apparatus and medium for generating layout

Also Published As

Publication number Publication date
CN118428313B (en) 2024-09-24
CN118428313A (en) 2024-08-02

Similar Documents

Publication Publication Date Title
JP7234370B2 (en) Generating Integrated Circuit Floorplans Using Neural Networks
US8555221B2 (en) Partitioning for hardware-accelerated functional verification
CN112257848B (en) Method for determining logic core layout, model training method, electronic device, medium
CN118428313B (en) Method, apparatus and medium for layout processing
CN118363252B (en) Method, apparatus and medium for layout processing
CN118092068B (en) Method, apparatus and medium for light source mask optimization
TWI765836B (en) A method for analog circuit sizing and apparatus
CN116432403A (en) Method, system, device and storage medium for constructing motor combination agent model
CN111401569A (en) Hyper-parameter optimization method and device and electronic equipment
KR20240013343A (en) Modeling method of neural network for simulation in semiconductor design process, simulation method in semiconductor design process using the same, and semiconductor design system performing the same
Hou Convergence of the adapted smoothed empirical measures
CN118821702A (en) Method, device and storage medium for interconnect evaluation
CN120012700A (en) A method for compensating etching deviation and related products
CN117216333B (en) Deep multi-hop query method, device, equipment and medium based on graph data optimization
WO2025035626A1 (en) Method and apparatus for determining parameter of layout quality test tool, and device and medium
CN114757153B (en) String, string set processing method, computer device and storage medium
CN117973284A (en) Circuit reliability degradation prediction method based on attention graph convolutional network
CN112699148B (en) Method, device, equipment and storage medium for refreshing cache
CN118821699B (en) Method, device and medium for optimizing layout processing model
CN115933330A (en) Hotspot detection method, device and medium
CN119808705B (en) Training method, device and computer equipment for chip design index generation model
CN119065193B (en) Method, electronic device and computer-readable storage medium for optical proximity correction
CN120012708B (en) SRAF placement method and device, storage medium and electronic equipment
US20240394453A1 (en) Global placement of circuit designs using a calibrated simple timer
Wu et al. Delay-Driven Rectilinear Steiner Tree Construction

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination