CN119227608A - A universal FPGA logic structure and its design method - Google Patents
A universal FPGA logic structure and its design method Download PDFInfo
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Abstract
The embodiment of the specification provides a generalized FPGA logic structure and a design method, wherein the generalized FPGA logic structure comprises a functional module, a data exchange module and a signal conversion module, the functional module comprises a solidification functional module and a custom functional module, whether each functional module is instantiated, a base address and an address space are set through a macro definition file, the data flow between each functional module is configured, the data exchange module is used for realizing data transmission between each functional module according to the configured data flow between each functional module, the input and the output of the data exchange module are respectively provided with a custom standard time sequence interface, and the signal conversion module is used for connecting each functional module with the data exchange module to realize signal conversion between the custom standard time sequence interface and a common interface of each functional module. The invention expands the application range of the module and can effectively cope with the continuously changing design requirements.
Description
Technical Field
The present document relates to the field of electronic design technologies, and in particular, to a generalized FPGA logic structure and a design method thereof.
Background
The FPGA is widely applied to various electronic systems with strict real-time performance, certainty and bandwidth requirements of a computing unit by the fine granularity parallelism of a lookup table and a logic gate level thereof, and is widely applied to the fields of digital signal processing, communication, video and audio signal processing, industrial control, military application, instruments and meters, high-performance computing and the like:
The FPGA has the greatest advantages of extremely fine granularity parallelism, but the extremely fine granularity parallelism system structure brings a plurality of problems for engineering design, and is mainly characterized in that the FPGA has high design threshold, the highly parallel operation mode of the FPGA has large difference with the serial thinking modes of human brains, the FPGA has high design threshold relative to most programming languages such as C language, C++, python and C#, the module universality is weak, the module level multiplexing of the FPGA is closely related to signal names and signal functions, the time sequence relationship among signals can influence the module functions, the universality among FPGA modules is greatly reduced, the comprehensive implementation time is long, the comprehensive implementation of FPGA design codes needs to be corresponding to the triggering mechanism of each basic unit, and the comprehensive implementation time of the medium-scale design is long, for example, the 7k325t comprehensive implementation time of Xilinx is more than 30 mins.
Therefore, aiming at the problems of the FPGA in engineering application, taking the development efficiency as a main aim, the research of structuring, generalizing and standardizing architecture has important engineering significance, the modern SOC design thought is consulted, a reconfigurable and generalized FPGA logic structure is provided, the customization development efficiency of the FPGA is improved, and the related requirements of the industrial control field are oriented based on the provided reconfigurable and generalized FPGA logic structure, so that the logic design, verification and related application deployment of a prototype system are completed.
Disclosure of Invention
One or more embodiments of the present disclosure provide a generalized FPGA logic structure, including a functional module, a data exchange module, and a signal conversion module;
the function modules comprise a solidification function module and a custom function module, whether each function module is instantiated, a base address and an address space are set through a macro definition file, and the data flow direction between each function module is configured;
the data exchange module is used for realizing data transmission among the function modules according to the configured data flow direction among the function modules, and the input and the output of the data exchange module adopt custom standard time sequence interfaces;
The signal conversion module is used for connecting each functional module with the data exchange module to realize signal conversion between the custom standard time sequence interface and the common interface of each functional module.
Further, the address space of each functional module is determined by a base address and an offset address.
Further, the memory corresponding to the address space of each functional module comprises a register file and a RAM, wherein the register file is positioned in the initial area of the address space, and the RAM is positioned in the address space outside the area where the register file is positioned.
Further, the data exchange module divides the output signals into enable, addr, data groups and ready groups according to the characteristics of the output signals, each group is provided with multiplexers equal to the contained output signals in number, signal interconnection of different functional modules is completed by configuring selection signals of the multiplexers, and the selection signals of the multiplexers are automatically generated after being configured by an upper computer according to requirements.
Further, the data exchange module comprises a data input exchange module and a data output exchange module, and the data input exchange module and the data output exchange module are deterministic exchange delays.
Further, the signal conversion module realizes the conversion from the following 6 kinds of common interfaces of the functional modules to the custom standard time sequence interface, and specifically includes:
register input conversion, namely a register file for writing calculation result data into an address space;
Register output conversion, which is used for reading data from a register file of an address space for self operation function;
the data transmission conversion is used for transmitting certain data of the address space of the data transmission conversion to the target module;
the function module write conversion is used for writing data into an address space of the function module or an address of a target module address space;
the function module read conversion is used for reading data from the self address space and used for self operation function;
and the target address feedback conversion is used for receiving the data sent by the target functional module and performing self operation.
Further, the input data of the custom standard time sequence interface comprises data obtained by the data sending conversion, the function module writing conversion and the function module reading conversion.
Further, the priority is set for the conversion operation from the common interface of the functional module to the custom standard time sequence interface, the conversion operation of the custom standard time sequence interface is hit according to the priority, the address and the data information in the input data of the missed conversion operation are cached, and the conversion operation is executed until the conversion operation is the highest priority.
One or more embodiments of the present disclosure provide a method for designing a generalized FPGA logic structure, including:
Whether each functional module is instantiated, the base address and the address space size are set through a macro definition file, and the data flow direction among the functional modules is configured;
The data transmission between the function modules is realized through the data exchange module according to the data flow direction between the function modules, wherein the input and output of the data exchange module adopts a self-defined standard time sequence interface;
And connecting each functional module with the data exchange module through a signal conversion module to realize signal conversion between the custom standard time sequence interface and a common interface of each functional module.
Further, when signals of the custom standard time sequence interface and the custom standard time sequence interface are converted, priority is set for conversion operation from the custom standard time sequence interface to the custom standard time sequence interface, the conversion operation of the custom standard time sequence interface is hit according to the priority, and address and data information in input data of the missed conversion operation are cached until the conversion operation is the highest priority.
The embodiment of the invention is used for solidifying and self-defining configuration of the functional modules, so that a user can flexibly select and adjust functions according to specific application requirements, multiple application scenes are supported, the complexity in the design process is reduced and the development efficiency is improved through the instantiation, the base address and the address space size of the macro definition file setting module, the data exchange module is responsible for configuring and managing the data flow direction between the functional modules, the high efficiency and accuracy of data transmission are ensured, the delay of data processing is reduced, the data between different modules are interacted through the self-defining standard time sequence interface, the signal conversion module is introduced, the seamless connection between the different functional modules and the data exchange module is allowed, the compatibility between different interfaces is supported, the application range of the modules is expanded, the method is suitable for multiple complex applications, and the continuously changing design requirements can be effectively met.
The foregoing description is only an overview of the present invention, and is intended to be implemented in accordance with the teachings of the present invention in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present invention more readily apparent.
Drawings
For a clearer description of one or more embodiments of the present description or of the solutions of the prior art, the drawings that are necessary for the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description that follow are only some of the embodiments described in the description, from which, for a person skilled in the art, other drawings can be obtained without inventive faculty.
FIG. 1 is a schematic diagram of a generalized FPGA logic structure provided in one or more embodiments of the present disclosure;
FIG. 2 is a schematic diagram illustrating a data exchange module with a generalized FPGA logic structure according to one or more embodiments of the present disclosure;
FIG. 3 is a schematic diagram illustrating a signal conversion module with a generalized FPGA logic structure according to one or more embodiments of the present disclosure;
FIG. 4 is a schematic diagram of a generalized prototype system software design of a generalized FPGA logic structure according to one or more embodiments of the present disclosure;
Fig. 5 is a flowchart of a method for designing a generalized FPGA logic structure according to one or more embodiments of the present disclosure.
Detailed Description
In order to enable a person skilled in the art to better understand the technical solutions in one or more embodiments of the present specification, the technical solutions in one or more embodiments of the present specification will be clearly and completely described below with reference to the drawings in one or more embodiments of the present specification, and it is obvious that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one or more embodiments of the present disclosure without inventive faculty, are intended to be within the scope of the present disclosure.
Example 1
According to an embodiment of the present invention, a generalized FPGA logic structure is provided, and fig. 1 is a schematic diagram of a generalized FPGA logic structure provided in one or more embodiments of the present specification, as shown in fig. 1, where the generalized FPGA logic structure according to the embodiment of the present invention specifically includes a functional module, a data exchange module, and a signal conversion module, where each functional module, for example, a pulse width modulation PWM, an analog-to-digital converter ADC, a universal asynchronous receiver/transmitter UART, and the like, implements data transmission between each other through the data exchange module after being processed by the signal conversion module.
The functional modules are mainly used for realizing relatively independent functions, and comprise curing functional modules which are verified to be finished and custom functional modules which are required by users in special demands, each functional module is allocated with a section of address space, whether each functional module is instantiated, base address and address space size can be set through a macro definition file, and data flow among the functional modules is configured.
The address space of each functional module is determined by a base address, which is the starting address of the functional module in the memory or peripheral address space, and an offset address, which is a fixed address to which the module is assigned, typically set at system initialization, which is a value relative to the base address for determining a particular register or memory location, which is typically variable within the same functional module for accessing different registers or data. The memory corresponding to the address space of each functional module comprises a register file and a RAM, wherein the register file is positioned in the initial area of the address space, and the RAM is positioned in the address space outside the area where the register file is positioned.
The data exchange module is used for realizing data transmission among the function modules according to the configured data flow direction among the function modules, and the input and the output of the data exchange module adopt custom standard time sequence interfaces, so that the data exchange module has stronger expandability.
Fig. 2 is a schematic design structure diagram of a data exchange module, as shown in fig. 2, the data exchange module divides output signals into four groups of enable, addr, data and ready according to the characteristics of the output signals, each group is provided with multiplexers equal to the number of the contained output signals, and signal interconnection of different functional modules is completed by configuring selection signals of the multiplexers, wherein the selection signals of the multiplexers are automatically generated after being configured by an upper computer according to requirements. When a specific output signal of a certain functional module needs to be interconnected with a specific input signal of another functional module, it is first determined which group of output signals (such as an enable group, an addr group, etc.) is involved, then a multiplexer corresponding to the output signals in the group is found, and then, according to the required signal source and the requirement of the target module, the selection signals of the multiplexer are configured so that the multiplexer outputs the correct input signals, thereby completing the interconnection between the two functional modules on the specific output signals. For example, if a data output signal of one functional module is to be interconnected with an input port of another functional module, it is necessary to find a multiplexer corresponding to that data output signal in the data group and then to implement the correct signal connection by configuring its selection signal.
The data exchange module comprises a data input exchange module and a data output exchange module, wherein deterministic exchange delay is formed between the data input exchange module and the output exchange module, for example, when the system clock is set to be 100MHz, the deterministic delay of 10ns is input to the data exchange module.
Each functional module is used for accessing a data exchange module to finish conversion from an original data interface of the module to a custom standard time sequence interface, the signal conversion module is used for connecting each functional module with the data exchange module to realize signal conversion between the custom standard time sequence interface and a common interface of each functional module, and the common interface comprises a register interface, a RAM interface and the like, and the problems of time sequence constraint, address hit, priority judgment during data conflict, data caching and the like are required to be considered in the conversion process.
The design scheme of the signal conversion module is shown in fig. 3, the signal conversion module realizes the conversion from the common interface of each functional module to the custom standard time sequence interface, the cleaning of the input and output data of the functional module is completed, and the judgment of the data conflict priority and the data caching mechanism are realized. Specifically, the signal conversion module may implement conversion from the following 6 common interfaces to a custom standard timing interface, including:
register input conversion, namely a register file for writing calculation result data into an address space;
Register output conversion, which is used for reading data from a register file of an address space for self operation function;
the data transmission conversion is used for transmitting certain data of the address space of the data transmission conversion to the target module;
the function module write conversion is used for writing data into an address space of the function module or an address of a target module address space;
the function module read conversion is used for reading data from the self address space and used for self operation function;
and the target address feedback conversion is used for receiving the data sent by the target functional module and performing self operation.
Setting priority for conversion operation from the common interface of the functional module to the custom standard time sequence interface, hit the conversion operation of the custom standard time sequence interface according to the priority, and cache address and data information in input data of the missed conversion operation until the conversion operation is the highest priority. Specifically, the address space of each functional module is composed of a register file and a RAM, and write collision should be avoided during the operation of the register file and the RAM, and in addition, if a single-port RAM is used, simultaneous read operation should be avoided. Therefore, in the present embodiment, in the design process, the signal conversion module virtualizes operations such as data sending, writing by the function module, and reading by the function module as input data of the custom standard timing interface, hits all operations of the custom timing interface according to priority, and caches missed addresses and data information until the operations are the highest priority.
Based on the reconfigurable generalized FPGA structural design thought, the construction work of a prototype system is developed to verify the feasibility of the reconfigurable generalized FPGA structure, and the method is oriented to part of design requirements (digital power supply and motor drive control requirements are mainly analyzed) in the field of industrial control:
The core processor adopting the hardware board comprises an FPGA and a DSP, wherein the FPGA is mainly used for realizing external AD sampling, PWM output, PWM input signal acquisition, interface driving such as Ethernet, SRIO and the like and high-real-time high-certainty algorithm realization, and the DSP is mainly used for completing a user control algorithm and communication with a superior system.
Aiming at the requirements of the industrial control field on sampling, driving control, communication and the like, the proposed reconfigurable generalized FPGA logic structure is adopted to develop prototype system design work, as shown in fig. 4, generalized prototype system software mainly comprises three parts of an FPGA, a DSP and an upper computer, wherein the FPGA adopts the reconfigurable generalized structure to design, the DSP part is a driving library for the FPGA design, the application program is convenient to call, and the upper computer generates configuration parameters of the FPGA and generates corresponding DSP library functions according to each program requirement.
The generalized prototype system software contained the functional modules shown in table 1:
TABLE 1
The software system is deployed and applied to a DSP+FPGA controller and is applied to a digital power project.
Example 2
According to an embodiment of the present invention, a method for designing a logic structure of a generalized FPGA is provided, and fig. 5 is a flowchart of a method for designing a logic structure of a generalized FPGA provided in one or more embodiments of the present invention, where the method for designing a logic structure of a generalized FPGA according to an embodiment of the present invention specifically includes:
S1, setting whether each functional module is instantiated, a base address and an address space size through a macro definition file, and configuring a data flow direction among the functional modules, wherein the functional modules comprise a solidification functional module and a custom functional module;
S2, realizing data transmission among the function modules according to the configured data flow direction among the function modules through a data exchange module, wherein the input and output of the data exchange module adopt custom standard time sequence interfaces;
S3, connecting each functional module with the data exchange module through a signal conversion module to realize signal conversion between the custom standard time sequence interface and a common interface of each functional module.
Further, when signals of the custom standard time sequence interface and the custom standard time sequence interface are converted, priority is set for conversion operation from the custom standard time sequence interface to the custom standard time sequence interface, the conversion operation of the custom standard time sequence interface is hit according to the priority, and address and data information in input data of the missed conversion operation are cached until the conversion operation is the highest priority.
The embodiment of the present invention corresponds to the embodiment 1, and specific operations may be understood with reference to the description of embodiment 1, which is not repeated herein.
The invention has the following beneficial effects:
The embodiment of the invention is used for solidifying and self-defining configuration of the functional modules, so that a user can flexibly select and adjust functions according to specific application requirements, multiple application scenes are supported, the complexity in the design process is reduced and the development efficiency is improved through the instantiation, the base address and the address space size of the macro definition file setting module, the data exchange module is responsible for configuring and managing the data flow direction between the functional modules, the high efficiency and accuracy of data transmission are ensured, the delay of data processing is reduced, the data between different modules are interacted through the self-defining standard time sequence interface, the signal conversion module is introduced, the seamless connection between the different functional modules and the data exchange module is allowed, the compatibility between different interfaces is supported, the application range of the modules is expanded, the method is suitable for multiple complex applications, and the continuously changing design requirements can be effectively met.
It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.
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