CN119212396A - Magnetic random access memory, forming method and working method thereof - Google Patents
Magnetic random access memory, forming method and working method thereof Download PDFInfo
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- CN119212396A CN119212396A CN202310774312.7A CN202310774312A CN119212396A CN 119212396 A CN119212396 A CN 119212396A CN 202310774312 A CN202310774312 A CN 202310774312A CN 119212396 A CN119212396 A CN 119212396A
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- 230000005291 magnetic effect Effects 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims description 25
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- 239000000758 substrate Substances 0.000 claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 19
- 239000003302 ferromagnetic material Substances 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- ZDZZPLGHBXACDA-UHFFFAOYSA-N [B].[Fe].[Co] Chemical compound [B].[Fe].[Co] ZDZZPLGHBXACDA-UHFFFAOYSA-N 0.000 claims description 6
- 229910017052 cobalt Inorganic materials 0.000 claims description 6
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- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 6
- OQCGPOBCYAOYSD-UHFFFAOYSA-N cobalt palladium Chemical compound [Co].[Co].[Co].[Pd].[Pd] OQCGPOBCYAOYSD-UHFFFAOYSA-N 0.000 claims description 6
- GUBSQCSIIDQXLB-UHFFFAOYSA-N cobalt platinum Chemical compound [Co].[Pt].[Pt].[Pt] GUBSQCSIIDQXLB-UHFFFAOYSA-N 0.000 claims description 6
- OBACEDMBGYVZMP-UHFFFAOYSA-N iron platinum Chemical compound [Fe].[Fe].[Pt] OBACEDMBGYVZMP-UHFFFAOYSA-N 0.000 claims description 6
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims description 6
- PCLURTMBFDTLSK-UHFFFAOYSA-N nickel platinum Chemical compound [Ni].[Pt] PCLURTMBFDTLSK-UHFFFAOYSA-N 0.000 claims description 6
- HVFOPASORMIBOE-UHFFFAOYSA-N tellanylidenechromium Chemical compound [Te]=[Cr] HVFOPASORMIBOE-UHFFFAOYSA-N 0.000 claims description 6
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- 150000004767 nitrides Chemical class 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 claims description 3
- 239000000395 magnesium oxide Substances 0.000 claims description 3
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
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- 238000005516 engineering process Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
- H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
- H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type
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Abstract
The magnetic random access memory comprises a substrate, a first electrode layer positioned on the substrate, a plurality of memory units positioned on the first electrode layer, a barrier layer positioned on the free layer, a pinning layer positioned on the barrier layer, and second electrode layers positioned on the memory units, wherein the thickness of the transmission layer of each memory unit is different, and the second electrode layers are electrically connected with the pinning layer. The memory density of the magnetic random access memory is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a magnetic random access memory, a method for forming the same, and a method for operating the same.
Background
At present, in the field of chip industry, charge-based SRAM and DRAM memory cells are widely used. The gradual reduction of these devices comes at the cost of increased standby power consumption. An effective way to address this challenge is to develop nonvolatile memory that is fast enough. In addition to the study of the charge properties of electrons, the spin properties of electrons have also been studied and applied in the design of logic devices. Spintronics devices based on electron spin are attracting attention from chip manufacturers.
Existing Spin-based Spin electronics include Spin transfer torque magnetoresistive random access memory (Spin-transfer torque magnetoresistive random access memory, STT-MRAM) and Spin orbit torque magnetoresistive random access memory (Spin-orbit torque magnetoresistive random access memory, SOT-MRAM). Spin transfer torque magnetoresistive random access memory is a promising emerging non-volatile memory technology, but large write currents through Magnetic Tunnel Junctions (MTJs) can limit reliability. The read-write path of the spin orbit torque magnetic resistance random access memory with three ends can be separated, and the reliability of the device is improved.
The performance of the existing spin-orbit torque magnetoresistive random access memory is still to be improved.
Disclosure of Invention
The invention solves the technical problem of providing a magnetic random access memory, a forming method and a working method thereof so as to improve the performance of a spin orbit torque magnetic resistance random access memory.
In order to solve the technical problems, the technical scheme of the invention provides a magnetic random access memory, which comprises a substrate, a first electrode layer positioned on the substrate, a plurality of memory units positioned on the first electrode layer, a transmission layer, a free layer positioned on the transmission layer, a barrier layer positioned on the free layer, a pinning layer positioned on the barrier layer, wherein the thickness of the transmission layer of each memory unit is different, and a second electrode layer positioned on the memory units and electrically connected with the pinning layer.
Optionally, the spin-orbit coupling effect of the transmissive layer is less than the spin-orbit coupling effect of the first electrode layer.
Optionally, the material of the transmissive layer comprises a metal or a metal nitride, the metal comprising copper or aluminum, the metal nitride comprising titanium nitride.
Optionally, the material of the first electrode layer includes a metal, and the metal includes tungsten.
Optionally, the thickness of the transmissive layer ranges from 0 to 10 nanometers.
Optionally, the thickness of the transmission layer of each storage unit is changed in a gradient manner, and the absolute value of the difference value between the transmission layers of two adjacent gradients is in the range of 0.2-1 nm.
Optionally, the number of the storage units ranges from 1 to 50.
Optionally, the material of the barrier layer includes magnesium oxide.
Optionally, the material of the free layer comprises a ferromagnetic material, wherein the ferromagnetic material comprises cobalt-iron-boron, cobalt, iron-germanium-tellurium, cobalt-platinum, cobalt-palladium, nickel-platinum, nickel-palladium, chromium telluride or iron-platinum.
Optionally, the material of the pinning layer comprises a ferromagnetic material, wherein the ferromagnetic material comprises cobalt-iron-boron, cobalt, iron-germanium-tellurium, cobalt-platinum, cobalt-palladium, nickel-platinum, nickel-palladium, chromium telluride or iron-platinum.
Optionally, the material of the second electrode layer includes a metal, and the metal includes copper.
The substrate comprises a base, a first word line grating structure and a second word line grating structure which are arranged on the base, a first doping area and a second doping area which are arranged in the base at two sides of the first word line grating structure, a third doping area and a fourth doping area which are arranged in the base at two sides of the second word line grating structure, a first bit line which is arranged on the first doping area, a first conductive structure which is arranged on the second doping area, a second conductive structure which is arranged on the third doping area, a second conductive structure which is arranged on the second conductive structure and is electrically connected with the second conductive structure, a second bit line which is arranged on the fourth doping area, and a medium structure which is arranged on the base, wherein the first word line grating structure, the second word line grating structure, the first bit line, the first conductive structure, the second conductive structure and the second bit line are arranged in the medium structure.
Correspondingly, the technical scheme of the invention also provides a forming method of the magnetic random access memory, which comprises the steps of providing a substrate, forming a first electrode layer on the substrate, forming a plurality of memory units on the first electrode layer, wherein each memory unit comprises a transmission layer, a free layer positioned on the transmission layer, a barrier layer positioned on the free layer, a pinning layer positioned on the barrier layer, the thickness of the transmission layer of each memory unit is different, and forming a second electrode layer on the memory units, and the second electrode layer is electrically connected with the pinning layer.
Optionally, the thickness of the transmission layer of each storage unit is changed in a gradient manner, and the absolute value of the difference value between the transmission layers of two adjacent gradients is in the range of 0.2-1 nm.
Optionally, the number of the storage units ranges from 1 to 50.
The substrate comprises a base, a first word line grating structure and a second word line grating structure which are arranged on the base, a first doping area and a second doping area which are arranged in the base at two sides of the first word line grating structure, a third doping area and a fourth doping area which are arranged in the base at two sides of the second word line grating structure, a first bit line which is arranged on the first doping area, a first conductive structure which is arranged on the second doping area, a second conductive structure which is arranged on the third doping area, a second conductive structure which is arranged on the second conductive structure and is electrically connected with the second conductive structure, a second bit line which is arranged on the fourth doping area, and a medium structure which is arranged on the base, wherein the first word line grating structure, the second word line grating structure, the first bit line, the first conductive structure, the second conductive structure and the second bit line are arranged in the medium structure.
Correspondingly, the technical scheme of the invention provides a working method of the magnetic random access memory, which comprises the steps of providing the magnetic random access memory, wherein the magnetic random access memory comprises a substrate, a first electrode layer arranged on the substrate, a plurality of memory units arranged on the first electrode layer, a transmission layer, a free layer arranged on the transmission layer, a barrier layer arranged on the free layer and a pinning layer arranged on the barrier layer, wherein the transmission layers of the memory units are different in thickness, a second electrode layer arranged on the memory units and electrically connected with the pinning layer, applying first currents with different magnitudes to the first electrode layer, performing writing operation, and applying second currents to the second electrode layer, and performing reading operation.
Optionally, the second current is less than the first current.
The substrate comprises a base, a first word line grating structure and a second word line grating structure which are arranged on the base, a first doping area and a second doping area which are arranged in the base at two sides of the first word line grating structure, a third doping area and a fourth doping area which are arranged in the base at two sides of the second word line grating structure, a first bit line which is arranged on the first doping area, a first conductive structure which is arranged on the second doping area, a second conductive structure which is arranged on the third doping area, a second conductive structure which is arranged on the second conductive structure and is electrically connected with the second conductive structure, a second bit line which is arranged on the fourth doping area, and a medium structure which is arranged on the base, wherein the first word line grating structure, the second word line grating structure, the first bit line, the first conductive structure, the second conductive structure and the second bit line are arranged in the medium structure.
Optionally, applying the first currents of different magnitudes to the first electrode layer for writing operations includes applying a voltage to the first word line gate structure to turn on the transistor and applying the first currents of different magnitudes to the first electrode layer through the first bit line.
Optionally, applying a second current to the second electrode layer for a read operation includes applying a voltage to the second word line gate structure to turn on the transistor and applying a second current to the second electrode layer through the second bit line.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
According to the technical scheme, the plurality of memory cells are formed on the first electrode layer, and the thickness of the transmission layer of each memory cell is different. The transmission layers can adjust critical current density of magnetic moment inversion of the free layer in the memory cells, and the thickness of the transmission layers of the memory cells is different, so that the critical current density of magnetic moment inversion of the free layer of each memory cell is different, currents with different magnitudes are written into the magnetic random access memory, the free layers of the memory cells in the magnetic random access memory can be inverted, multi-stage resistance reading can be performed, multi-stage storage is realized, and storage density is improved.
Further, the thickness of the transmission layer of each memory cell is changed in a gradient manner, and the absolute value of the difference value between the transmission layers of two adjacent gradients is in the range of 0.2-1 nm. The magnitude of critical current density for magnetic moment inversion of the free layer is also uniformly and linearly increased, multi-stage resistance reading can be performed, multi-stage storage is realized, and storage density is improved.
Further, the plurality of memory cells are located on the first electrode layer, the first electrode layer is electrically connected with the second doped region on one side of the first word line grating structure, the second electrode layer is electrically connected with the third doped region on one side of the second word line grating structure, namely, the reading and writing of the plurality of memory cells can be completed only by adopting two transistors, and the area of the magnetic random access memory is saved.
Drawings
FIGS. 1 and 2 are schematic diagrams of the structure of a MRAM in accordance with an embodiment of the present invention;
FIG. 3 is a flow chart of a method of operating a MRAM in accordance with an embodiment of the invention.
Detailed Description
As described in the background, the performance of the existing spin-orbit torque magnetoresistive random access memory is still to be improved.
Specifically, the challenges of the current spin-orbit torque magnetoresistive random access memory are mainly related to the memory capacity and the density, each memory cell needs two access transistors, a plurality of memory cells need to be accessed into a plurality of transistors, a certain area is occupied, the density of the memory cells cannot be further improved, and the memory capacity cannot be further improved.
In order to solve the above problems, the technical scheme of the invention provides a magnetic random access memory, a forming method and a working method thereof, wherein a plurality of memory cells are formed on a first electrode layer, and the thickness of a transmission layer of each memory cell is different. The transmission layers can adjust critical current density of magnetic moment inversion of the free layer in the memory cells, and the thickness of the transmission layers of the memory cells is different, so that the critical current density of magnetic moment inversion of the free layer of each memory cell is different, currents with different magnitudes are written into the magnetic random access memory, the free layers of the memory cells in the magnetic random access memory can be inverted, multi-stage resistance reading can be performed, multi-stage storage is realized, and storage density is improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 1 and 2 are schematic structural diagrams of a magnetic random access memory according to an embodiment of the invention.
Referring to fig. 1 and 2, fig. 2 is an enlarged schematic diagram of a plurality of memory cells 111 in fig. 1, where the magnetic random access memory includes a substrate, a first electrode layer 110 disposed on the substrate, a plurality of memory cells 111 disposed on the first electrode layer 110, the memory cells 111 including a transmissive layer 113, a free layer 114 disposed on the transmissive layer 113, a barrier layer 115 disposed on the free layer 114, and a pinned layer 116 disposed on the barrier layer 115, the transmissive layer 113 of each memory cell 111 having a different thickness, and a second electrode layer 112 disposed on the plurality of memory cells 111, the second electrode layer 112 being electrically connected to the pinned layer 116.
In the mram, by forming a plurality of memory cells 111 on a first electrode layer 110, the thickness of a transmissive layer 113 of each memory cell 111 is different. The transmission layer 113 can adjust critical current density of magnetic moment inversion of the free layer 114 in the memory cell, and thickness of the transmission layer 113 of each memory cell 111 is different, so that critical current density of magnetic moment inversion of the free layer 114 of each memory cell 111 is different, and current with different magnitudes is written into the magnetic random access memory, so that the free layer 114 of different memory cells 111 in the magnetic random access memory can be inverted, multi-stage resistance reading can be performed, multi-stage storage is realized, and storage density is improved.
In this embodiment, the spin-orbit coupling effect of the transmissive layer 113 is smaller than that of the first electrode layer 110. So that the spin current can better pass through the transmissive layer 113.
The material of the transmissive layer 113 includes a metal including copper or aluminum or a metal nitride including titanium nitride.
In this embodiment, the material of the transmissive layer 113 includes copper.
In this embodiment, the material of the first electrode layer 110 includes a metal, and the metal includes tungsten.
In the present embodiment, the thickness of the transmissive layer 113 ranges from 0 nm to 10 nm. The thickness of the transmissive layer 113 ranges from 0 or more to 10 nm or less, i.e., the memory cell does not include the transmissive layer.
In this embodiment, the thickness of the transmission layer 113 of each memory cell changes in a gradient, and the absolute value of the difference between two adjacent gradient transmission layers 113 ranges from 0.2 nm to 1 nm.
The thicker the transmissive layer 113, the less spin current density through the transmissive layer 113, requiring a greater critical current density to flip the magnetic moment of the free layer 114. The thickness of the transmissive layer 113 of each memory cell 111 changes in a gradient, and the increase of the critical current density also changes linearly, i.e., every 0.2 nm to 1 nm of the transmissive layer 113 increases the critical current density for reversing the magnetic moment of the free layer 114 by 10% -50%. The thickness of the transmission layer 113 of each memory cell 111 is changed in a gradient manner, so that the critical current density of the free layer 114 with the magnetic moment inverted is also increased linearly, the reading of the multi-level resistor can be performed, the multi-level storage is realized, and the storage density is improved.
In this embodiment, the number of the memory units 111 ranges from 1 to 50.
In this embodiment, the material of the barrier layer 115 includes magnesium oxide.
In this embodiment, the material of the free layer 114 includes a ferromagnetic material including cobalt-iron-boron, cobalt, iron-germanium-tellurium, cobalt-platinum, cobalt-palladium, nickel-platinum, nickel-palladium, chromium-telluride, or iron-platinum.
In this embodiment, the material of the pinning layer 116 comprises a ferromagnetic material including cobalt-iron-boron, cobalt, iron-germanium-tellurium, cobalt-platinum, cobalt-palladium, nickel-platinum, nickel-palladium, chromium-telluride, or iron-platinum.
In this embodiment, the material of the second electrode layer 112 includes a metal, and the metal includes copper.
In this embodiment, the substrate comprises a base 100, a first word line grating structure 101 and a second word line grating structure 102 located on the base 100, a first doped region 103 and a second doped region 104 located in the base 100 at two sides of the first word line grating structure 101, a third doped region 105 and a fourth doped region 106 located in the base 100 at two sides of the second word line grating structure 102, a first bit line 107 located on the first doped region 103, a first conductive structure 109 located on the second doped region 104, the first electrode layer 110 being located on the first conductive structure 109 and the first electrode layer 110 being electrically connected with the first conductive structure 109, a second conductive structure 120 located on the third doped region 105, the second electrode layer 112 being also located on the second conductive structure 120, the second electrode layer 112 being electrically connected with the second conductive structure 120, a second bit line 108 located on the fourth doped region 106, a dielectric structure (not shown) located on the base 100, the first word line grating structure 101, the second word line grating structure 102, the second bit line 107, and the second bit line structure 109 being located in the dielectric structure 108.
In this embodiment, the first conductive structure 109 includes a plurality of metal layers (not shown) and connection plugs (not shown) between adjacent metal layers, between the metal layers and the second doped region 104, and between the metal layers and the first electrode layer 110, and the second conductive structure 120 includes a plurality of metal layers (not shown) and connection plugs (not shown) between adjacent metal layers, between the metal layers and the third doped region 105, and between the metal layers and the second electrode layer 112.
In this embodiment, the number of the metal layers is two.
In this embodiment, the substrate further comprises a third conductive structure 130 electrically connected to the first electrode layer 110, the third conductive structure 130 being located within the dielectric structure, the first electrode layer 110 being located on the first conductive structure 109 and on the third conductive structure 130. The third conductive structure 130 is used for electrically connecting with other external circuits.
In this embodiment, the first doped region 103 includes a drain doped region, the second doped region 104 includes a source doped region, the third doped region 105 includes a source doped region, and the fourth doped region 106 includes a drain doped region.
The magnetic random access memory has the advantages that the memory cells are located on the first electrode layer 110, the first electrode layer 110 is electrically connected with the second doped region 104 on one side of the first word line grating structure 101, the second electrode layer 112 is electrically connected with the third doped region 105 on one side of the second word line grating structure 102, namely, the read-write of the memory cells can be completed by adopting only two transistors, and the area of the magnetic random access memory is saved.
Correspondingly, the embodiment of the invention also provides a forming method of the magnetic random access memory, which comprises the steps of providing a substrate, forming a first electrode layer 110 on the substrate, forming a plurality of memory cells 111 on the first electrode layer 110, wherein each memory cell 111 comprises a transmission layer 113, a free layer 114 positioned on the transmission layer 113, a barrier layer 115 positioned on the free layer 114 and a pinning layer 116 positioned on the barrier layer 115, the thicknesses of the transmission layers 113 of the memory cells 111 are different, and forming a second electrode layer 112 on the memory cells 111, and the second electrode layer 112 is electrically connected with the pinning layer 116.
In this embodiment, the substrate comprises a base 100, a first word line grating structure 101 and a second word line grating structure 102 located on the base 100, a first doped region 103 and a second doped region 104 located in the base 100 at two sides of the first word line grating structure 101, a third doped region 105 and a fourth doped region 106 located in the base 100 at two sides of the second word line grating structure 102, a first bit line 107 located on the first doped region 103, a first conductive structure 109 located on the second doped region 104, the first electrode layer 110 being located on the first conductive structure 109 and the first electrode layer 110 being electrically connected with the first conductive structure 109, a second conductive structure 120 located on the third doped region 105, the second electrode layer 112 being also located on the second conductive structure 120, the second electrode layer 112 being electrically connected with the second conductive structure 120, a second bit line 108 located on the fourth doped region 106, a dielectric structure (not shown) located on the base 100, the first word line grating structure 101, the second word line grating structure 102, the second bit line 107, and the second bit line structure 109 being located in the dielectric structure 108.
In the present embodiment, the thickness of the transmissive layer 113 ranges from 0nm to 10 nm.
In this embodiment, the number of the memory units 111 ranges from 1 to 50.
FIG. 3 is a flow chart of a method of operating a MRAM in accordance with an embodiment of the invention.
Referring to fig. 3, the working method of the magnetic random access memory includes:
Step S10, providing a magnetic random access memory, wherein the magnetic random access memory is shown in fig. 1 and 2 and comprises a first electrode layer 110 positioned on a substrate, a plurality of memory cells 111 positioned on the first electrode layer 110, wherein each memory cell 111 comprises a transmission layer 113, a free layer 114 positioned on the transmission layer 113, a barrier layer 115 positioned on the free layer 114 and a pinning layer 116 positioned on the barrier layer 115, the thicknesses of the transmission layers 113 of the memory cells 111 are different, a second electrode layer 112 positioned on the memory cells 111, and the second electrode layer 112 is electrically connected with the pinning layer 116;
Step S20, applying first currents with different magnitudes to the first electrode layer 110 to perform writing operation;
step S30, a second current is applied to the second electrode layer 112 for reading operation.
In this embodiment, the substrate comprises a base 100, a first word line grating structure 101 and a second word line grating structure 102 located on the base 100, a first doped region 103 and a second doped region 104 located in the base 100 at two sides of the first word line grating structure 101, a third doped region 105 and a fourth doped region 106 located in the base 100 at two sides of the second word line grating structure 102, a first bit line 107 located on the first doped region 103, a first conductive structure 109 located on the second doped region 104, the first electrode layer 110 being located on the first conductive structure 109 and the first electrode layer 110 being electrically connected with the first conductive structure 109, a second conductive structure 120 located on the third doped region 105, the second electrode layer 112 being also located on the second conductive structure 120, the second electrode layer 112 being electrically connected with the second conductive structure 120, a second bit line 108 located on the fourth doped region 106, a dielectric structure (not shown) located on the base 100, the first word line grating structure 101, the second word line grating structure 102, the second bit line 107, and the second bit line structure 109 being located in the dielectric structure 108.
In the present embodiment, the first electrode layer 110 is applied with the first currents of different magnitudes, and the writing operation includes applying the voltage to the first word line gate structure 101 to turn on the transistor, and applying the first currents of different magnitudes to the first electrode layer 110 through the first bit line 107 to complete the writing operation.
By applying the first currents with different magnitudes to the first electrode layer 110 through the first bit line 107, the free layers 114 of different memory cells in the mram are turned over or not, so that the resistance states of the memory cells 111 are different, and the multi-level memory can be realized, thereby improving the memory density.
In this embodiment, the second current is applied to the second electrode layer 112 for a read operation, including applying a voltage to the second word line gate structure 102 to turn on the transistor and applying a second current to the second electrode layer 112 through the second bit line 108. The read operation is completed by reading the current level of the mram.
In this embodiment, the second current is less than the first current. To complete the read operation.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (21)
1. A magnetic random access memory, comprising:
a substrate;
A first electrode layer on the substrate;
the memory units comprise a transmission layer, a free layer positioned on the transmission layer, a barrier layer positioned on the free layer and a pinning layer positioned on the barrier layer, wherein the transmission layers of the memory units have different thicknesses;
and the second electrode layers are positioned on the memory cells and are electrically connected with the pinning layer.
2. The magnetic random access memory of claim 1 wherein the spin-orbit coupling effect of the transmissive layer is less than the spin-orbit coupling effect of the first electrode layer.
3. The magnetic random access memory of claim 2 wherein the material of the transmissive layer comprises a metal comprising copper or aluminum or a metal nitride comprising titanium nitride.
4. The magnetic random access memory of claim 1 wherein the material of the first electrode layer comprises a metal comprising tungsten.
5. The magnetic random access memory of claim 1 wherein the thickness of the transmissive layer ranges from 0 to 10 nanometers.
6. The mram of claim 5, wherein the thickness of the transmissive layer of each memory cell is graded, and an absolute value of a difference between transmissive layers of adjacent two gradients ranges from 0.2 nm to 1 nm.
7. The magnetic random access memory of claim 1 wherein the number of memory cells ranges from 1 to 50.
8. The magnetic random access memory of claim 1 wherein the material of the barrier layer comprises magnesium oxide.
9. The magnetic random access memory of claim 1 wherein the material of the free layer comprises a ferromagnetic material comprising cobalt-iron-boron, cobalt, iron-germanium-tellurium, cobalt-platinum, cobalt-palladium, nickel-platinum, nickel-palladium, chromium telluride, or iron-platinum.
10. The magnetic random access memory of claim 1 wherein the material of the pinning layer comprises a ferromagnetic material comprising cobalt-iron-boron, cobalt, iron-germanium-tellurium, cobalt-platinum, cobalt-palladium, nickel-platinum, nickel-palladium, chromium telluride, or iron-platinum.
11. The magnetic random access memory of claim 1 wherein the material of the second electrode layer comprises a metal comprising copper.
12. The magnetic random access memory of claim 1 wherein the substrate comprises a base, a first and a second word line gate structure on the base, a first and a second doped region in the base on both sides of the first word line gate structure, a third and a fourth doped region in the base on both sides of the second word line gate structure, a first bit line on the first doped region, a first conductive structure on the second doped region, the first electrode layer on the first conductive structure and electrically connected to the first conductive structure, a second conductive structure on the third doped region, the second electrode layer on the second conductive structure and electrically connected to the second conductive structure, a second bit line on the fourth doped region, a dielectric structure on the base, the first, second, first, second and second conductive structures being located within the dielectric.
13. A method of forming a magnetic random access memory, comprising:
Providing a substrate;
forming a first electrode layer on a substrate;
Forming a plurality of memory units on the first electrode layer, wherein the memory units comprise a transmission layer, a free layer positioned on the transmission layer, a barrier layer positioned on the free layer and a pinning layer positioned on the barrier layer, and the transmission layers of the memory units have different thicknesses;
and forming a second electrode layer on the memory cells, wherein the second electrode layer is electrically connected with the pinning layer.
14. The method of claim 13, wherein the thickness of the transmissive layer of each memory cell is graded, and the absolute value of the difference between the transmissive layers of two adjacent gradients is in the range of 0.2 nm to 1 nm.
15. The method of claim 13, wherein the number of memory cells is in a range of 1 to 50.
16. The method of claim 13, wherein the substrate comprises a base, a first word line gate structure and a second word line gate structure on the base, a first doped region and a second doped region in the base on two sides of the first word line gate structure, a third doped region and a fourth doped region in the base on two sides of the second word line gate structure, a first bit line on the first doped region, a first conductive structure on the second doped region, the first electrode layer on the first conductive structure and electrically connected with the first conductive structure, a second conductive structure on the third doped region, the second electrode layer on the second conductive structure and electrically connected with the second conductive structure, a second bit line on the fourth doped region, a dielectric structure on the base, the first word line gate structure, the second word line gate structure, the first bit line, the first conductive structure, the second conductive structure and the second bit line in the dielectric structure.
17. A method of operating a magnetic random access memory comprising:
Providing a magnetic random access memory, wherein the magnetic random access memory comprises a substrate; the memory cell comprises a transmission layer, a free layer, a barrier layer and a pinning layer, wherein the free layer is arranged on the transmission layer, the barrier layer is arranged on the free layer, the pinning layer is arranged on the barrier layer, and the thickness of the transmission layer of each memory cell is different;
applying first currents with different magnitudes to the first electrode layer, and performing writing operation;
And applying a second current to the second electrode layer to perform a reading operation.
18. The method of claim 17, wherein the second current is less than the first current.
19. The method of claim 17, wherein the substrate comprises a base, a first word line gate structure and a second word line gate structure on the base, a first doped region and a second doped region in the base on two sides of the first word line gate structure, a third doped region and a fourth doped region in the base on two sides of the second word line gate structure, a first bit line on the first doped region, a first conductive structure on the second doped region, the first electrode layer on the first conductive structure and electrically connected with the first conductive structure, a second conductive structure on the third doped region, the second electrode layer on the second conductive structure and electrically connected with the second conductive structure, a second bit line on the fourth doped region, a dielectric structure on the base, the first word line gate structure, the second word line gate structure, the first bit line, the first conductive structure, the second conductive structure and the second bit line in the dielectric structure.
20. The method of claim 18, wherein applying the first current of different magnitudes to the first electrode layer to perform the write operation includes applying a voltage to the first word line gate structure to turn on the transistor and applying the first current of different magnitudes to the first electrode layer through the first bit line.
21. The method of claim 18, wherein applying a second current to the second electrode layer for a read operation includes applying a voltage to the second word line gate structure to turn on the transistor and applying a second current to the second electrode layer through the second bit line.
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