CN119211568A - A video transmission design method and system based on FPGA - Google Patents

Abstract

The invention belongs to the technical field of high-definition video acquisition and transmission, and discloses a video transmission design method and system based on an FPGA. According to the method, through the design of a UDP/IP/MAC receiving module, a UDP/IP/MAC transmitting module, a PHY chip working mode configuration module, a DDR3SDRAM controller and an HDMI control module, under the condition that an IP core is not called, a hardware description language Verilog HDL is used for realizing digital circuit bottom driving of an Ethernet video transmission controller, under the condition that an external physical layer chip is not needed, a Verilog HDL driving circuit is built through the Verilog HDL to complete HDMI physical layer transmitting function, and finally data interaction with an upper computer is completed. The invention saves the area and the cost of the hardware board card and improves the universality, the flexibility and the compatibility of the system.

Description

FPGA-based video transmission design method and system

Technical Field

The invention belongs to the technical field of high-definition video acquisition and transmission, and particularly relates to a video transmission design method and system based on an FPGA.

Background

With the continuous improvement of microelectronics, photoelectric communication, digital video, multimedia technology and modern sensing technology, the wide application and high-speed development of integrated circuits, especially the wide popularization of FPGA (programmable gate array), make analog video systems develop and gradually replace towards digital video systems, and meanwhile digital video systems develop towards high integration level, flexibility, universality, expansibility, compatibility, high resolution, intelligence and ultra-long distance transmission, so that video systems are continuously updated in the technologies of acquisition, buffering, processing, transmission and display, and video systems based on FPGA have become popular.

The Ethernet transmission technology has been widely used in military enterprises and civil enterprises due to the advantages of long transmission distance, high resistance, low ultra-long-distance transmission loss, etc., and the development of high-speed video transmission technology has driven the wide popularization of gigabit Ethernet technology.

Through the analysis, the prior art has the problems and defects that the area and the cost of a hardware board card are high and the universality, the flexibility and the compatibility of the system are poor in the transmission of video data in the prior art.

Disclosure of Invention

In order to overcome the problems in the related art, the disclosed embodiments of the present invention provide a video transmission design method and system based on an FPGA.

The technical scheme is that the design method of the FPGA-based video transmission comprises the steps of realizing digital circuit bottom driving of an Ethernet video transmission controller by using a hardware description language Verilog HDL under the condition of not calling an IP core through the design of a UDP/IP/MAC receiving module, a UDP/IP/MAC transmitting module, a PHY chip working mode configuration module, a DDR3 SDRAM controller and an HDMI control module, and finally completing data interaction with an upper computer by building a Verilog HDL driving circuit through the Verilog HDL under the condition of no external physical layer chip.

Further, the design of the UDP/IP/MAC receiving module comprises the design of a receiving end data sampling conversion module, a clock synchronization module crossing clock domains and a pixel point information extraction module;

The receiving end data sampling conversion module comprises a primitive IDDR in the FPGA for converting double-edge 4bit data into single-edge 8bit data;

the design of the clock synchronization module crossing clock domains comprises that the phase mismatch or clock frequency mismatch between the channel clock PHY_clk transmitted from the PHY chip end received by the data sampling and converting module at the receiving end and the system clock in the FPGA is carried out, the clock domain crossing processing is carried out, and the data is crossed from the physical layer clock domain to the FPGA system clock domain;

the pixel point information extraction module is designed to extract RGB image information from data and data transmitted by the enabling signal through the clock domain crossing processing module.

Further, a multiplier circuit is added in the design of the pixel point information extraction module, and the result obtained by multiplying the information w of the image length and width by h is used as a cache address threshold of the DDR3 SDRAM controller according to an instantiation code template written by the multiplier circuit.

Further, the design of the UDP/IP/MAC sending module comprises the design of a network layer IP protocol, a transmission layer UDP protocol, a data packing sending module of a data link layer MAC sub-layer, a checksum calculating module, a CRC (cyclic redundancy check) algorithm module and a sending end data sampling conversion module;

Filling a preamble, a MAC address, an IP header and UDP header information before transmitting data, and filling the preamble, the MAC address, the IP header and the UDP header information into a protocol data packet which can be identified by a PC;

the checksum calculation module design comprises an algorithm for adding check or error correction to the coding of the data;

The design of the transmitting end data sampling conversion module comprises the step of converting single-edge 8-bit data into double-edge 4-bit data, and the double-edge 4-bit data is in butt joint with an RGMII interface of an external physical layer PHY chip.

Further, the PHY chip operating mode configuration module design includes:

CMODE0, CMODE, CMODE and CMODE3 configuration pins are connected with resistors with different values, the address of the PHY chip is determined through the external resistance value of CMODE and the external resistance value of CMODE3, and the PHY chip is woken up to work normally;

After the PHY chip performs hardware configuration or register configuration, the physical layer chip provides various interfaces for the MAC sub-layer of the data link layer according to the normal operation of the configuration, including MII media independent interface, reduced MII interface, GMII gigabit media independent interface and Reduced GMII interface.

Further, the MDC and the MDIO configure a specific function register in the PHY chip according to the read-write timing sequence, configure the PHY chip into a restart_auto_ negatiation (auto negotiation) working mode, and write the value of the specific function register according to the read-write timing sequence.

Furthermore, the HDMI control module comprises a VGA control module, an 8b10b coding module and a parallel-to-serial module, and the HDMI transmitting end and the upper computer are interacted with each other after the design is completed.

Further, the VGA control module is designed to use a VGA interface time sequence of 640:480@60 Hz to calculate pixel clock clk=800:525:60=25.2 MHz, and support hot plug and audio transmission;

The 8bit to 10bit module design comprises that the quantity of the encoded binary data 1 and 0 is kept consistent, so that direct current is balanced;

The parallel-to-serial module design comprises the steps of converting parallel data into serial data of 2, 8, 10 and 14 bits by using primitives OSERDESE and OSERDESE2 provided by xilinx, configuring OSERDESE2 into a mode of converting the parallel data into 10 bits, and cascading two OSERDESE primitives to obtain 10-bit video data, wherein one serves as a master and the other serves as a slave when parallel-to-serial conversion is processed.

Another object of the present invention is to provide a system for designing FPGA-based video transmission, the system implementing the method for designing FPGA-based video transmission, the system comprising:

The device comprises a UDP/IP/MAC receiving module, a UDP/IP/MAC transmitting module, a PHY chip working mode configuration module, a DDR3 SDRAM controller and an HDMI control module, wherein the DDR3 SDRAM controller and the HDMI control module realize data self-loop transceiving, under the condition of not calling an IP core, a hardware description language Verilog HDL is used for realizing digital circuit bottom driving of an Ethernet video transmission controller, under the condition of no external physical layer chip, a Verilog HDL driving circuit is built through the Verilog HDL to complete HDMI physical layer transmitting function, and finally data interaction with an upper computer is completed.

The invention provides the design and implementation process of the gigabit Ethernet data transmission controller and the HDMI transmitting end controller based on the FPGA, the digital logic circuit design of the MAC sublayer of the data link layer, the UDP protocol of the transmission layer and the IP protocol of the network layer is completed by using the Verilog HDL under the condition of not calling an IP core, and the physical layer transmitting function is completed by directly constructing a driving circuit in the FPGA by using the Verilog HDL under the condition of no external HDMI physical layer chip, so that the high-speed transmission and display of video data are finally realized. The invention saves the area and the cost of the hardware board card and improves the universality, the flexibility and the compatibility of the system.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure;

Fig. 1 is a schematic diagram of a video transmission design system based on FPGA according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of an FPGA-based video transmission design system provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of a PHY chip card configuration;

FIG. 4 is a diagram of read and write timing waveforms of the MDC;

FIG. 5 is a diagram of the read and write timing waveforms of the MDIO;

In the figure, the device comprises a1, a UDP/IP/MAC receiving module, a2, a UDP/IP/MAC transmitting module, a 3, a PHY chip working mode configuration module, a4, DDR3 SDRAM controller, and a5, HDMI control module.

Detailed Description

In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to the appended drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The invention may be embodied in many other forms than described herein and similarly modified by those skilled in the art without departing from the spirit or scope of the invention, which is therefore not limited to the specific embodiments disclosed below.

In the embodiment 1, the design method for video transmission based on the FPGA provided by the embodiment of the present invention realizes the gigabit ethernet video transmission controller and the HDMI transmitting end controller based on the FPGA design, including the configuration principle and the configuration mode of the PHY chip of the physical layer, the UDP protocol of the transport layer, the IP protocol of the network layer and the MAC sublayer implementation scheme of the data link layer, and realizes the digital circuit bottom driving of the ethernet video transmission controller by using the Verilog HDL of the hardware description language without calling the IP core. Under the condition of no external physical layer chip, a Verilog HDL driving circuit is built through the Verilog HDL to realize the HDMI physical layer sending function, and finally, the data interaction with an upper computer is completed. The invention saves the area and the cost of the hardware board card and improves the universality, the flexibility and the compatibility of the system.

As shown in fig. 1, a design system for FPGA-based video transmission according to an embodiment of the present invention includes:

The UDP/IP/MAC receiving module 1, the UDP/IP/MAC sending module 2, the PHY chip working mode configuration module 3, the DDR3 SDRAM controller 4 and the HDMI control module 5 realize data self-loop transceiving, namely the Ethernet transmission function is completed, and a test system is also built. Fig. 2 is a schematic diagram of a design system for FPGA-based video transmission according to an embodiment of the present invention.

Exemplary, the configuration principle and configuration mode of the PHY chip of the physical layer are driven;

The design of the PHY chip working mode configuration module 3 is firstly carried out, namely the design of the PHY hardware configuration and register configuration module, and the physical layer is positioned at the lowest layer of the whole hybrid model, and more detailed division can be divided into three layers, namely a physical medium related sub-layer, a physical medium additional sub-layer and a physical coding sub-layer. At present, a plurality of special chips have the functions realized by the three layers, and the chips can be directly connected with an RJ45 network card interface, if the physical layer chips work normally, special configuration is needed.

As shown in fig. 3, which is a schematic diagram of PHY chip board card configuration, it can be seen from fig. 3 that CMODE0, CMODE1, CMODE and CMODE3 configuration pins are connected with resistors with different values, the values of these resistors are fixed, when the external resistance value of CMODE2 is 22.6K and the external resistance value of CMODE3 is 4.02K, the address of the PHY chip can be determined to be 5' b00000, and at this time, the chip is woken up to work normally. If the board card needs to relate to a plurality of PHY chips and a plurality of network interfaces, the addresses of the chips can be determined by changing external resistance values, and the resistance values can be determined according to PHY chip manuals. In addition, in addition to the hardware configuration mode, the PHY also supports the configuration of an interface register, and it can be seen from fig. 3 that the PHY chip has two pins, namely MDC and MDIO, respectively, where MDC is a clock line and MDIO is a bidirectional data line.

As shown in fig. 4 and fig. 5, which are respectively read-write time sequence waveforms of MDC and MDIO, are half duplex IIC-like buses, and specific function registers in a PHY chip can be configured according to the read-write time sequence, the system needs to configure the PHY chip into a restart_auto_ negatiation (auto negotiation) operation mode, and the following values need to be written into the specific function registers according to the read-write time sequence:

always@(index)

begin

case(index)

0:power_down<=24'h001900;

1:restart_auto_negatiation<=24'h001100;

default:reg_data<=24'h001300;

endcase

end.

For example, after the PHY chip performs hardware configuration or register configuration, the PHY chip may work normally according to the configuration requirement, and the physical layer chip provides multiple interfaces to the data link layer MAC sublayer, such as MII (media independent interface), RMII (Reduced MII), GMII (gigabit media independent interface), RGMII (Reduced GMII), and so on. The GMII differs from the RGMII interface in that the GMII is controlled with 8 data lines, 8 pins, and RGMII is controlled with 4 data lines, 4 pins. The Reduced version has the advantage of saving half of data lines, and can exert the advantages of the Reduced version under the condition of shortage of FPGA pin resources, and the corresponding reference clock frequency needs to be doubled or double-edge sampling is adopted although the data lines are Reduced by half. For example, the PHY has an operating clock of 125MHz, and in the same case, if the data line is halved by 125MHz/s, 4=500 Mb/s, and if the data line is sampled at this time by a single edge, the transmission bandwidth of 1.0Gb/s is not achieved. The bandwidth of 1.0G is generated by using a 125MHz clock on the basis of the original bandwidth, and a double-edge sampling mode is required, namely, the rising edge 4bit and the falling edge 4bit, and the bandwidth is 125 MHz/s. 4*2 =1000 Mb/s.

Illustratively, the UDP/IP/MAC receiving module 1 is designed, namely, the gigabit Ethernet receiving end controller is designed;

After the PHY chip is configured, the Ethernet physical layer works normally, and a gigabit Ethernet receiving end controller is further designed, and mainly comprises a receiving end data sampling conversion module, a clock synchronization module crossing clock domains and a pixel point information extraction module.

The receiving end data sampling conversion module (IDDR data sampling conversion module) is designed, and the data processing mode adopted by the FPGA is single-edge sampling generally, and because the design adopts an RGMII interface, the PHY chip outputs double-edge sampling data to the FPGAMAC sublayer, so that the double-edge 4bit data is required to be converted into single-edge 8bit data by using the primitive IDDR in the FPGA, and the single-edge 8bit data is converted in the FPGA, otherwise, the meaning of data transmission is lost, and the function of original data is lost.

After the IDDR data sampling conversion module is completed, the double-edge 4bit data transmitted by the PHY is converted into single-edge 8bit data and a corresponding data synchronization enabling signal. However, there is a problem that the channel associated clock phy_clk transmitted from the PHY chip end is inconsistent with the system clock in the FPGA, and there is a phase mismatch or a clock frequency inconsistency, which all cause a metastable state problem in the data transmission process, so that errors occur in the received data. Therefore, a cross-clock domain process is required to cross data from the physical layer clock domain to the FPGA system clock domain.

When the design of the pixel information extraction module is carried out, the data and the enabling signals are processed by the clock domain crossing processing module, the transmitted data not only comprises RGB data information transmitted by an upper computer, but also comprises destination MAC address, source MAC address and preamble information, and the data need to be filtered, so that the pixel information extraction module, namely the RGB image information extraction module, is designed after the data is processed by the clock domain crossing processing module, and is a crucial step. In addition, a multiplier circuit is added to the pixel point information extraction module, an exemplary code template written by the multiplier circuit is adopted as the cache address threshold of the DDR3 SDRAM controller 4, and the result obtained by multiplying the information w of the image length and width by h is adopted as the cache address threshold.

Illustratively, the UDP/IP/MAC transmitting module 2 is designed, namely, the transmitting end controller is designed;

After the gigabit ethernet receiving end controller is completed, the design and implementation of the gigabit ethernet transmitting end controller are also required. The system mainly comprises a network layer IP protocol, a transmission layer UDP protocol, a data packing and transmitting module of a data link layer MAC sub-layer, a checksum calculating module, a CRC algorithm module and a transmitting end data sampling and converting module.

The difference between the sending end controller and the receiving end controller is that the receiving end only needs to receive the data of the upper computer according to the time sequence and extract the image data information, and the preamble and the MAC address information transmitted by the upper computer need to be filtered in the process. When the FPGA board sends data to the PC, the PC cannot recognize if only the data is sent.

The data packaging and transmitting module is designed and realized, and the difference between the transmitting end controller and the receiving end controller is that the receiving end only needs to receive the data of the upper computer according to the time sequence and extract the image data information, and the preamble and the MAC address information transmitted by the upper computer need to be filtered in the process. When the FPGA board sends data to the PC, if the data is only sent, the PC cannot recognize the data, so that information such as a preamble, a MAC address, an IP header, and a UDP header needs to be filled before the data is sent, and the information is filled into a protocol data packet that the PC can recognize.

In the communication field, errors may occur in the data transmission process due to some interference, and in order to reduce the occurrence of such errors, the hardware reliability is improved, and meanwhile, some algorithm support for checking or error correction is added on the coding of the data. The most common way is to incorporate a check mechanism or check bit into the data, and such a code with error correction capability is called a check code.

When the upper computer sends data to the FPGA through the sending end of the Ethernet, a PHY chip of a physical layer is needed, and under the condition that the configuration interface of the PHY chip in the design is an RGMII interface and the clock frequency and the transmission rate are unchanged, the transmission is carried out in a double-edge sampling mode, but the inside of the FPGA is always in a single-edge sampling working mode, and at the moment, the IDDR module is used for converting double-edge 4bit data into single-edge 8bit data. After the data is processed by the FPGA, the single-edge 8-bit data is converted into double-edge 4-bit data through a ODDR module, and the double-edge 4-bit data is in butt joint with an RGMII interface of an external physical layer PHY chip.

Illustratively, the HDMI control module 5 is designed, i.e., the HDMI transmit controller is designed;

Modular functionality of gigabit ethernet transport controllers has been implemented previously. The system comprises a PHY working principle and configuration mode of a receiving end, a cross-clock domain processing module and an RGB image information extraction module, and a data framing module, a checksum module, a CRC module and a ODDR module of a transmitting end. Further realizing the modularized function of the HDMI transmitting end controller, and using the Verilog HDL to build a Verilog HDL driving circuit to replace the physical layer chip transmitting end function.

The design of the required HDMI control module 5 comprises a VGA control module, an 8b10b coding module and a parallel-to-serial conversion module, and the data interaction between the HDMI transmitting end and the upper computer can be realized after the design is completed.

The VGA control module is designed and realized, and VGA is a universal image video transmission protocol and has the advantages of high resolution, rich colors and the like. Is widely applied to the fields of color displays and the like. However, the disadvantage that it does not support hot plug and audio transmission also limits its application area. The invention uses 640 x 480@60Hz VGA interface time sequence, calculates pixel clock clk=800 x 525 x 60=25.2 MHz, and needs to be explained that the line synchronizing signal and the field synchronizing signal are both valid at low level, and the line synchronizing signal is also provided in a data line invalid area.

After the external video image data is converted into the information corresponding to the resolution pixel point through the VGA control module, a conversion module from 8bit to 10bit is needed to be designed, and the purpose of the conversion module is to keep the balance of direct current and keep the quantity of the encoded binary data 1 and 0 consistent. The biggest problem overcome by the dc equalization is that when the logic 1 and the logic 0 of the high-speed serial stream with multiple bits are unchanged, the signal transmission error is caused by the voltage level relation during the signal conversion.

And (3) carrying out parallel-to-serial module design to complete the realization process of the 8 bit-to-10 bit coding module, and designing a last module, namely a serial-to-parallel module. In processing parallel-to-serial conversion, the primitives OSERDESE, OSERDESE2 provided by xilox are also used to support conversion of parallel data into 2, 8, 10, and 14bit serial serialized data, where OSERDESE2 is configured as a parallel data to 10bit pattern. To obtain 10bit video data, two OSERDESE primitives need to be concatenated, one as a master and the other as a slave.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.

While the invention has been described with respect to what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Claims (9)

1. A design method for video transmission based on FPGA, characterized in that the method uses the design of a UDP/IP/MAC receiving module (1), a UDP/IP/MAC sending module (2), a PHY chip working mode configuration module (3), a DDR3 SDRAM controller (4) and an HDMI control module (5), and uses the hardware description language Verilog HDL to realize the bottom-level driver of the digital circuit of the Ethernet video transmission controller without calling the IP core; in the absence of an external physical layer chip, a Verilog HDL driving circuit is built by Verilog HDL to complete the HDMI physical layer sending function, and finally completes the data interaction with the host computer. 2. The design method of video transmission based on FPGA according to claim 1, characterized in that the design of the UDP/IP/MAC receiving module (1) includes: the design of a receiving end data sampling conversion module, a cross-clock domain clock synchronization module and a pixel point information extraction module; The receiving end data sampling conversion module design includes: using the primitive IDDR inside the FPGA to convert the double-edge 4-bit data into single-edge 8-bit data; The design of the cross-clock domain clock synchronization module includes: performing cross-clock domain processing on the phase mismatch or clock frequency inconsistency between the accompanying clock PHY_clk transmitted from the PHY chip end received by the receiving end data sampling conversion module and the system clock in the FPGA, and crossing the data from the physical layer clock domain to the FPGA system clock domain; The design of the pixel point information extraction module includes: extracting RGB image information from data and enable signals transmitted through the cross-clock domain processing module. 3. The design method of video transmission based on FPGA according to claim 2 is characterized in that, in the design of the pixel information extraction module, a multiplier circuit is further added, and according to the instantiation code template written by the multiplier circuit, the result obtained by multiplying the image length and width information w and h is used as the cache address threshold of the DDR3 SDRAM controller (4). 4. The design method of video transmission based on FPGA according to claim 1 is characterized in that the design of the UDP/IP/MAC sending module (2) includes the design of the network layer IP protocol, the transport layer UDP protocol, and the data packet sending module, the checksum calculation module, the CRC check algorithm module and the sending end data sampling conversion module of the data link layer MAC sublayer; The design of the data packaging and sending module includes: filling the preamble, MAC address, IP header and UDP header information before sending the data, filling it into a protocol data packet that can be recognized by the PC; The design of the verification and calculation module includes: adding a verification or error correction algorithm to the encoding of the data; The design of the data sampling conversion module at the transmitting end includes: converting the single-edge 8-bit data into double-edge 4-bit data, and connecting with the RGMII interface of the external physical layer PHY chip. 5. The design method of video transmission based on FPGA according to claim 1, characterized in that the design of the PHY chip working mode configuration module (3) includes: The CMODE0, CMODE1, CMODE2 and CMODE3 configuration pins are connected to resistors of different values, and the address of the PHY chip is determined by the external resistance value of CMODE2 and the external resistance value of CMODE3, and the PHY chip is awakened to work normally; the PHY chip is also configured with two pins, MDC and MDIO, where MDC is a clock line and MDIO is a bidirectional data line; After the PHY chip performs hardware configuration or register configuration, it works normally according to the configuration, and the physical layer chip provides multiple interface standards to the data link layer MAC sublayer, including MII media independent interface, Reduced MII interface, GMII Gigabit media independent interface and Reduced GMII interface. 6. The design method of video transmission based on FPGA according to claim 5 is characterized in that the MDC and MDIO configure the specific function registers in the PHY chip according to the read and write timing, configure the PHY chip to the restart_auto_negatiation (auto-negatiation) working mode, and write the value of the specific function register according to the read and write timing. 7. The design method of video transmission based on FPGA according to claim 1 is characterized in that the design of the HDMI control module (5) includes the design of a VGA control module, an 8b10b encoding module and a parallel-to-serial module, and after the design is completed, data interaction between the HDMI transmitter and the host computer is realized. 8. The design method of video transmission based on FPGA according to claim 7 is characterized in that the design of the VGA control module includes: using the VGA interface timing of 640*480@60Hz, calculating the pixel clock clk=800*525*60=25.2MHz, supporting hot plugging and audio transmission; The 8-bit to 10-bit module design includes: the number of 1s and 0s in the encoded binary data is kept consistent to make the DC balanced; The parallel-to-serial module design includes: when processing parallel-to-serial conversion, using the primitive OSERDESE2 provided by Xilinx, OSERDESE2 supports converting parallel data into 2, 8, 10 and 14-bit serial serialized data, configuring OSERDESE2 to convert parallel data into 10-bit mode, cascading two OSERDESE2 primitives to obtain 10-bit video data, one of which serves as the host and the other as the slave. 9. A design system for video transmission based on FPGA, characterized in that the system implements the design method for video transmission based on FPGA according to any one of claims 1 to 8, and the system comprises: The UDP/IP/MAC receiving module (1), the UDP/IP/MAC sending module (2), the PHY chip working mode configuration module (3), the DDR3 SDRAM controller (4) and the HDMI control module (5) realize data self-loop transmission and reception. Without calling the IP core, the hardware description language Verilog HDL is used to realize the underlying driver of the digital circuit of the Ethernet video transmission controller; without an external physical layer chip, the Verilog HDL driver circuit is built by Verilog HDL to complete the HDMI physical layer transmission function, and finally complete the data interaction with the host computer.