CN119210614B - An on-chip automatic calibration system for local oscillator leakage and I/Q imbalance - Google Patents
An on-chip automatic calibration system for local oscillator leakage and I/Q imbalance Download PDFInfo
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- CN119210614B CN119210614B CN202411310532.5A CN202411310532A CN119210614B CN 119210614 B CN119210614 B CN 119210614B CN 202411310532 A CN202411310532 A CN 202411310532A CN 119210614 B CN119210614 B CN 119210614B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/16—Multiple-frequency-changing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
- H04B1/50—Circuits using different frequencies for the two directions of communication
- H04B1/52—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa
- H04B1/525—Hybrid arrangements, i.e. arrangements for transition from single-path two-direction transmission to single-direction transmission on each of two paths or vice versa with means for reducing leakage of transmitter signal into the receiver
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B17/00—Monitoring; Testing
- H04B17/10—Monitoring; Testing of transmitters
- H04B17/11—Monitoring; Testing of transmitters for calibration
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Abstract
The invention discloses an on-chip automatic calibration system for local oscillation leakage and I/Q imbalance, which comprises a first partial circuit used as a mixer, a second partial circuit used as a local oscillation leakage and image frequency detection circuit and a third partial circuit used as a digital control circuit; the invention detects the local oscillation leakage and the image frequency signal of the output port of the transmitter by a self-mixing method, realizes the detection of the local oscillation leakage and the I/Q imbalance, automatically adjusts the output current of the current type DAC in the transconductance stage of the mixer according to the detection result by using the on-chip digital circuit, and realizes the automatic calibration of the integrated local oscillation leakage and the I/Q imbalance on the chip.
Description
Technical Field
The invention relates to the technical field of power electronic design, in particular to an on-chip automatic calibration system for local oscillator leakage and I/Q imbalance.
Background
In the variable frequency transmitter, local oscillator leakage and I/Q imbalance are the two most important indexes, and excessive local oscillator leakage and I/Q imbalance can affect the constellation diagram of the transmitted signal, so that the constellation diagram generates displacement in the horizontal or vertical direction. Therefore, when designing a transmitter, the reduction of local oscillation leakage and I/Q imbalance needs to be considered, the local oscillation leakage and I/Q imbalance can be improved by optimizing the selection of the transistor size of the mixer and the symmetry of the layout, the main factor of the local oscillation leakage is caused by the inconsistent currents of two differential paths in the transconductance stage I path or the transconductance stage Q path, the main factor of the I/Q imbalance is caused by the inconsistent currents of the transconductance stage I path and the transconductance stage Q path, and the local oscillation leakage and I/Q imbalance can be improved by adjusting the bias voltage of each path transconductance of an actual chip mixer.
The traditional method for calibrating the local oscillation leakage and the I/Q imbalance of the transmitter is to read the local oscillation leakage and the image signal output by the transmitter through a vector network analyzer, and manually adjust the offset voltage of the transconductance stage of the mixer to minimize the output local oscillation leakage and the image signal. This method requires expensive equipment, requires a long time for calibration, and after a certain period of operation of the chip, the environment inside the chip may change, and the result of the original calibration is no longer an optimal value.
Disclosure of Invention
Aiming at three important concerns of local oscillation leakage, I/Q imbalance and on-chip incapability of accurately and automatically calibrating in the prior art, the invention discloses an on-chip automatic calibration system for local oscillation leakage and I/Q imbalance, which is added with a local oscillation leakage and I/Q imbalance calibration circuit based on a traditional frequency converter, and a broadband local oscillation leakage and image frequency signal detection circuit and an on-chip digital control circuit, so that signal reading and automatic calibration are realized under the condition of no need of external instruments and manual adjustment.
The technical scheme is that the following technical scheme is adopted to achieve the technical purpose.
An on-chip automatic calibration system for local oscillation leakage and I/Q imbalance includes a first partial circuit 1000 functioning as a mixer, a second partial circuit 2000 functioning as a local oscillation leakage and image frequency detection circuit, and a third partial circuit 3000 functioning as a digital control circuit;
The first partial circuit 1000 includes a I, Q mixer formed by two gilbert units, the input of which is a quadrature intermediate frequency signal provided by the outside, including IF_I+, IF_I-, IF_Q+, IF_Q-, and quadrature local oscillator signals including LO_I+, LO_I-, LO_Q+, LO_Q-, the output of which is a radio frequency differential signal including RF+ and RF-, the radio frequency differential signal is amplified by a power amplifier and then coupled into a single-ended radio frequency signal RF at the radio frequency output end of the transmitter, and the total four transconductance stages of positive and negative paths of the I, Q mixer are controlled by current-mode DACs respectively, thereby realizing that local oscillator leakage and I/Q imbalance can be calibrated;
The second partial circuit 2000 is configured to perform local oscillation leakage and image detection on the single-ended radio frequency signal RF, and finally convert the local oscillation leakage and the image signal into a digital signal proportional to the power thereof;
The output end of the third partial circuit 3000 is connected to the current DAC in the first partial circuit 1000, and is configured to obtain the current local oscillation leakage and the image frequency by reading the digital signal generated by the second partial circuit 2000, so as to find the IDAC output with the least local oscillation leakage and the image frequency by using a traversing method.
The method has the advantages that local oscillator leakage and image frequency signals of the output port of the transmitter are detected through a self-mixing method, local oscillator leakage and I/Q imbalance detection is achieved, an on-chip digital circuit is used for automatically adjusting output current of a current type DAC in the transconductance stage of the mixer according to detection results, and automatic calibration of on-chip integrated local oscillator leakage and I/Q imbalance is achieved.
Drawings
FIG. 1 is a schematic diagram of an on-chip automatic calibration system for local oscillator leakage and I/Q imbalance according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a first circuit configuration of an on-chip automatic calibration system for local oscillator leakage and I/Q imbalance according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a second part of an on-chip automatic calibration system for local oscillator leakage and I/Q imbalance according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a third control logic portion of an on-chip automatic calibration system for local oscillator leakage and I/Q imbalance according to an embodiment of the present application;
FIG. 5 is a graph of local oscillator leakage rejection test results for a transmitter with an on-chip auto-calibration system with local oscillator leakage and I/Q imbalance;
Fig. 6 is a graph of image rejection test results for a transmitter with an on-chip auto-calibration system with local oscillator leakage and I/Q imbalance.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, integrally connected, mechanically connected, electrically connected, directly connected, indirectly connected through an intermediate medium, or in communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings.
Examples
As shown in fig. 1, an on-chip automatic calibration system for local oscillation leakage and I/Q imbalance of the present embodiment is suitable for a transmitter, and includes a first partial circuit 1000 serving as a mixer, a second partial circuit 2000 serving as a local oscillation leakage and image frequency detection circuit, and a third partial circuit 3000 serving as a digital control circuit;
The first partial circuit 1000 comprises I, Q mixers composed of two Gilbert units, wherein the inputs of the I, Q mixers are quadrature intermediate frequency signals provided by the outside, the quadrature intermediate frequency signals comprise IF_I+, IF_I-, IF_Q+, IF_Q-, and quadrature local oscillation signals, the quadrature local oscillation signals comprise LO_I+, LO_I-, LO_Q+, LO_Q-, and the output of the quadrature local oscillation signals are radio frequency differential signals, the RF differential signals comprise RF+ and RF-, the radio frequency differential signals are amplified by a power amplifier and are coupled into single-ended radio frequency signals RF at the radio frequency output end of a transmitter, and the plus and minus four transconductance stages of the I, Q mixers are respectively controlled by a current type DAC, so that local oscillation leakage and I/Q imbalance can be calibrated;
The second partial circuit 2000 is configured to perform local oscillation leakage and image detection on the single-ended radio frequency signal RF, and finally convert the local oscillation leakage and the image signal into a digital signal proportional to the power thereof;
The output end of the third partial circuit 3000 is connected to the current DAC in the first partial circuit 1000, and is used for obtaining the current local oscillation leakage and the image frequency by reading the digital signal generated by the second partial circuit 2000, so as to find the IDAC output that minimizes the local oscillation leakage and the image frequency by using a traversal method.
As shown in fig. 2, the first partial circuit 1000 includes an I-way mixer switching stage, an I Lu Hunpin transconductance stage, and a series inductance between the two stages, a Q-way mixer switching stage, a Q Lu Hunpin transconductance stage, and a series inductance between the two stages, a current-type DAC connected to the I Lu Hunpin transconductance stage and the Q Lu Hunpin transconductance stage for controlling the four-way mixer, and a transconductance stage bias resistor connected to the I Lu Hunpin transconductance stage and the Q Lu Hunpin transconductance stage;
The I-path mixer switching stage is connected with the I-path mixer transconductance stage through a series inductor, the Q-path mixer switching stage is connected with the Q-path mixer transconductance stage through a series inductor, the input signals of the I-path mixer switching stage are LOI+ and LOI-, the input signals of the Q-path mixer switching stage are LOQ+ and LOQ-, LOI-, LOQ+ and LOQ-are quadrature local oscillation signals, the mixer output signals are RF+ and RF-, namely radio frequency differential output signals, the input signals connected with the I Lu Hunpin transconductance stage are IF I+ and IF_I-, the input signals connected with the Q Lu Hunpin transconductance stage are IF_Q+ and IF_Q-, IF_Q+ and IF_Q-are quadrature local oscillation signals after buffer amplification;
The I-channel mixer switching stage is used as a switching stage of a Gilbert unit and comprises a first transistor 1021, a second transistor 1022, a third transistor 1023 and a fourth transistor 1024, wherein the source electrode of the first transistor 1021 is connected with the source electrode of the second transistor 1022, the source electrode of the third transistor 1023 is connected with the source electrode of the fourth transistor 1024, the drain electrode of the first transistor 1021 is connected with the drain electrode of the third transistor 1023, the drain electrode of the second transistor 1022 is connected with the drain electrode of the fourth transistor 1024 and is used as an output end of the I-channel mixer, the grid electrodes of the first transistor 1021 and the fourth transistor 1024 are connected as a positive input end of a local oscillation signal I channel, the grid electrodes of the second transistor 1022 and the third transistor 1023 are connected as a negative input end of a local oscillation signal I channel, and an input signal LO I-;
Similarly, the Q-channel mixer switching stage, which is used as a switching stage of a Gilbert cell, comprises a fifth transistor 1025, a sixth transistor 1026, a seventh transistor 1027 and an eighth transistor 1028, wherein the sources of the fifth transistor 1025 and the sixth transistor 1026 are connected, the sources of the seventh transistor 1027 and the eighth transistor 1028 are connected, the drains of the fifth transistor 1025 and the seventh transistor 1027 are connected, the drains of the sixth transistor 1026 and the eighth transistor 1028 are connected and used as an output end of the Q-channel mixer, the gates of the fifth transistor 1025 and the eighth transistor 1028 are connected and used as a positive input end of a local oscillation signal Q channel, the gates of the input signal LO_Q+ and the sixth transistor 1026 and the seventh transistor 1027 are connected and used as a negative input end of the local oscillation signal Q channel, and the input signal LO_Q-;
After the output ends of the two paths of mixers, namely the I path mixer and the Q path mixer, are connected, the residual sidebands are counteracted, and the single sidebands are added to obtain single sideband output, and output signals RF+ and RF-, namely radio frequency differential output signals.
The I-way mixer transconductance stage comprises a ninth transistor 1002, a tenth transistor 1004, an eleventh transistor 1005, a twelfth transistor 1007, the q Lu Hunpin transconductance stage comprises a thirteenth transistor 1010, a fourteenth transistor 1012, a fifteenth transistor 1013, a sixteenth transistor 1015, the current-mode DAC controlling the four-way mixer comprises a first IDAC1001, a second IDAC1008, a third IDAC1009, a fourth IDAC1016, and the transconductance stage bias resistor comprises a first resistor 1003, a second resistor 1006, a third resistor 1011, and a fourth resistor 1014;
I. the positive and negative total four paths of transconductance stages of the Q mixer are respectively controlled by a current-mode DAC, so that local oscillation leakage and I/Q imbalance can be calibrated, a ninth transistor 1002, a twelfth transistor 1007, a thirteenth transistor 1010 and a sixteenth transistor 1015 form a transconductance-stage current mirror, the gates of all the transistors in the current mirror are connected with the drain, the source is grounded, the drain of the ninth transistor 1002 is connected with a first IDAC1001, the drain of the twelfth transistor 1007 is connected with a second IDAC1008, the drain of the thirteenth transistor 1010 is connected with a third IDAC1009, the drain of the sixteenth transistor 1015 is connected with a fourth IDAC1016, and each IDAC can be controlled by a digital circuit, namely a third partial circuit 3000 to control the output size of current, and the control amplitude is 60 mu A; the invention adopts the current type DAC to control the four-way current at the offset position of the four-way transconductance of the mixer, thereby realizing the calibration of local oscillation leakage and I/Q imbalance.
A gate of the ninth transistor 1002 and a gate of the tenth transistor 1004 in the I-channel mixer transconductance stage are connected through a first resistor 1003, a gate of the eleventh transistor 1005 and a gate of the twelfth transistor 1007 are connected through a second resistor 1006, sources of the tenth transistor 1004 and the eleventh transistor 1005 are grounded, a gate of the thirteenth transistor 1010 and a gate of the fourteenth transistor 1012 in the Q-channel mixer transconductance stage are connected through a third resistor 1011, a gate of the fifteenth transistor 1013 and a gate of the sixteenth transistor 1015 are connected through a fourth resistor 1014, and sources of the fourteenth transistor 1012 and the fifteenth transistor 1013 are grounded.
The series inductance between the mixer switching stage and the transconductance stage comprises a first inductance 1017, a second inductance 1018, a third inductance 1019, a fourth inductance 1020, the drain of a tenth transistor 1004 in the I-channel mixer transconductance stage is connected with the sources of a first transistor 1021 and a second transistor 1022 in the I-channel mixer switching stage through the first inductance 1017, the drain of an eleventh transistor 1005 in the I-channel mixer transconductance stage is connected with the sources of a third transistor 1023 and a fourth transistor 1024 in the I-channel mixer switching stage through the second inductance 1018, the drain of a fourteenth transistor 1012 in the Q-channel mixer transconductance stage is connected with the sources of a fifth transistor 1025 and a sixth transistor 1026 in the Q-channel mixer switching stage through the third inductance 1019, and the drain of a fifteenth transistor 1013 in the Q-channel mixer transconductance stage is connected with the sources of a seventh transistor 1027 and an eighth transistor 1028 in the Q-channel mixer switching stage through the fourth inductance 1020.
The first transistor 1021, the second transistor 1022, the third transistor 1023, the fourth transistor 1024, the fifth transistor 1025, the sixth transistor 1026, the seventh transistor 1027, and the eighth transistor 1028 are the same in size, the ninth transistor 1002, the twelfth transistor 1007, the thirteenth transistor 1010, and the sixteenth transistor 1015 are the same in size, the tenth transistor 1004, the eleventh transistor 1005, the fourteenth transistor 1012, and the fifteenth transistor 1013 are the same in size, the first IDAC1001, the second IDAC1008, the third IDAC1009, and the fourth IDAC1016 have the same current output range, the first resistor 1003, the second resistor 1006, the third resistor 1011, and the fourth resistor 1014 have the same resistance value, and the first inductor 1017, the second inductor 1018, the third inductor 1019, and the fourth inductor 1020 have the same inductance value.
As shown in fig. 3, the second partial circuit 2000 includes an input coupling transformer 2100, a self-mixer 2200, a low-pass filter 2300, a voltage amplifier 2400, an envelope detector 2500 and an ADC2600, where the input coupling transformer 2100 is a first-stage input, the self-mixer 2200, the low-pass filter 2300, the voltage amplifier 2400 and the envelope detector 2500 are cascaded in sequence, and two outputs of the envelope detector 2500 are respectively connected to two inputs of the ADC2600, and finally the local oscillation leakage and the image signal are converted into a digital signal proportional to the power thereof, and the digital signal is input to the third partial circuit 3000;
The input coupling transformer 2100 is formed by coupling a primary coil and a secondary coil, so that a T model function formed by serially connecting and parallelly connecting inductors is realized, the chip area is reduced, and the function of coupling a transmitter output signal RF to the second partial circuit 2000 under the condition that the transmitting power is hardly influenced is realized;
The self-mixer 2200 is a one-stage self-mixer, and comprises a seventeenth transistor 2203, an eighteenth transistor 2204, a nineteenth transistor 2207, a twentieth transistor 2208, a fifth resistor 2201, a sixth resistor 2202, a seventh resistor 2209, an eighth resistor 2210, a ninth resistor 2211, a first capacitor 2205 and a second capacitor 2206, wherein the input end of the self-mixer 2200 is in+ and IN-, and the output end is OUT;
The drain of the seventeenth transistor 2203 is connected to the source of the nineteenth transistor 2207, the drain of the eighteenth transistor 2204 is connected to the source of the twentieth transistor 2208, the gate of the seventeenth transistor 2203 is connected to the positive input terminal in+, the gate of the eighteenth transistor 2204 is connected to the negative input terminal IN-, the seventeenth transistor 2203 is grounded to the source of the eighteenth transistor 2204, the gates of the nineteenth transistor 2207 and the twentieth transistor 2208 are connected to the bias voltage Vb2, the drains of the nineteenth transistor 2207 and the twentieth transistor 2208 are connected to the output terminal OUT, the output terminal OUT is connected to the power supply through the fifth resistor 2201, the output terminal OUT is connected to the gate of the seventeenth transistor 2203 through the eighth resistor 2210, the second capacitor 2206 is connected to the gate of the eighteenth transistor 2204 IN sequence, the gate of the seventeenth transistor 2203 is connected to the bias voltage Vb1 through the fifth resistor 2201, the output terminal OUT is connected to the output terminal 2300 through the sixth resistor 2300;
The seventeenth transistor 2203 has the same size as the eighteenth transistor 2204, the nineteenth transistor 2207 has the same size as the twentieth transistor 2208, the fifth resistor 2201 has the same resistance as the sixth resistor 2202, the seventh resistor 2209 has the same resistance as the eighth resistor 2210, and the first capacitor 2205 has the same capacitance as the second capacitor 2206;
the self-mixer 2200 mixes the radio frequency and local oscillator leakage coupled by the input coupling transformer 2100 with the image frequency signal, and outputs components such as a double intermediate frequency, a radio frequency and a radio frequency third harmonic, wherein the double intermediate frequency is a product of mixing the radio frequency and the local oscillator leakage, and the double intermediate frequency is a product of mixing the radio frequency and the image frequency, and the values of the local oscillator leakage and the image frequency in the original signal are respectively represented;
The low-pass filter 2300 is a first-stage low-pass filter and comprises a fifth inductor 2301, a third capacitor 2302 and a fourth capacitor 2303, wherein the input end of the low-pass filter is IN, and the output end of the low-pass filter is OUT, the fifth inductor 2301 is connected with the third capacitor 2302 IN parallel, one end of the fifth inductor is connected with IN, the other end of the fifth inductor is connected with OUT, one end of the fourth capacitor 2303 is connected with OUT, the other end of the fourth capacitor is connected with the ground, and the output end OUT is connected with the input end of the voltage amplifier 2400;
The voltage amplifier 2400 is a two-stage voltage amplifier, and includes a twenty-first transistor 2402, a twenty-second transistor 2403, a twenty-third transistor 2412, a twenty-fourth transistor 2411, a fifth capacitor 2401, a sixth capacitor 2407, a seventh capacitor 2408, an eighth capacitor 2410, a ninth capacitor 2414, a sixth inductor 2404, a seventh inductor 2406, a tenth resistor 2405, an eleventh resistor 2409, a twelfth resistor 2413, and a thirteenth resistor 2415, where an input terminal of the voltage amplifier 2400 is IN, and an output terminal is OUT;
A gate of the twenty-first transistor 2402 is connected to the input terminal IN through a fifth capacitor 2401, a source of the twenty-first transistor 2402 is grounded, a gate of the twenty-first transistor 2402 is connected to the voltage bias Vb1, a drain of the twenty-first transistor 2402 is connected to a source of the twenty-first transistor 2403, a gate of the second transistor 2403 is connected to the bias voltage Vb2, a drain of the twenty-first transistor 2403 is connected to the power supply by sequentially connecting a sixth inductor 2404 and a tenth resistor 2405 IN series, a seventh inductor 2406 is connected IN parallel with a sixth capacitor 2407, one end is connected to a drain of the second transistor 2403, the other end is connected to a gate of the twenty-third transistor 2412 through an eighth capacitor 2410, a drain of the twenty-first transistor 2403 is connected to a gate of the twenty-first transistor 2402 by sequentially connecting a seventh capacitor 2408 and an eleventh resistor 2409 IN series, and the sixth inductor 2404 is coupled to the seventh inductor 2406; the drain of the twenty-third transistor 2412 is connected to the source of the twenty-fourth transistor 2411, the gate of the twenty-third transistor 2412 is connected to the bias voltage Vb3, the source of the twenty-fourth transistor 2412 is grounded, the gate of the twenty-fourth transistor 2411 is connected to the bias voltage Vb4, the drain of the twenty-fourth transistor 2411 is connected to the power supply through a twelfth resistor 2413, the drain of the twenty-fourth transistor 2411 is connected to the output terminal OUT, and the output terminal OUT is connected to the gate of the twenty-third transistor 2412 by sequentially connecting the ninth capacitor 2414 and the thirteenth resistor 2415 IN series;
The voltage amplifier 2400 is used for amplifying the voltage of the signal with the intermediate frequency and the signal with the intermediate frequency, which are output from the mixer 2200, and filtering the interference component with the intermediate frequency and the signal with the intermediate frequency, and the low-pass filter 2300 and the voltage amplifier 2400 cooperate to filter the interference component with the intermediate frequency and the signal with the intermediate frequency more thoroughly.
The envelope detector 2500 is a one-stage envelope detector including a twenty-fifth transistor 2503, a twenty-sixth transistor 2504, a twenty-seventh transistor 2508, a twenty-eighth transistor 2509, a twenty-ninth transistor 2510, a thirty-first transistor 2513, a thirty-first transistor 2514, a tenth capacitor 2501, an eleventh capacitor 2506, a twelfth capacitor 2512, a thirteenth capacitor 2515, a fourteenth capacitor 2507, a fourteenth resistor 2502, a fifteenth resistor 2505, a sixteenth resistor 2511, an input terminal of the envelope detector being IN, and output terminals being OUT1 and OUT2;
A gate of the twenty-fifth transistor 2503 is connected to the input terminal IN through a tenth capacitor 2501, a gate of the twenty-fifth transistor 2503 is connected to the bias voltage Vb1 through a fourteenth resistor 2502, a source of the twenty-fifth transistor 2503 is grounded, a gate of the twenty-sixth transistor 2504 is connected to the ground through an eleventh capacitor 2506, a gate of the twenty-sixth transistor 2504 is connected to the bias voltage Vb1 through a fifteenth resistor 2505, a drain of the twenty-fifth transistor 2503 is connected to a drain of the twenty-sixth transistor 2504, an output terminal OUT2 is connected to the drain of the twenty-ninth transistor 2510, an output terminal OUT2 is grounded through a fourteenth capacitor 2512, a source of the twenty-ninth transistor 2510 is connected to the power supply through a twelfth capacitor 2512, a gate of the twenty-eighth transistor 2510 is connected to the drain of the twenty-eighth transistor 2509, a source of the twenty-eighth transistor 2509 is connected to the power supply source, a drain of the twenty-eighth transistor 2509 is connected to the drain of the twenty-eighth transistor, a drain of the output transistor 2509 is connected to the drain of the output transistor OUT2 through a thirteenth capacitor 2508, a drain of the output terminal OUT2 is connected to the drain of the thirty-eighth transistor 2511 is connected to the drain of the thirty-eighth transistor, a drain of the output transistor 2512 is connected to the drain of the thirty-eighth capacitor, a drain of the output transistor 2512 is connected to the drain of the thirty-eighth transistor 2512 is connected to the drain voltage source, a drain of the drain transistor is connected to the thirty-eighth capacitor, the drain transistor 2512 is connected to the drain source of the drain is connected to the drain source of the thirty-eighth capacitor, and the drain is connected to the drain source of the drain transistor junction drain source of the drain transistor, and the drain is connected to the twenty-eighth source is connected to the source, and source of the drain source is connected;
The twenty-fifth transistor 2503 has the same size as the twenty-sixth transistor 2504, the fourteenth resistor 2502 has the same resistance as the fifteenth resistor 2505, and the tenth capacitor 2501 has the same capacitance as the eleventh capacitor 2506.
The envelope detector 2500 is used for converting the one-time intermediate frequency signal and the two-time intermediate frequency signal into direct current components, wherein the level output by the output end OUT1 is positively correlated with the voltage of the input signal, and the level output by the output end OUT2 is more sensitive when the voltage of the input signal is smaller, and the level output by the output end OUT2 is negatively correlated with the voltage of the input signal, and the level output by the output end OUT2 is more sensitive when the voltage of the input signal is larger;
The ADC2600 includes two dc level input ports, a digital control port for switching the read port, and a digital bus output port, where the two dc level input ports are respectively connected to the output terminal OUT1 and the output terminal OUT2 of the envelope detector 2500, and the digital bus output port is connected to the third partial circuit 3000, where the level range of the ADC sampling is 0-1V, and the sampling precision is 10 bits;
The ADC2600 converts the input dc level into a digital signal, and outputs the digital signal to the third partial circuit 3000 through the bus, so that the digital control circuit can obtain the local oscillator leakage of the transmitter and the power of the image component, and perform automatic calibration according to the local oscillator leakage and the power of the image component.
Local oscillator leakage and image frequency generated by the I/Q mixer are coupled into RF signals at the output end of the transmitter and input into the detection circuit, the local oscillator and the image frequency are respectively converted into a double intermediate frequency and a double intermediate frequency through the self-mixer, filtered and amplified and then converted into direct current level, and the direct current level is transmitted to the third partial circuit after being sampled by the ADC.
The third partial circuit 3000 is a digital control circuit for automatically generating Verilog codes, and comprises a digital bus input port, a calibration signal input port, a calibration end signal output port, and four digital bus output ports, where the digital bus output ports are respectively connected with the first IDAC1001, the second IDAC1008, the third IDAC1009, and the fourth IDAC1016, and are used for controlling the current output by the DAC;
The signal flow process of this embodiment is:
The first part circuit 1000 inputs quadrature intermediate frequency signals provided for the outside, including IF i+, IF I-, if_q+, if_q-, and quadrature local oscillation signals including lo_i+, lo_i-, lo_q+, lo_q-, and outputs radio frequency differential signals including rf+ and RF-, which are amplified by a power amplifier and become single-ended radio frequency signals RF at a radio frequency output port, the second part circuit 2000 inputs radio frequency signals RF and outputs digital bus signals, the third part circuit 3000 inputs including digital bus signals from the second part circuit 2000 and a calibration start signal and outputs a calibration end signal and four digital bus outputs, the digital bus outputs being connected to the first IDAC1001, the second IDAC1008, the third IDAC1009, the fourth IDAC1016 in the first part circuit 1000, respectively, thereby forming a closed loop control loop.
The local oscillator leakage and I/Q imbalance calibration process in this embodiment is that, due to the difference in chip process manufacturing, the sizes of the transconductance stage transistors, that is, the tenth transistor 1004, the eleventh transistor 1005, the fourteenth transistor 1012, and the fifteenth transistor 1013 may be different, which may cause imbalance of the direct current of the transconductance stage transistors, and imbalance of the current of the transconductance stage transistors may cause that the local oscillator signal or the image frequency of the output port cannot be completely offset, one local oscillator signal or the image frequency output amplitude with larger current is larger, so as to generate larger local oscillator leakage or image frequency. In order to realize on-chip automation of the calibration process, the invention adds the local oscillator leakage and image frequency detection circuit at the output port of the transmitter, converts the components to be detected into digital signals and outputs the digital signals to the on-chip digital control circuit, and the digital control circuit obtains the IDAC control code when the local oscillator leakage and the image frequency are minimum in a traversing way after receiving the calibration starting signals, thereby realizing the calibration of the local oscillator leakage and the I/Q imbalance.
As shown in fig. 4, the control logic of the third partial circuit 3000 of the system in the present invention includes a main flow and three sub-flows, namely, sub-flow 3100a, sub-flow 3100b and sub-flow 3100c, wherein when the main flow starts automatic calibration, the system first executes step 3001, the third partial circuit 3000 receives a calibration signal from the calibration signal input port and enters into sub-flow 3100a, and in sub-flow 3100a, the system calibrates local oscillation leakage of path I, namely, calibrates the first IDAC1001, wherein the step of 3100a is consistent with 3100, the modified IDAC register is the control register corresponding to the first IDAC1001, and enters into sub-flow 3100b after the end;
In the sub-flow 3100, the circuit firstly enters a step 3101 to set the control register value of the corresponding IDAC to 0, then enters a step 3102 to add 1 to the register value, then enters a step 3103, a third partial circuit reads the values of the output end OUT1 and the output end OUT2 read by the ADC2600 through a digital bus input port and calculates the values to obtain OUT1-OUT2, then enters a step 3104, if the values of OUT1-OUT2 are smaller than the previous reading, the values of OUT1-OUT2 are stored, and a step 3105 is triggered, the current register value is stored, after the step 3104 is finished, the step 3106 is entered, whether the register value reaches the upper limit is judged, if the upper limit is not reached, the step 3102 is returned, if the upper limit is reached, the step 3107 is entered, the register is set to the optimal offset value obtained in the loop, and the sub-flow 3100 is ended;
In the sub-flow 3100b, the system calibrates local oscillation leakage of Q paths, that is, calibrates the fourth IDAC1016, wherein the step of 3100b is consistent with 3100, the modified IDAC register is a control register corresponding to the fourth IDAC1016, and enters the sub-flow 3100c after the end;
In the sub-process 3100c, the circuit performs calibration on the unbalance of two paths I, Q, namely, the first IDAC1001 and the second IDAC1008 are calibrated at the same time, at the moment, a step 3102 in the sub-process becomes to add 1 to the register values controlling the first IDAC1001 and the second IDAC1008 at the same time, namely, the difference value between the registers is kept constant, a step 3106 in the sub-process becomes to judge whether the value of the first IDAC1001 or the second IDAC1008 reaches the upper limit, if one of the values reaches the upper limit, a step 3107 is entered, the other steps are consistent, and the step 3002 is entered after the end, in the step 3002, since the calibration of local oscillation leakage and the calibration of the I/Q unbalance are mutually influenced, the step 3003 is entered when the value of the current register is the same as the value of the upper-round register, if the value is not the same, the calibration is not converged, the step 3004 is entered when the value is the same, the iteration number of times is judged to be reached, if the iteration number of the upper limit is not reached in the step 3003, the step 3100a is returned, and if the step 3004 is reached, the calibration signal is automatically completed through the end of the circuit in the step 3004;
The digital control circuit realizes automatic local oscillation leakage and I/Q imbalance calibration by automatically traversing the register value of the output current of the IDAC and combining the digital signal input by the detection circuit.
The invention adopts an I/Q frequency mixing architecture, and is provided with two mixers, namely an I-path mixer and a Q-path mixer, which are respectively used for inputting orthogonal intermediate frequency signals and orthogonal local oscillation signals, wherein one of two sidebands obtained by the I-path mixer and the Q-path mixer has the same phase, the other phase is opposite, the required sidebands are reserved finally, and the residual sidebands are counteracted, so that single-sided sideband frequency conversion is realized. The mixer output matching network realizes the sideband selection, specifically, the sidebands can be switched by changing the connection mode of the I-path mixer and the Q-path mixer output, wherein the positive end of the I-path output is connected with the positive end of the Q-path output, the negative end is connected with the negative end, the upper sidebands are selected, the positive end of the I-path output is connected with the negative end of the Q-path output, and the negative end is connected with the positive end, the lower sidebands are selected.
The invention adds a local oscillator leakage and I/Q imbalance calibration circuit based on the traditional frequency converter, namely a first partial circuit comprising a current type DAC, and adds a broadband local oscillator leakage and image frequency signal detection circuit and an on-chip digital control circuit, thus realizing signal reading and automatic calibration under the conditions of no need of external instruments such as an external vector network analyzer and manual adjustment, detecting the local oscillator leakage and image frequency signal output by a transmitter by using the on-chip circuit, and automatically adjusting the offset voltage of a transconductance stage of the frequency mixer to an optimal value by using the on-chip digital control circuit.
As shown in fig. 5, this is a comparison schematic diagram of the situations before and after the local oscillation leakage suppression calibration in the test of this example, where the abscissa in the figure is the intermediate frequency and the ordinate is the local oscillation leakage suppression ratio, and it can be seen from fig. 5 that in the range of the intermediate frequency signal being 2.4-7.5GHz, the local oscillation leakage suppression of the transmitter is improved by at least 20dBc after the automatic calibration, and in the required radio frequency range, the local oscillation leakage suppression ratio of the transmitter is greater than 40dBc.
As shown in fig. 6, this is a comparison schematic diagram of the situations before and after the image rejection calibration in the test of this example, the abscissa in fig. 6 is the intermediate frequency, and the ordinate is the image rejection ratio, and it can be seen from fig. 6 that in the range of the intermediate frequency signal being 2.4-7.5GHz, the image rejection of the transmitter is raised by at least 8dBc after the automatic calibration, and in the required radio frequency range, the image rejection ratio of the transmitter is greater than 40dBc.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
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| CN104158552A (en) * | 2014-08-01 | 2014-11-19 | 华为技术有限公司 | Zero intermediate frequency transmitter, receiver and related method and system |
| CN117155291A (en) * | 2023-09-14 | 2023-12-01 | 南京汇君半导体科技有限公司 | Broadband single-side-band up-converter capable of calibrating local oscillator leakage |
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| CN101964631B (en) * | 2010-09-15 | 2012-11-28 | 华东师范大学 | Improved double Gilbert structure radio-frequency orthogonal upper frequency mixer |
| US8724679B2 (en) * | 2012-04-09 | 2014-05-13 | Tensorcom, Inc. | Method and apparatus of transceiver calibration using substrate coupling |
| CN115412029A (en) * | 2021-05-28 | 2022-11-29 | 深圳市中兴微电子技术有限公司 | Mixer, Transceiver |
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| CN104158552A (en) * | 2014-08-01 | 2014-11-19 | 华为技术有限公司 | Zero intermediate frequency transmitter, receiver and related method and system |
| CN117155291A (en) * | 2023-09-14 | 2023-12-01 | 南京汇君半导体科技有限公司 | Broadband single-side-band up-converter capable of calibrating local oscillator leakage |
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