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CN119201816A - Multi-channel serial digital interface timing alignment adjustment method, device and equipment - Google Patents

Multi-channel serial digital interface timing alignment adjustment method, device and equipment Download PDF

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Publication number
CN119201816A
CN119201816A CN202310763251.4A CN202310763251A CN119201816A CN 119201816 A CN119201816 A CN 119201816A CN 202310763251 A CN202310763251 A CN 202310763251A CN 119201816 A CN119201816 A CN 119201816A
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China
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delay
channel
data
serial
signal
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徐栋
高加林
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Beijing Tebang Microelectronic Technology Co ltd
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Beijing Tebang Microelectronic Technology Co ltd
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Priority to CN202310763251.4A priority Critical patent/CN119201816A/en
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

本公开涉及一种多通道串行数字接口时序对齐调整方法、装置及设备，所述方法包括：通过确定所述第一通道的串行数字接口的时钟信号在所述延时单元的第一延时参数，确定当所述第二通道的数据能够被所述第一通道的串行数字接口的时钟信号正确采集时，所述第二通道的数据信号在所述延时单元的第二延时参数，设置所述第一通道在所述延时单元的延时参数为第一延时参数，设置所述第二通道在所述延时单元的延时参数为第二延时参数，可以使得多通道数据共用同一串行数字接口的时钟信号，且能够实现接收端组件准确同步采集发射端组件多个通道的数据，节约了接收端组件的IO资源，提高了扩展可能性、灵活性及可靠性。

The present disclosure relates to a method, device and equipment for adjusting the timing alignment of a multi-channel serial digital interface. The method comprises: determining a first delay parameter of a clock signal of a serial digital interface of a first channel in a delay unit, determining a second delay parameter of a data signal of the second channel in the delay unit when data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, setting the delay parameter of the first channel in the delay unit as a first delay parameter, and setting the delay parameter of the second channel in the delay unit as a second delay parameter, so that multi-channel data can share the clock signal of the same serial digital interface, and can realize accurate and synchronous collection of data of multiple channels of a transmitting end component by a receiving end component, saving IO resources of the receiving end component, and improving expansion possibility, flexibility and reliability.

Description

Multi-channel serial digital interface time sequence alignment adjustment method, device and equipment
Technical Field
The present disclosure relates to the field of integrated circuits, and in particular, to a method, an apparatus, and a device for adjusting time sequence alignment of a multi-channel serial digital interface.
Background
In the fields of communication, radar, software radio and the like, a receiving end component can receive serial data of a transmitting end component and process the serial data, in actual use, the transmitting end component can be multichannel, an Interface (IO) of the receiving end component is a precious resource, in order to save resources such as the receiving end component IO and the like, especially special clock IO resources, in many practical applications, multichannel serial digital interface data can share clock signals of the same channel, clock signals of the same channel are directly used for collecting data of other groups, time sequence errors of data transmission can be caused, if the same clock is adopted for sampling a plurality of groups of data with the same time delay, the time sequence window is far smaller than the time sequence window which is independently regulated for each group of data, even an effective time sequence window cannot be found, and the sampling system cannot work normally.
Disclosure of Invention
According to an aspect of the present disclosure, there is provided a method for adjusting timing alignment of a multi-channel serial digital interface, where the channels include a first channel and at least one second channel, and the multi-channel serial digital interface data share a clock signal of the same channel, and a delay unit is used to delay a serial digital interface clock and data respectively, and the method includes:
Determining a first delay parameter of a clock signal of a serial digital interface of the first channel in the delay unit;
Determining a second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly acquired by the clock signal of the serial digital interface of the first channel;
Setting the delay parameter of the first channel in the delay unit as a first delay parameter, and setting the delay parameter of the second channel in the delay unit as a second delay parameter.
In one possible implementation manner, the determining the first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit includes:
setting an initial delay parameter of the first channel;
Continuously collecting a conversion signal obtained by a conversion component in the delay unit, and increasing the delay parameter with a preset step length under the condition that the conversion signal is a first preset value or a second preset value, or recording the current delay parameter under the condition that the conversion signal is not the first preset value or the second preset value and is different from the previous conversion signal, and increasing the delay parameter with the preset step length;
And when the delay parameter reaches the maximum delay parameter, obtaining the first delay parameter by using the recorded delay parameters.
In one possible implementation manner, when the delay parameter reaches the maximum delay parameter, the obtaining the first delay parameter by using the recorded multiple delay parameters includes:
And taking the average value or the median of the plurality of delay parameters as the first delay parameter.
In one possible implementation manner, the determining the second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel includes:
setting an initial delay parameter of the second channel;
Continuously collecting a plurality of data output by the second channel in each period, if the plurality of data are not sampled correctly, increasing the delay parameter with a preset step length, or if the plurality of data are sampled correctly, recording the current delay parameter, and increasing the delay parameter with the preset step length;
And when the delay parameter reaches the maximum delay parameter, obtaining the second delay parameter by using the recorded delay parameters.
In a possible implementation manner, when the delay parameter reaches a maximum delay parameter, the obtaining the second delay parameter by using the recorded plurality of delay parameters includes:
and taking the average value or the median of the plurality of delay parameters as the second delay parameter.
In one possible embodiment, the method further comprises:
And dynamically adjusting delay parameters of the first channel and the second channel according to an alignment mode of the clock signal of the serial digital interface after delay of the first channel and the clock signal of the serial digital interface before delay and a conversion signal output by a conversion component in the delay unit.
In one possible implementation manner, the dynamically adjusting the delay parameters of the first channel and the second channel according to the alignment manner of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the delay unit includes:
collecting conversion signals for N times, wherein N is more than 1 and is an integer;
If the N conversion signals are all of a first preset value and the alignment mode is rising edge alignment, increasing delay parameters of the first channel and the second channel;
If the N conversion signals are all the first preset value and the alignment mode is falling edge alignment, reducing delay parameters of the first channel and the second channel;
if the N conversion signals are all of the second preset value and the alignment mode is rising edge alignment, reducing delay parameters of the first channel and the second channel;
If the N conversion signals are all the second preset value and the alignment mode is falling edge alignment, increasing delay parameters of the first channel and the second channel;
If at least one of the N converted signals has a value greater than a first preset value and less than a second preset value, the delay parameters of the first channel and the second channel are not changed.
In one possible implementation, the receiving end component delays the serial digital interface clock and the data respectively using a delay unit, where the delay unit includes:
The input signal delayer is used for receiving a clock signal or a data signal, delaying the clock signal or the data signal according to a set delay parameter, and outputting a delay clock signal and a delay data signal, wherein the delay parameter comprises the first delay parameter and the second delay parameter;
The serial-to-parallel converter is used for receiving the clock signal or the data signal, carrying out serial-to-parallel conversion on the clock signal or the data signal and outputting a conversion signal;
The frequency division module is used for dividing the clock signal, outputting a frequency division clock and providing a clock for the serial-parallel converter;
the bit clock alignment state machine is used for judging whether the clock signal is aligned with the delay clock signal according to the conversion signal obtained after the serial-parallel conversion of the clock signal;
the delay judging state machine is used for judging whether the current delay value can enable data to be correctly acquired according to the conversion signal obtained after the delay data signal is subjected to serial-parallel conversion;
The data alignment module is used for adjusting the dislocation between the converted signals after the serial-parallel conversion of the delay data signals, so that the boundaries of the converted signals are correctly identified;
Wherein the determining, when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel includes:
and in a test mode of the transmitting end assembly, determining a second delay parameter of the data signal of the second channel when the data of the second channel can be correctly acquired by the clock signal of the first channel serial digital interface.
In one possible embodiment, the first preset value is 0x00 and the second preset value is 0xFF.
According to an aspect of the present disclosure, there is provided a multi-channel serial digital interface timing alignment adjustment device, the channels including a first channel and at least one second channel, the multi-channel serial digital interface data sharing a clock signal of a same channel, the serial digital interface clock and the data being respectively delayed by a delay unit, the device comprising:
A first determining module, configured to determine a first delay parameter of a clock signal of a serial digital interface of the first channel in the delay unit;
A second determining module, configured to determine a second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel;
The setting module is used for setting the delay parameter of the first channel in the delay unit as a first delay parameter and setting the delay parameter of the second channel in the delay unit as a second delay parameter.
According to an aspect of the present disclosure, there is provided an electronic device including the multi-channel serial digital interface timing alignment adjustment apparatus.
According to an aspect of the present disclosure, there is provided a multi-channel serial digital interface timing alignment adjustment device, the channels including a first channel and at least one second channel, the multi-channel serial digital interface data sharing clock signals of the same channel, the serial digital interface clock and the data being respectively delayed using a delay unit, the device including a first delay unit, at least one second delay unit, the first delay unit and the second delay unit each including an input signal delayer, a serial-to-parallel converter, a bit clock alignment state machine, a data alignment module, and a data acquisition module, the first delay unit further including a frequency division module, the second delay unit further including a delay determination state machine, the first delay unit being configured to determine a first delay parameter of the clock signal of the serial digital interface of the first channel at the first delay unit, a preset second delay unit being configured to determine a second delay parameter of the data signal of the second channel at the second delay unit when the data of each second channel can be correctly acquired by the clock signal of the digital interface of the first channel,
The input signal delayer is used for receiving a clock signal or a data signal, delaying the clock signal or the data signal according to a set delay parameter, and outputting a delay clock signal and a delay data signal, wherein the delay parameter comprises the first delay parameter and the second delay parameter;
The serial-parallel converter is used for receiving the clock signal or the data signal, carrying out serial-parallel conversion on the clock signal or the data signal, and outputting a conversion signal;
The frequency division module is used for dividing the frequency of the clock signal, outputting a frequency division clock and providing a clock for the serial-parallel converter;
the bit clock alignment state machine is used for judging whether the clock signal is aligned with the delay clock signal according to the conversion signal obtained after the serial-parallel conversion of the clock signal;
The delay judging state machine is used for judging whether the current delay value can enable data to be correctly acquired according to the conversion signal obtained after the delay data signal is subjected to serial-parallel conversion;
The data alignment module is used for adjusting the dislocation between the converted signals after the serial-parallel conversion of the delay data signals, so that the boundaries of the converted signals are correctly identified;
the data acquisition module is used for acquiring data output by the serial-parallel converter.
In a possible implementation manner, the serial-to-parallel converter in the first delay unit includes a first serial-to-parallel converter, a second serial-to-parallel converter, and a third serial-to-parallel converter, where,
The data input of the input signal delay device is used for inputting the clock signal,
The delay parameter input end of the input signal delayer is connected with the output end of the bit clock alignment state machine to receive the delay parameter output by the bit clock alignment state machine,
The output end of the input signal delayer is connected with the first clock signal end of the first serial-to-parallel converter of the first delay unit, the first clock signal end of the second serial-to-parallel converter of the first delay unit, the first clock signal end of the third serial-to-parallel converter of the first delay unit and the input end of the frequency dividing module,
The output end of the frequency dividing module is connected with the second clock signal end of the first serial-parallel converter of the first delay unit, the second clock signal end of the second serial-parallel converter of the first delay unit and the second clock signal end of the third serial-parallel converter of the first delay unit,
The data input of the first serial-to-parallel converter of the first delay unit is arranged to receive the clock signal,
The output end of the first serial-parallel converter of the first delay unit is connected with the data input end of the bit clock alignment state machine,
The data input of the second serial-to-parallel converter of the first delay unit is for receiving a frame synchronization signal,
The output end of the second serial-parallel converter of the first delay unit is connected with the input end of the data alignment module,
The data input of the third serial-to-parallel converter of the first delay unit is arranged to receive a data signal,
The output end of the third serial-parallel converter of the first delay unit is connected with the input end of the data acquisition module.
In a possible implementation manner, the input signal delayer in the second delay unit comprises a first input signal delayer and a second input signal delayer, the serial-parallel converter in the second delay unit comprises a first serial-parallel converter and a second serial-parallel converter,
The data input of the first input signal delay is for receiving a frame synchronization signal,
The delay parameter input end of the first input signal delayer is connected with the output end of the delay judgment state machine and is used for receiving the delay parameter output by the delay judgment state machine,
The data output end of the first input signal delayer is connected with the data input end of the first serial-parallel converter of the second delay unit,
The data input of the second input signal delay is arranged to receive a data signal,
The delay parameter input end of the second input signal delayer is connected with the output end of the delay judgment state machine and is used for receiving the delay parameter output by the delay judgment state machine,
The data output end of the second input signal delayer is connected with the data input end of the second serial-parallel converter of the second delay unit,
The first clock signal end of the first serial-to-parallel converter of the second delay unit and the first clock signal end of the second serial-to-parallel converter of the second delay unit are connected with the output end of the input signal delay unit of the first delay unit,
The second clock signal end of the first serial-parallel converter of the second delay unit and the second clock signal end of the second serial-parallel converter of the second delay unit are connected with the output end of the frequency division module,
The output end of the first serial-parallel converter of the second delay unit is connected with the input end of the data alignment module,
The output end of the second serial-parallel converter of the second delay unit is connected with the input end of the data acquisition module and the input end of the delay judgment state machine.
In one possible implementation manner, the determining the first delay parameter of the clock signal of the serial digital interface of the first channel in the first delay unit includes:
Setting an initial delay parameter of an input signal delayer of the first delay unit;
Continuously collecting a conversion signal obtained by a preset serial-parallel converter in the first delay unit, and increasing the delay parameter by a preset step length under the condition that the conversion signal is a first preset value or a second preset value, or recording the current delay parameter under the condition that the conversion signal is not the first preset value or the second preset value and is different from the previous conversion signal, and increasing the delay parameter by the preset step length;
And when the delay parameter reaches the maximum delay parameter, obtaining the first delay parameter by using the recorded delay parameters.
In one possible implementation manner, the determining the second delay parameter of the second channel data signal in the second delay unit when the second channel data can be correctly collected by the clock signal of the serial digital interface of the first channel includes:
setting an initial delay parameter of an input signal delayer of the second delay unit;
Continuously collecting a plurality of data output by a preset serial-parallel converter of the second channel in each period, and if the plurality of data are not sampled correctly, increasing the delay parameter by a preset step length, or if the plurality of data are sampled correctly, recording the current delay parameter and increasing the delay parameter by the preset step length;
And when the delay parameter reaches the maximum delay parameter, obtaining the second delay parameter by using the recorded delay parameters.
In a possible embodiment, the device is further configured to:
and dynamically adjusting delay parameters of the first channel and the second channel according to an alignment mode of a clock signal of the serial digital interface after delay of the first channel and a clock signal of the serial digital interface before delay and a conversion signal output by a conversion component in a preset delay unit.
In a possible implementation manner, the dynamically adjusting the delay parameters of the first channel and the second channel according to the alignment manner of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the preset delay unit includes:
collecting conversion signals for N times, wherein N is more than 1 and is an integer;
If the N conversion signals are all of a first preset value and the alignment mode is rising edge alignment, increasing delay parameters of the first channel and the second channel;
If the N conversion signals are all the first preset value and the alignment mode is falling edge alignment, reducing delay parameters of the first channel and the second channel;
if the N conversion signals are all of the second preset value and the alignment mode is rising edge alignment, reducing delay parameters of the first channel and the second channel;
If the N conversion signals are all the second preset value and the alignment mode is falling edge alignment, increasing delay parameters of the first channel and the second channel;
If at least one of the N converted signals has a value greater than a first preset value and less than a second preset value, the delay parameters of the first channel and the second channel are not changed.
According to an aspect of the disclosure, an electronic device is provided, which comprises a processor and a memory for storing instructions executable by the processor, wherein the processor is configured to call the instructions stored by the memory to execute the multi-channel serial digital interface time sequence alignment adjustment method, and the processor comprises an FPGA or an ASIC.
According to an aspect of the present disclosure, there is provided a storage medium having stored thereon program instructions which, when executed by a processor, implement the above-described multi-channel serial digital interface timing alignment adjustment method.
According to the multi-channel serial digital interface time sequence alignment adjustment method, through determining the first delay parameter of the clock signal of the serial digital interface of the first channel in the time delay unit, when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel is determined to be the second delay parameter of the time delay unit, the delay parameter of the first channel in the time delay unit is set to be the first delay parameter, the delay parameter of the second channel in the time delay unit is set to be the second delay parameter, the problem that a DCO window is too small and time sequence errors are easy to occur can be solved, the fact that the multi-channel data share the clock signal of the same serial digital interface can be achieved, the data of a plurality of channels of transmitting end assemblies can be accurately and synchronously collected by a receiving end assembly, IO (input/output) resources of the receiving end assembly are saved, and the expansion possibility, flexibility and reliability are improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the technical aspects of the disclosure.
Fig. 1 shows a serial LVDS interface timing diagram of a common ADC digital IO output.
Fig. 2a shows a schematic diagram of a delay unit in a receiving-end assembly according to an embodiment of the present disclosure.
Fig. 2b shows a schematic diagram of a delay cell in an FPGA according to an embodiment of the disclosure.
Fig. 3 shows a flowchart of a multi-channel serial digital interface timing alignment adjustment method according to an embodiment of the present disclosure.
Fig. 4 shows a flowchart of a multi-channel serial digital interface timing alignment adjustment method according to an embodiment of the present disclosure.
Fig. 5 shows a schematic diagram of various delay cells according to an embodiment of the present disclosure.
Fig. 5a, 5b, 5c, 5d, 5e, 5f, 5g illustrate schematic connection relationships of various components of a delay unit according to an embodiment of the present disclosure.
Fig. 6a and 6B are schematic diagrams respectively illustrating adjustment of a first delay parameter of a channel a and a second delay parameter of a channel B by using the multi-channel serial digital interface timing alignment adjustment method according to the embodiments of the present disclosure.
Fig. 7 shows a schematic diagram of dynamic adjustment of delay parameters according to an embodiment of the disclosure.
Fig. 8 shows a block diagram of a multi-channel serial digital interface timing alignment adjustment device according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
In the description of the present disclosure, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the present disclosure and simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be configured and operated in a particular orientation, and thus should not be construed as limiting the present disclosure.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the present disclosure, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed, mechanically connected, electrically connected, directly connected, indirectly connected via an intervening medium, or in communication or in interaction between two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
The term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean that a exists alone, while a and B exist together, and B exists alone. In addition, the term "at least one" herein means any one of a plurality or any combination of at least two of a plurality, for example, including at least one of A, B, C, may mean including any one or more elements selected from the group consisting of A, B and C.
Furthermore, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
It should be understood that the specific types of the receiving end component and the transmitting end component in the embodiments of the present disclosure are not limited, those skilled in the art may select the specific types according to practical situations and needs, and the receiving end component may be an FPGA, an ASIC chip, or the like, and the transmitting end component may be an ADC, or may be a digital signal source, or the like, for example, a quantized result of TRANSCIEVER, or even a digital chip, so long as the transmitting end component may send a serial digital code stream, and the receiving end component may receive and process an LVDS code stream sent by the transmitting end component. For convenience of description, the embodiments of the present disclosure will be described by taking an ADC (Analog-to-digital Converter) as a transmitting end component and an FPGA as a receiving end component.
Firstly, the related technology and the problems thereof are introduced by taking an ADC as a transmitting end component and an FPGA as a receiving end component, and at present, the multi-channel, high-speed and high-precision ADC is widely applied to the fields of communication, radar, software radio and the like. At present, a serial LVDS (Low-Voltage DIFFERENTIAL SIGNALING) interface is mainly adopted as a digital end output interface by a mainstream high-speed multichannel ADC, and the interface has the characteristics of Low power consumption, strong anti-interference capability of differential signals, ultrahigh transmission speed and the like, and can effectively reduce the number of I/O devices.
Referring to fig. 1, fig. 1 shows a serial LVDS interface timing diagram of a common ADC digital IO output.
The serial LVDS interface timing of a common ADC digital IO output is shown in fig. 1. In fig. 1, ENC -/ENC+ represents an ADC input sampling clock to drive an ADC sampling circuit, DCO -/DCO+ represents a digital LVDS interface clock, and for the DDR sampling mode, the rising and falling edges of the sampling clock DCO align with the center of the data, facilitating the collection of FPGA (Field Programmable GATE ARRAY ), and FR -/FR+ represents a frame synchronization signal to indicate which bits are spliced together into a complete data. FR rising edge is aligned with Data edge, out#a -/A+ represents Data channel a, such as ADC16bit even bit serial Data, out#b -/B+ represents Data channel B, such as ADC16bit odd bit serial Data, serial LVDS transmitting end, clock DCO is aligned with center of Data, and Data is aligned with FR, and as Data rate increases, sampling window of Data becomes smaller. Taking the LTM9011 of ADI corporation as an example, the 16-bit ADC has a data interface rate of 1Gbps and a data period of 1ns at a sampling rate of 125 MSPS.
It is known to those skilled in the art that even in the case of a hardware PCB with strict equal-length design, since paths traveled by DCO and Data inside the FPGA are different, it is difficult to guarantee a phase relationship among DCO, data and FR in the FPGA sampling circuit, and it is difficult to guarantee a sufficient timing sampling window, thereby causing generation of errors. In addition, with the improvement of the chip integration level, a plurality of groups of DCO/FR/Data occur, and each group of FR/Data is collected by an independent DCO. However, in some miniaturized applications, a small-package-size FPGA chip is required, and the IO of the FPGA is a precious resource, so that in order to save resources such as FPGA IO, especially dedicated clock IO resources, in many practical applications, multiple groups of Data/FR often share a set of DCO clocks. In this time, due to the timing deviation between the DCOs and the Data/FR of other groups, the direct use of one DCO to directly collect the FR/Data of other groups may cause the timing error of Data transmission, and the related technology has a mode of equally delaying multiple groups of Data, however, equally delaying two or more groups of Data may cause that the timing window is much smaller than the delay of each group of Data alone, even an effective timing window cannot be found, which results in the sampling system not working normally.
As described above, in the FPGA sampling circuit, it is difficult to ensure the phase relationship among DCO, data and FR, and it is difficult to ensure enough time sequence sampling windows, so that the error code is generated, for this reason, the FPGA delay unit may be used to perform delay compensation on the clock path, so as to solve the problem of time sequence reduction and error code caused by the internal wiring path of the FPGA, and of course, the specific implementation manner of the delay unit is not limited, and for different FPGAs, the implementation manner of the delay unit may be different, and those skilled in the art may adopt appropriate technical means according to actual situations and needs.
Referring to fig. 2a, fig. 2a is a schematic diagram illustrating a delay unit in a receiving-end assembly according to an embodiment of the disclosure.
In one possible implementation, as shown in fig. 2a, the delay unit may comprise an input signal delay, a serial-to-parallel converter, a bit clock alignment state machine, a frequency division module, wherein,
The input signal delayer is used for receiving a clock signal or a data signal, delaying the clock signal or the data signal according to a set delay parameter, and outputting a delay clock signal and a delay data signal, wherein the delay parameter comprises the first delay parameter and the second delay parameter;
The serial-parallel converter is used for receiving the clock signal or the data signal, carrying out serial-parallel conversion on the clock signal or the data signal, and outputting a conversion signal;
The frequency division module is used for dividing the frequency of the clock signal, outputting a frequency division clock and providing a clock for the serial-parallel converter;
and the bit clock alignment state machine is used for judging whether the clock signal is aligned with the delay clock signal according to the conversion signal obtained after the serial-parallel conversion of the clock signal.
Of course, the delay unit may further include other components, which are not limited to the embodiment of the disclosure, and may be set by those skilled in the art according to actual situations and needs, and the number and specific implementation manner of each component may also be set according to actual situations and needs.
An exemplary description of delay cells in an FPGA is provided below.
Referring to fig. 2b, fig. 2b is a schematic diagram illustrating a delay unit in a receiving-end component (e.g., FPGA) according to an embodiment of the disclosure.
In a possible embodiment, as shown in fig. 2b, the delay unit may comprise:
A differential input buffer IBUFDS for converting a differential signal including a clock signal (DCLK), a data signal into a single-ended signal;
An input signal delayer IDELAYE, connected to the differential input buffer IBUFDS, for delaying the single-ended signal according to a set delay parameter (such as delay time), where the input signal delayer IDELAYE includes a signal input terminal IDATAIN for receiving the single-ended signal output by the differential input buffer IBUFDS;
the I/O clock buffer IBUFIO and the local clock buffer BUFR are connected to the signal output terminal DATAOUT of the input signal delay IDELAYE, and are respectively used for outputting an I/O clock signal CLK and a local clock signal CLKDIV according to the delayed clock signal (IntBitClk);
The serial-to-parallel converter ISERDESE2 is configured to receive the single-ended signal (e.g., the input end D is configured to receive the single-ended clock signal BitClk) and the I/O clock signal CLK, perform serial-to-parallel conversion on the single-ended signal, and output the converted signal through a plurality of output ends (Q1-Q8) of the serial-to-parallel converter ISERDESE2, where the I/O clock signal CLK may be used as a sampling clock of the serial-to-parallel converter ISERDESE 2;
A Bit Clock alignment state machine PASM (Bit Clock PHASE ALIGNMENT STATE MACHINE) for determining whether the single-ended signal is aligned with the I/O Clock signal CLK according to the transition signal.
The input signal delayer IDELAYE2, the serial-to-parallel converter ISERDESE2, and the bit clock alignment state machine PASM are also configured to receive the local clock signal CLKDIV.
For example, as shown in fig. 2b, before the input signal delayer IDELAYE, a differential input buffer IBUFDS may be provided to convert the differential signal into a single-ended signal, and the frequency dividing module in fig. 2a may include an I/O clock buffer IBUFIO and a local clock buffer BUFR respectively for outputting the I/O clock signal CLK and the local clock signal CLKDIV according to the delayed clock signal (IntBitClk), which may, of course, be implemented by other embodiments, which are not limited to the embodiments of the disclosure.
The specific implementation manners of the differential input buffer IBUFDS, the input signal delayer IDELAYE2, the I/O clock buffer IBUFIO, the local clock buffer BUFR, the serial-to-parallel converter ISERDESE2, and the bit clock alignment state machine PASM in the embodiments of the present disclosure are not limited, and those skilled in the art may implement the embodiments by using appropriate technical means according to actual situations and needs, and exemplary those skilled in the art may implement the embodiments by using the differential input buffer IBUFDS, the input signal delayer IDELAYE, the I/O clock buffer IBUFIO, the local clock buffer BUFR, the serial-to-parallel converter ISERDESE, and the bit clock alignment state machine PASM that are mature in the related art.
Illustratively, as shown in fig. 2b, both the clock signal and the data signal input to the FPGA are converted from differential signals to single-ended signals through the differential input buffer IBUFDS, so that the edges of the single-ended clock signal Bitclk after the clock signal (DCLK) passes through the differential input buffer IBUFDS are aligned with the signal centers after the data signal passes through the differential input buffer IBUFDS. Therefore, only by controlling the delay parameters of the input signal delayer IDELAYE, the clock I/O clock signal CLK and the single-ended clock signal Bitclk after passing through the input signal delayer IDELAYE and the I/O clock buffer IBUFIO are aligned, so that the delays of the I/O clock buffer IBUFIO, the local clock buffer BUFR and the network (net) are eliminated, and the delay equality is realized. The I/O clock signal CLK may be used as a sampling clock of the serial-to-parallel converter ISERDESE (e.g., may be a dedicated serial-to-parallel converter of the FPGA, such as ISERDES (Input SERializer DESerializer)), when the I/O clock signal CLK collects a rising edge or a falling edge of the single-ended clock signal Bitclk, the serial-to-parallel converter ISERDESE2 may output a continuously variable value, which indicates that the I/O clock signal CLK is aligned with the single-ended clock signal BitClk, and when the serial-to-parallel converter ISERDESE outputs a value of 0xFF or 0x00, which indicates that the edges of the I/O clock signal CLK are not collected with the edges of the single-ended clock signal BitClk, by the above method, the embodiments of the disclosure may solve the problem of Data transmission of the same set of DCO/FR/Data.
However, since the delay unit of the FPGA cannot perform multiple different delays on one DCO, the above method cannot cope with the case of multiple sets of DCO/FR/Data, and for this reason, the embodiment of the disclosure may perform equal delay on two sets of Data to cope with the case of multiple sets of DCO/FR/Data, taking a chip with 2 sets of serial LVDS outputs, each set including independent DCO/FR/Data as an example, many applications use 1 DCO common to two sets of Data/FR due to IO limitation, especially clock IO resource limitation.
Illustratively, since the DCO cannot drive two sets of delay cells inside the FPGA, a scheme of the DCO after 1-way delay is common to both sets of Data/FR can be used. Exemplary window-adjusting specific processes include:
Step 1, after power-up, configuring an ADC into a test mode (Testmode modes) through a register access interface, and configuring digital output into an increment number or a decrement number;
Step 2, setting delay parameters of the input signal delayer IDELAYE (according to different time sequence parameters, the delay parameters are different values n of 0-31), wherein it should be noted that the delay parameter ranges of different FPGAs are different, and specific data values can refer to description documents of delay resources of corresponding FPGAs;
Step 3, waiting for the completion of adjustment of the data realignment module, wherein the data realignment module is used for realizing boundary alignment of parallel data, for example, 8-bit data input in serial from outside can obtain 8-bit parallel data after serial-parallel conversion, but the parallel data may have dislocation between front and back 8-bit data, which is unrecognizable by serial-parallel conversion, so that the required parallel data boundary can be found through the data realignment module, and of course, the specific implementation mode of the data realignment module in the embodiment of the disclosure is not limited, and the specific implementation mode of the data realignment module can be realized through related technologies by a person skilled in the art;
Step 4, when the delay is N, recording continuous N data (N is 16384 for example) output by each group of channels, and if the N data of each group are all incremental data, N is an effective window delay value at the moment;
step 5, recording the effective values of all n in the delay parameter range (such as 0-31), if a plurality of n are effective values, taking the intermediate value m as the final delay value;
and 6, configuring m as a delay value of the input signal delayer IDELAYE, exiting Testmode mode by the ADC, entering a normal working mode, and completing window adjustment operation.
However, when the two sets of data are equally delayed, the time sequence window is much smaller than the time sequence window adjusted independently for each set of data, even the effective time sequence window cannot be found, and the sampling system cannot work normally, therefore, the multi-channel serial digital interface time sequence alignment adjustment method provided by the embodiment of the disclosure determines that when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel by determining the first time delay parameter of the clock signal of the serial digital interface of the first channel, the data signal of the second channel is in the second delay parameter of the delay unit, the delay parameter of the first channel in the delay unit is set as the first delay parameter, the delay parameter of the second channel in the delay unit is set as the second delay parameter, the problem that a DCO window is too small and time sequence errors are easy to occur can be solved, the multi-channel data can share the clock signal of the same serial digital interface, the receiving end component can accurately and synchronously acquire the data of a plurality of channels of the transmitting end component, IO resources of the receiving end component are saved, and the expansion possibility, flexibility and reliability are improved.
Referring to fig. 3, fig. 3 is a flowchart illustrating a method for adjusting the timing alignment of a multi-channel serial digital interface according to an embodiment of the disclosure.
The channels include a first channel and at least one second channel, the serial digital interface data of the multiple channels share the clock signal of the same channel, and a delay unit (for example, may be a receiving end component such as an FPGA delay unit) is used to delay the serial digital interface clock and the data (for example, may be from an original transmitting end component such as an ADC) respectively, as shown in fig. 3, and the method includes:
Step S11, determining a first delay parameter of a clock signal of a serial digital interface of the first channel in the delay unit;
Step S12, determining a second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel;
Step S13, setting the delay parameter of the first channel in the delay unit as a first delay parameter, and setting the delay parameter of the second channel in the delay unit as a second delay parameter.
It should be understood that different channels of the transmitting end assembly (e.g., ADC) may correspond to different delay parameters, so that after the ADC enters the normal operation mode, the receiving end assembly (e.g., FPGA) can accurately and synchronously collect the data of each channel of the ADC.
For example, when the center position of the data signal of the second channel is aligned with the edge of the clock signal of the first channel, the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, and of course, the specific manner of determining that the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel is not limited, and those skilled in the art can determine in a suitable manner according to the actual situation and needs.
The level standard of the serial digital interface is not limited in the embodiments of the present disclosure, and a person skilled in the art may set the level standard according to the actual situation and needs, and the serial digital interface may be a digital LVDS interface or an interface of other level standards, and the serial digital interface is hereinafter described as an example of the digital LVDS interface.
In the embodiment of the present disclosure, the specific implementation manner of determining the first delay parameter of the delay unit by the clock signal of the serial digital interface of the first channel in step S11 is not limited, and a person skilled in the art may adopt a suitable technical means according to the actual situation and needs, and the following is described in an exemplary manner.
Referring to fig. 4, fig. 4 is a flowchart illustrating a method for adjusting the timing alignment of a multi-channel serial digital interface according to an embodiment of the disclosure.
In one possible implementation manner, as shown in fig. 4, step S11 of determining a first delay parameter of a clock signal of the serial digital interface of the first channel in the delay unit may include:
Step S111, setting an initial delay parameter of the first channel, for example, the delay parameter of the input signal delayer IDELAYE of the first channel may be set as the initial delay parameter;
Step S112, continuously collecting a conversion signal obtained by a conversion component in the delay unit, and increasing the delay parameter with a preset step length when the conversion signal is a first preset value or a second preset value, or recording a current delay parameter and increasing the delay parameter with the preset step length when the conversion signal is not the first preset value or the second preset value and is different from a previous conversion signal, wherein the conversion component can continuously collect the conversion signal by the bit clock alignment state machine PASM, for example, through the bit clock alignment state machine PASM, and increasing the delay parameter with a preset step length when the conversion signal is the first preset value or the second preset value, or recording a current delay parameter and increasing the delay parameter with the preset step length when the conversion signal is not the first preset value or the second preset value and is different from a previous conversion signal;
and step S113, when the delay parameter reaches the maximum delay parameter, obtaining the first delay parameter by using the recorded delay parameters.
In the embodiment of the disclosure, the delay parameter of the input signal delayer IDELAYE of the first channel is set as an initial delay parameter, the conversion signal is continuously collected by the bit clock alignment state machine PASM, and the delay parameter is increased by a preset step length when the conversion signal is a first preset value or a second preset value, or the current delay parameter is recorded and the delay parameter is increased by the preset step length when the conversion signal is not the first preset value or the second preset value and is different from the previous conversion signal, and when the delay parameter reaches the maximum delay parameter, the first delay parameter can be quickly obtained by using the recorded delay parameters so as to set the delay parameter of the delay unit of the first channel.
For example, the initial delay parameter may be, for example, 0, the first preset value may be, for example, 0x00, the second preset value may be, for example, 0xFF, the preset step size may be, for example, 1, the maximum delay parameter may be, for example, 31, the present disclosure embodiment may output a continuously variable value at the serial-to-parallel converter ISERDESE2 (the converted signal is not the first preset value or the second preset value and is different from the previous converted signal), determine that the acquired data has a metastable state, indicate that the I/O clock signal CLK is already aligned with the single-ended clock signal BitClk, and thus record the current delay parameter, and increase the delay parameter by the preset step size, and when the value output by the serial-to-parallel converter ISERDESE2 is, is 0xFF or 0x00 (the converted signal is the first preset value or the second preset value), indicate that the I/O clock signal edge is not acquired, i.e. aligned, and thus, indicate that the edge of the single-ended clock signal BitClk is not acquired, and thus the delay parameter is not aligned, and thus, the present disclosure embodiment may be implemented to quickly record whether the delay parameter is increased.
Illustratively, as shown in FIG. 2b, SERDESE serial-parallel conversion as an alignment principle may be described as that the I/O clock signal CLK is a delayed clock through IDELAY2, bitCLK is a target alignment clock at the same frequency as the I/O clock signal CLK, and the final purpose is to align the CLK clock with BitClk. The alignment is achieved by delaying CLK by IDELAY 2. The alignment is determined by taking the I/O clock signal CLK as the capture clock for ISERDESE and BitClk as the input signal for ISERDESE, e.g., taking the rising edge of the I/O clock signal CLK as BitCLK, and taking 8 times as the output value for ISERDESE2 (8 bits in parallel), wherein 0x00 is output if the I/O clock signal CLK is at BitCLK low level, and 0xFF is output if the I/O clock signal CLK is at BitCLK high level, both of these 2 cases indicating no alignment.
Of course, the specific size of the above parameters is not limited in the embodiments of the present disclosure, and specific values of the above parameters may be different for different FPGAs or different receiving end assemblies, and may be set by those skilled in the art according to actual situations and needs.
For example, referring to fig. 2b together, for the first channel, the initial delay parameter of the input signal delayer IDELAYE may be set to 0, the converted signals output by the serial-to-parallel converter ISERDESE2 are continuously collected by the bit clock alignment state machine PASM and the state of each converted signal is determined, where the delay parameter is added to 1 if the converted signal is 0x00 or 0xFF, or the current delay parameter is recorded if the converted signal is not 0x00 or 0xFF and is different from the previous converted signal, and the delay parameter is added to 1 until the delay parameter accumulation reaches or exceeds the maximum delay parameter, so that the recorded delay parameters may be obtained.
For example, the delay parameter may be recorded in a storage module, which in one example may include a computer-readable storage medium, which may be a tangible device that may hold and store instructions for use by the instruction execution device. The storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of a storage medium include, by way of non-exhaustive list, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a floppy disk, a mechanical encoding device, punch cards or in-groove protrusion structures having instructions stored thereon, and any suitable combination of the foregoing. A storage medium as used herein is not to be construed as a transitory signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a pulse of light through a fiber optic cable), or an electrical signal transmitted through an electrical wire.
In a possible implementation manner, when the delay parameter reaches the maximum delay parameter, step S113 obtains the first delay parameter by using the recorded multiple delay parameters, and may include:
And taking the average value or the median of the plurality of delay parameters as the first delay parameter.
The embodiment of the disclosure does not limit the working mode of the ADC when determining the first delay parameter, and the working mode of the ADC may be a test mode or a normal working mode when determining the first delay parameter.
In the embodiment of the disclosure, when it is determined in step S12 that the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, a specific implementation manner of the second delay parameter of the delay unit for the data signal of the second channel is not limited, and a person skilled in the art may adopt a suitable technical means according to actual situations and needs, and the following description is given by way of example.
In a possible implementation manner, as shown in fig. 4, step S12 determines that when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the second delay parameter of the data signal of the second channel in the delay unit may include:
Step S121, setting an initial delay parameter of the second channel, for example, setting a delay parameter of the input signal delayer IDELAYE2 of the second channel as the initial delay parameter;
Step S122, continuously collecting a plurality of data output by the second channel in each period, if the plurality of data are not sampled correctly, increasing the delay parameter with a preset step length, or if the plurality of data are sampled correctly, recording the current delay parameter, and increasing the delay parameter with the preset step length;
and step S123, when the delay parameter reaches the maximum delay parameter, obtaining the second delay parameter by using the recorded delay parameters.
In the embodiment of the disclosure, the delay parameter of the input signal delayer IDELAYE of the second channel is set as an initial delay parameter in the test mode of the ADC, and a plurality of data output by the second channel are continuously collected in each period, if the plurality of data are not sampled correctly, the delay parameter is increased by a preset step length, or if the plurality of data are sampled correctly, the current delay parameter is recorded, and the delay parameter is increased by the preset step length, and when the delay parameter reaches the maximum delay parameter, the second delay parameter can be obtained rapidly by using the recorded plurality of delay parameters, so as to set the delay parameter of the delay unit of the second channel.
Of course, the above determination of increasing data is exemplary, in other examples, the data may be decreasing data, or may change according to a certain rule, so as to determine whether the current delay value enables the FPGA to correctly collect the ADC data, so that when the plurality of data is not increasing data, decreasing data, or other data that changes according to a certain rule, it may be determined that the plurality of data is not correctly sampled, and conversely, when the plurality of data is increasing data, decreasing data, or other data that changes according to a certain rule, it may be determined that the plurality of data is correctly sampled.
For example, in the case of obtaining the first delay parameter of the first channel, the embodiment of the disclosure may fix the first delay parameter of the first channel, determine the second delay parameter of the second channel, for example, the first channel uses the delayed DCO as the sampling clock, because the DCO is already aligned with the data of the first channel, the delay value of the DCO cannot be adjusted under the constraint that the input signal delayer IDELAYE2 can only be driven by one IO, and for the data of the second channel, in the case that the DCO clock cannot adjust the delay, the embodiment of the disclosure adds a delay adjusting function of the delay unit on each data of the second channel, and since the delayed data is aligned with the DCO of the first channel, the DCO of the first channel and the delayed DCO can be judged whether to be aligned or not by the serial-parallel converter ISERDESE, the delay of the DCO can be dynamically adjusted, and the time remains aligned. Meanwhile, because the environments of the first channel and the second channel are the same, the change trend of the electrical parameters is the same, and thus the delay value of the data of the second channel is also adjusted in the same direction, so as to finish the dynamic alignment of the data of the second channel.
In a possible implementation manner, when the delay parameter reaches the maximum delay parameter, obtaining the second delay parameter by using the recorded multiple delay parameters may include:
and taking the average value or the median of the plurality of delay parameters as the second delay parameter.
For example, referring to fig. 2b together, for the second channel, the initial delay parameter of the input signal delayer IDELAYE may be set to 0, and the recorded plurality of delay parameters may be obtained by continuously collecting the plurality of data (such as 16384) output by the second channel in each period (continuous time period), if the plurality of data is not correctly sampled, the delay parameter is added to 1, or if the plurality of data is correctly sampled, the current delay parameter is recorded, and the delay parameter is added to 1, until the delay parameter accumulation reaches or exceeds the maximum delay parameter.
After the first delay parameter and the second delay parameter are set, the normal working mode needs to be jumped out of the testmode, and the time sequence allowance cannot be detected in real time in the normal sampling mode of the ADC, so that window cannot be automatically adjusted according to external environment changes (such as high temperature, low temperature and the like), and the method has a great hidden trouble in severe environment application.
The number of channels is not limited in the embodiments of the present disclosure, and those skilled in the art may configure delay parameters of any number of channels according to actual situations and needs.
Referring to fig. 5, fig. 5 shows a schematic diagram of various delay cells according to an embodiment of the disclosure.
In one example, as shown in fig. 5, the embodiment of the disclosure may configure delay parameters of each delay unit of channels 0 to N, where N may be an integer greater than 1.
In one example, as shown in fig. 5, the multi-channel serial digital interface timing alignment adjustment device, where the channels include a first channel (channel 0 in fig. 5) and at least one second channel (channel N in fig. 5), the multi-channel serial digital interface data share a clock signal of a same channel, the serial digital interface clock and the data are respectively delayed by using a delay unit, the device includes a first delay unit (corresponding to channel 0 in fig. 5) and at least one second delay unit (corresponding to channel N in fig. 5), the first delay unit and the second delay unit each include an input signal delayer, a serial-to-parallel converter, a bit clock alignment state machine, a data alignment module, and a data acquisition module, the first delay unit further includes a delay judgment state machine, the first delay unit is used to determine a first delay parameter of the clock signal of the serial digital interface of the first channel at the first delay unit, each second delay unit is used to determine a second delay parameter of the serial digital interface of the second channel when the serial digital interface of each second channel is capable of being correctly delayed by the second delay unit of the serial digital interface data of the second channel at the second delay unit,
The input signal delayer is used for receiving a clock signal or a data signal, delaying the clock signal or the data signal according to a set delay parameter, and outputting a delay clock signal and a delay data signal, wherein the delay parameter comprises the first delay parameter and the second delay parameter;
The serial-parallel converter is used for receiving the clock signal or the data signal, carrying out serial-parallel conversion on the clock signal or the data signal, and outputting a conversion signal;
The frequency division module is used for dividing the frequency of the clock signal, outputting a frequency division clock and providing a clock for the serial-parallel converter;
the bit clock alignment state machine is used for judging whether the clock signal is aligned with the delay clock signal according to the conversion signal obtained after the serial-parallel conversion of the clock signal;
The delay judging state machine is used for judging whether the current delay value can enable data to be correctly acquired according to the conversion signal obtained after the delay data signal is subjected to serial-parallel conversion;
The data alignment module is used for adjusting the dislocation between the converted signals after the serial-parallel conversion of the delay data signals, so that the boundaries of the converted signals are correctly identified;
the data acquisition module is used for acquiring data output by the serial-parallel converter.
According to the multi-channel serial digital interface time sequence alignment adjustment device, through determining the first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit, when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel is determined to be the second delay parameter of the delay unit, the delay parameter of the first channel in the delay unit is set to be the first delay parameter, the delay parameter of the second channel in the delay unit is set to be the second delay parameter, the problem that a DCO window is too small and time sequence errors are easy to occur can be solved, the clock signal of the same serial digital interface can be shared by multi-channel data, the data of a plurality of channels of transmitting end assemblies can be accurately and synchronously collected by the receiving end assemblies, IO (input/output) resources of the receiving end assemblies are saved, and the expansion possibility, flexibility and reliability are improved.
In one possible implementation, as shown in fig. 5, the serial-to-parallel converter in the first delay unit includes a first serial-to-parallel converter, a second serial-to-parallel converter, and a third serial-to-parallel converter, where,
The data input IDATAIN of the input signal delayer is used for inputting the clock signal DCO Ch0,
The Delay parameter input CNTVALUEIN of the input signal delayer is connected to the output delay_value of the bit clock alignment state machine to receive the Delay parameter delay_ch0 output by the bit clock alignment state machine,
The output end DATAOUT of the input signal delayer is connected with the first clock signal end CLK of the first serial-to-parallel converter of the first delay unit, the first clock signal end CLK of the second serial-to-parallel converter of the first delay unit, the first clock signal end CLK of the third serial-to-parallel converter of the first delay unit and the input end of the frequency dividing module,
The output end of the frequency dividing module is connected to the second clock signal end CLKDIV of the first serial-to-parallel converter of the first delay unit, the second clock signal end CLKDIV of the second serial-to-parallel converter of the first delay unit, the second clock signal end CLKDIV of the third serial-to-parallel converter of the first delay unit,
The data input D of the first serial-to-parallel converter of the first delay unit is arranged to receive the clock signal DCO Dh0,
The output Q of the first serial-to-parallel converter of the first delay unit is connected to the data input data of the bit clock alignment state machine,
The data input D of the second serial-to-parallel converter of the first delay unit is arranged to receive a frame synchronization signal FR Ch0,
The output end Q of the second serial-parallel converter of the first delay unit is connected with the input end of the data alignment module,
The data input D of the third serial-to-parallel converter of the first delay unit is arranged to receive a data signal,
The output end Q of the third serial-parallel converter of the first delay unit is connected with the input end data of the data acquisition module.
In one possible implementation, as shown in fig. 5, the input signal delayer in the second delay unit includes a first input signal delayer and a second input signal delayer, the serial-to-parallel converter in the second delay unit includes a first serial-to-parallel converter and a second serial-to-parallel converter,
The data input IDATAIN of the first input signal delay is for receiving the frame synchronization signal FR Ch0,
The Delay parameter input end CNTVALUEIN of the first input signal delayer is connected to the output end delay_value of the Delay judgment state machine, and is used for receiving the Delay parameter delay_chn output by the Delay judgment state machine,
The data output terminal DATAOUT of the first input signal delay is connected to the data input terminal D of the first serial-to-parallel converter of the second delay unit,
The data input IDATAIN of the second input signal delay is for receiving the data signal data0 ChN,
The Delay parameter input end CNTVALUEIN of the second input signal delayer is connected to the output end delay_value of the Delay judgment state machine, and is used for receiving the Delay parameter delay_chn output by the Delay judgment state machine,
The data output terminal DATAOUT of the second input signal delay is connected to the data input terminal D of the second serial-to-parallel converter of the second delay cell,
The first clock signal end CLK of the first serial-to-parallel converter of the second delay unit and the first clock signal end CLK of the second serial-to-parallel converter of the second delay unit are connected to the output end DATAOUT of the input signal delay unit of the first delay unit,
The second clock signal end CLKDIV of the first serial-to-parallel converter of the second delay unit and the second clock signal end CLKDIV of the second serial-to-parallel converter of the second delay unit are connected to the output end of the frequency division module,
The output end Q of the first serial-parallel converter of the second delay unit is connected with the input end of the data alignment module,
And the output end Q of the second serial-parallel converter of the second delay unit is connected with the input end of the data acquisition module and the input end of the delay judgment state machine.
In one example, as shown in fig. 5, the output of the data alignment module in each channel may be connected to the input of the data acquisition module, although for different types of FPGAs, the output of the data alignment module may be connected to different ports, for example, using serial-to-parallel converters ISERDES, bitslip in a 7-series FPGA to the bitslip input pins of serial-to-parallel converter ISERDES2, and for example, using serial-to-parallel converter ISERDES3 in a Ultrascale-series FPGA, where serial-to-parallel converter ISERDES3 has no bitslip input pins, it is necessary to direct bitslip to the data acquisition module, and a shift function is implemented in the data acquisition module, and for signals bitslip output by the output of the data alignment module, one skilled in the art may choose to connect to different pins depending on the particular FPGA.
In one possible implementation manner, the determining the first delay parameter of the clock signal of the serial digital interface of the first channel in the first delay unit may include:
Setting an initial delay parameter of an input signal delayer of the first delay unit;
The method includes continuously collecting a conversion signal obtained by a preset serial-to-parallel converter in the first delay unit, and increasing the delay parameter with a preset step length when the conversion signal is a first preset value or a second preset value, or recording a current delay parameter and increasing the delay parameter with the preset step length when the conversion signal is not the first preset value or the second preset value and is different from a previous conversion signal, wherein the preset serial-to-parallel converter may be an exemplary serial-to-parallel converter in which the data input end D receives the clock signal dc0_ch0, for example, a first serial-to-parallel converter of the channel 0 in fig. 5, and of course, in other embodiments, the preset serial-to-parallel converter may be set according to actual situations and needs, and the embodiment of the disclosure is not limited.
And when the delay parameter reaches the maximum delay parameter, obtaining the first delay parameter by using the recorded delay parameters.
In one possible implementation manner, the determining the second delay parameter of the second channel data signal in the second delay unit when the second channel data can be correctly collected by the clock signal of the serial digital interface of the first channel may include:
setting an initial delay parameter of an input signal delayer of the second delay unit;
Continuously collecting a plurality of data output by a preset serial-parallel converter of the second channel in each period, and if the plurality of data are not sampled correctly, increasing the delay parameter by a preset step length, or if the plurality of data are sampled correctly, recording the current delay parameter and increasing the delay parameter by the preset step length;
And when the delay parameter reaches the maximum delay parameter, obtaining the second delay parameter by using the recorded delay parameters.
In one possible implementation, the device may also be used to:
and dynamically adjusting delay parameters of the first channel and the second channel according to an alignment mode of a clock signal of the serial digital interface after delay of the first channel and a clock signal of the serial digital interface before delay and a conversion signal output by a conversion component in a preset delay unit.
In a possible implementation manner, the dynamically adjusting the delay parameters of the first channel and the second channel according to the alignment manner of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the preset delay unit includes:
collecting conversion signals for N times, wherein N is more than 1 and is an integer;
If the N conversion signals are all of a first preset value and the alignment mode is rising edge alignment, increasing delay parameters of the first channel and the second channel;
If the N conversion signals are all the first preset value and the alignment mode is falling edge alignment, reducing delay parameters of the first channel and the second channel;
if the N conversion signals are all of the second preset value and the alignment mode is rising edge alignment, reducing delay parameters of the first channel and the second channel;
If the N conversion signals are all the second preset value and the alignment mode is falling edge alignment, increasing delay parameters of the first channel and the second channel;
If at least one of the N converted signals has a value greater than a first preset value and less than a second preset value, the delay parameters of the first channel and the second channel are not changed.
The adjustment of the first delay parameter of the channel a and the second delay parameter of the channel B is exemplarily described below by taking a delay unit in the FPGA as an example for the first channel as the channel a and the second channel as the channel B.
Firstly, the connection relation of each component in each delay unit in the FPGA is described in an exemplary manner, and it should be noted that the following description of the connection relation of each component in each delay unit is only an exemplary manner of implementing the technical scheme of the disclosure, and should not be taken as limiting the embodiments of the disclosure.
Referring to fig. 5a, 5b, 5c, 5d, 5e, 5f, and 5g, fig. 5a, 5b, 5c, 5d, 5e, 5f, and 5g are schematic diagrams illustrating connection relationships between components of a delay unit according to an embodiment of the disclosure.
It should be understood that in the embodiment of the disclosure, the number of output terminals of the serial-to-parallel converter may include a plurality, for example, in fig. 5a, Q1 to Q8 may be included as a total of 8 output terminals, and of course, in other examples, the number of output terminals may also include other output terminals.
For example, for each channel, the embodiments of the present disclosure may configure a corresponding connection manner, for example, fig. 5a, fig. 5b, fig. 5c show a connection manner of each component of the delay unit corresponding to the channel 0, fig. 5d, fig. 5e show a connection manner of each component of the delay unit corresponding to the channel 1, and fig. 5f, fig. 5g show a connection manner of each component of the delay unit corresponding to the channel N.
For channel 0, as shown in fig. 5a, the input terminal of the differential input buffer IBUFDS is configured to receive the clock signal dc0_ch0 of channel 0, the output terminal of the differential input buffer IBUFDS is connected to the signal input terminal IDATAIN of the input signal Delay unit IDELAYE and the data input terminal D of the serial-to-parallel converter ISERDESE2, the Delay parameter input terminal of the input signal Delay unit IDELAYE2 is connected to the output terminal DelayValue of the bit clock alignment state machine PASM, the Delay parameter delay_ch0 of channel 0 output by the output terminal DelayValue of the bit clock alignment state machine PASM is received, the signal output terminal DATAOUT of the input signal Delay unit IDELAYE is connected to the input terminal of the I/O clock buffer IBUFIO and the input terminal of the area clock buffer BUFR, the output terminal of the I/O clock buffer IBUFIO is connected to the first clock signal terminal CLK of the serial-to-parallel converter ISERDESE2, the output terminal of the area clock buffer BUFR is connected to the input signal input terminal IDELAYE, the output terminal of the serial-to-parallel converter CLKDIV is connected to the output clock signal CLKDIV of the serial-to the input signal buffer CLKDIV, and the output terminal CLKDIV of the serial-to the data converter CLKDIV is connected to the output signal CLKDIV of the respective clock signal input unit CLKDIV of the serial-to the serial-parallel state machine CLKDIV.
For channel 0, as shown in fig. 5b, the input terminal of the differential input buffer IBUFDS is configured to receive the frame synchronization signal fr_ch0 of channel 0, the output terminal of the differential input buffer IBUFDS is connected to the data input terminal D of the serial-to-parallel converter ISERDESE, the data bit alignment port BitSlip of the serial-to-parallel converter ISERDESE is connected to the output terminal BitSlip of the data alignment module, the first clock signal terminal CLK of the serial-to-parallel converter ISERDESE2 is configured to receive the I/O clock signal CLK output by the output terminal of the I/O clock buffer IBUFIO, the second clock signal terminal CLKDIV of the serial-to-parallel converter ISERDESE is configured to receive the region clock signal CLKDIV output by the output terminal of the region clock buffer BUFR, the respective output terminals (Q1-Q8) of the serial-to-parallel converter ISERDESE2 are connected to the respective input terminals of the data alignment module, the clock signal terminal CLKDIV of the data alignment module is configured to receive the region clock signal CLKDIV output by the output terminal of the region clock buffer BUFR, and the output terminal BitSlip of the data alignment module is configured to output the region clock signal BitSlip.
For channel 0, as shown in fig. 5c, the input terminal of the differential input buffer IBUFDS is configured to receive the Data signal data_ch0 of channel 0, the output terminal of the differential input buffer IBUFDS is connected to the Data input terminal D of the serial-to-parallel converter ISERDESE, the Data bit alignment port BitSlip of the serial-to-parallel converter ISERDESE is configured to receive the bit alignment signal BitSlip _ch0 output by the Data alignment module, the first clock signal terminal CLK of the serial-to-parallel converter ISERDESE2 is configured to receive the I/O clock signal CLK output by the output terminal of the I/O clock buffer IBUFIO, the second clock signal terminal CLKDIV of the serial-to-parallel converter ISERDESE is configured to receive the local clock signal CLKDIV output by the output terminal of the local clock buffer BUFR, the respective output terminals (Q1-Q8) of the serial-to-parallel converter ISERDESE2 are connected to the respective input terminals of the Data acquisition module, the clock signal terminal CLKDIV of the Data acquisition module is configured to receive the local clock signal CLKDIV output by the output terminal of the local clock buffer BUFR, and the Data acquisition module is configured to output by the respective output terminal of the serial-to-parallel converter ISERDESE.
For channel 1, as shown in fig. 5D, the input terminal of the differential input buffer IBUFDS is configured to receive the frame synchronization signal fr_ch1 of channel 1, the output terminal of the differential input buffer IBUFDS is connected to the signal input terminal IDATAIN of the input signal Delay IDELAYE, the Delay parameter input terminal CNTVALUEIN of the input signal Delay IDELAYE is configured to receive the Delay parameter delay_ch1 of channel 1, the signal output terminal of the input signal Delay IDELAYE is connected to the data input terminal D of the serial-to-parallel converter ISERDESE2, the clock signal terminal C of the input signal Delay IDELAYE2, the first clock signal terminal CLK of the serial-to-parallel converter ISERDESE2 is configured to receive the I/O clock signal CLK output by the output terminal of the I/O clock buffer IBUFIO, the second clock signal terminal CLKDIV of the serial-to-parallel converter ISERDESE2 and the clock signal terminal CLKDIV of the data alignment module are configured to receive the local clock signal CLKDIV output by the output terminal of the local clock buffer BUFR, and the data alignment terminal 69 of the serial-to-parallel converter 95 is connected to the data alignment module 368 to the respective output terminals of the data alignment module 361 to the data input terminal of the data alignment module 988.
For channel 1, as shown in fig. 5e, the input terminal of the differential input buffer IBUFDS is for receiving the Data signal data_ch1 of channel 1, the output terminal of the differential input buffer IBUFDS is connected to the signal input terminal IDATAIN of the input signal delayer IDELAYE2, the Delay parameter input terminal CNTVALUEIN of the input signal delayer IDELAYE is connected to the output terminal DelayValue of the Delay decision state machine for receiving the Delay parameter delay_ch1 of channel 1, the signal output terminal of the input signal delayer IDELAYE2 is connected to the Data input terminal D of the serial-to-parallel converter ISERDESE2, the output terminal of the I/O clock buffer IBUFIO is connected to the clock signal terminal C of the input signal delayer IDELAYE2, the first clock signal terminal CLK of the serial-to-parallel converter ISERDESE2, the output end of the local clock buffer BUFR is connected to the second clock signal end CLKDIV of the serial-to-parallel converter ISERDESE2 and the clock signal end CLKDIV of the Delay judging state machine, the Data bit alignment port BitSlip of the serial-to-parallel converter ISERDESE is connected to the output end BitSlip of the Data alignment module to receive the bit alignment signal BitSlip _ch1, the output ends (Q1-Q8) of the serial-to-parallel converter ISERDESE2 are connected to the input ends of the Data acquisition module and the input ends of the Delay judging state machine, the Delay judging state machine is used for judging whether the Data output by the serial-to-parallel converter ISERDESE is incremental Data or decremental Data or not, and adjusting the Delay parameter, and the output end DelayValue of the Delay judging state machine is used for outputting the Delay parameter delay_ch1.
For the channel N, as shown in fig. 5f, the input end of the differential input buffer IBUFDS is configured to receive the frame synchronization signal fr_chn of the channel N, the output end of the differential input buffer IBUFDS is connected to the signal input end IDATAIN of the input signal Delay IDELAYE2, the Delay parameter input end CNTVALUEIN of the input signal Delay IDELAYE is configured to input the delay_chn of the channel N, the signal output end of the input signal Delay IDELAYE2 is connected to the data input end D of the serial-to-parallel converter ISERDESE2, the output end of the I/O clock buffer IBUFIO is connected to the clock signal end C of the input signal Delay IDELAYE, the first clock signal end CLK of the serial-to-parallel converter ISERDESE2, the output end of the local clock buffer BUFR is connected to the second clock signal end CLKDIV of the serial-to-parallel converter ISERDESE and the clock signal end CLKDIV of the data alignment module, the data bit alignment end BitSlip of the serial-to-parallel converter ISERDESE is connected to the output end BitSlip of the data alignment module to receive the bit aligned signal q_58_n and the output ends Q658 of the data alignment modules (Q1 to Q2).
For the channel N, as shown in fig. 5g, the input end of the differential input buffer IBUFDS is configured to receive the Data signal data_chn of the channel N, the output end of the differential input buffer IBUFDS is connected to the signal input end IDATAIN of the input signal Delay unit IDELAYE2, the Delay parameter input end CNTVALUEIN of the input signal Delay unit IDELAYE2 is configured to input the Delay parameter delay_chn of the channel N, the signal output end of the input signal Delay unit IDELAYE is connected to the Data input end D of the serial-to-parallel converter ISERDESE2, the output end of the I/O clock buffer IBUFIO is connected to the clock signal end C of the input signal Delay unit IDELAYE, the first clock signal end CLK of the serial-to-parallel converter ISERDESE2, the output end of the area clock buffer BUFR is connected to the second clock signal end CLKDIV of the serial-to-parallel converter ISERDESE2 and the clock signal end CLKDIV of the Delay judgment state machine, the Data bit alignment port BitSlip of the serial-to-parallel converter ISERDESE is connected to the output end BitSlip of the Data alignment module to receive the bit alignment signal input end of the serial-to-parallel converter ISERDESE2, the output end of the Data bit alignment module is connected to the output end of the Data alignment module 5342 to the output the serial-to the state machine, and the output end of the Data signal Delay unit is connected to the output of the Delay unit for judging state machine is connected to the state machine for judging whether the state machine is being output by the state of the Data signal output of the state of the serial-to the Data signal output of the serial-to the Data signal Delay unit by the output of the Data signal buffer through the Delay unit by the Delay unit 352, and the output signal of the Data signal is output by the output signal of the output signal.
After the above connection manner is configured, the embodiments of the present disclosure may determine delay parameters of each channel, and will be described by taking a channel a and a channel B as examples.
Referring to fig. 6a and 6B, fig. 6a and 6B are schematic diagrams illustrating adjustment of a first delay parameter of a channel a and a second delay parameter of a channel B by using the multi-channel serial digital interface timing alignment adjustment method according to the embodiments of the disclosure.
In one example, as shown in fig. 6a and 6B, the ADC may be set to Testmode mode in step S301 (naturally, the setting of the first delay parameter of the channel a may also be performed in the operation mode, so, in other examples, the ADC may also be set to Testmode mode when the determination of the second delay parameter of the channel B is started is completed), the initial delay Value DelayA of the DCO of the channel a in the delay unit is set to 0 in step S302, the serial-parallel Value of the DCO of the channel a is acquired in step S303, the state of the serial-parallel Value is determined in step S304, and if the serial-parallel Value is 0xFF or 0x00, the delay Value of the DCO of the channel a is increased (step S305); if the serial-parallel Value is a continuously variable Value (for example, is not 0xFF or 0x00, and the front and rear values are different), the current delay Value is recorded (in step S306), and the delay Value of DCO of channel a is increased, in step S307, if the delay Value DelayA is less than or equal to 0x31, the process goes to step 303 to continue the above, otherwise, step S308 is performed, that is, if there is no recorded delay Value of channel a, the process goes to step 320 to set the ADC to the normal operation mode, the adjustment failure flag position 1 is a window adjustment failure, if there is a recorded delay Value of channel a, the intermediate Value of the first delay Value is taken as the DCO delay Value (the first delay parameter) of channel a, after the first delay parameter is obtained, the second delay parameter of channel B can be determined, in step S310, the initial delay Value of channel B data is set to 0, in step S311, the data realignment module waits for the completion of data realignment in step S312, in step S313, the number of data output from channel B is determined in step S313, if the number of channel B is incremented in step S314, if the delay value is not the increment number, the delay value of the channel B is not recorded, in step S315, the delay value of the channel B is recorded, in step S316, if the delay value is less than or equal to 0x31, step S311 is continuously executed, otherwise, step S317 is executed, if the delay value of the channel B is not recorded, step S320 is skipped to set the ADC to a normal working mode, the adjustment failure flag position 1 is indicated to be failed, if the delay value of the channel B is recorded, step S318 is executed to take the intermediate value of the first delay value of the channel B as the delay value of the data of the channel B, then in step S319, the ADC is set to the normal working mode, the adjustment success flag position 1 is indicated to be successful.
In one possible embodiment, as shown in fig. 4, the method may further include:
Step S21, according to an alignment manner of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the delay unit, the dynamically adjusting the delay parameters of the first channel and the second channel may include:
setting the ADC into a normal working mode, wherein in the normal working mode, the FPGA can accurately and synchronously acquire data of a plurality of channels of the ADC;
And dynamically adjusting delay parameters of the input signal delayer IDELAYE2 of the first channel and the input signal delayer IDELAYE of the second channel according to an alignment mode of the clock signal of the serial digital interface after delay and the clock signal of the serial digital interface before delay of the first channel and a conversion signal output by the serial-parallel converter ISERDESE.
According to the embodiment of the disclosure, in the normal working mode, according to the alignment mode of the clock signal of the serial digital interface after delay of the first channel and the clock signal of the serial digital interface before delay and the conversion signal outputted by the serial-parallel converter ISERDESE, the delay parameters of the input signal delayer IDELAYE2 of the first channel and the input signal delayer IDELAYE2 of the second channel are dynamically adjusted, so that adaptation to external environment change can be realized, a time sequence window is dynamically adjusted, and the time sequence window is dynamically corrected on the premise that service is not interrupted in the system operation process, and the accuracy of acquired data is ensured.
For example, the dynamic adjustment of the delay parameters of the input signal delay IDELAYE of the first channel and the input signal delay IDELAYE of the second channel may be, for example, synchronous adjustment of the delay parameters of the input signal delay IDELAYE of the first channel and the input signal delay IDELAYE of the second channel, and the amplitude of each adjustment may be the same, so as to improve the efficiency of dynamic adjustment.
In a possible implementation manner, step S21 may dynamically adjust delay parameters of the first channel and the second channel according to an alignment manner of a clock signal of the serial digital interface after delay and a clock signal of the serial digital interface before delay and a conversion signal output by a conversion component in the delay unit, where the step may include:
collecting conversion signals for N times, wherein N is more than 1 and is an integer;
If the N conversion signals are all of a first preset value and the alignment mode is rising edge alignment, increasing delay parameters of the first channel and the second channel;
If the N conversion signals are all the first preset value and the alignment mode is falling edge alignment, reducing delay parameters of the first channel and the second channel;
if the N conversion signals are all of the second preset value and the alignment mode is rising edge alignment, reducing delay parameters of the first channel and the second channel;
If the N conversion signals are all the second preset value and the alignment mode is falling edge alignment, increasing delay parameters of the first channel and the second channel;
If at least one of the N converted signals has a value greater than a first preset value and less than a second preset value, the delay parameters of the first channel and the second channel are not changed.
The specific size of N is not limited in the embodiments of the present disclosure, and may be set by those skilled in the art according to actual situations and needs.
For example, when the delay Value of the channel a adjusting DCO increases from 0 to 0X31, the serial-to-parallel converter ISERDESE of the channel a outputs a Value (converted signal) as shown in table 1 below may occur.
TABLE 1
Delay value variation Value change After delay DCO aligns the edge of original DCO
0->0x31 0X00- > uncertain state- >0xFF Rising edge
0->0x31 0XFF- > uncertain state- >0x00 Falling edge
0->0x31 0X00- > uncertain state Rising edge
0->0x31 0XFF- > uncertainty state Falling edge
0->0x31 Uncertain state >0xFF Rising edge
0->0x31 Uncertain state >0x00 Falling edge
0->0x31 Always keep 0xFF Unknown
0->0x31 Always keep 0x00 Unknown
Illustratively, after knowing the alignment edge of the DCO, the alignment can be dynamically adjusted according to the Value of the output Value of the channel a serial-to-parallel converter ISERDESE, which can be divided into 4 cases shown in table 2.
TABLE 2
Alignment edge Value Delay adjustment
Rising edge 0xFF Reduction of
Rising edge 0x00 Increase in size
Falling edge 0xFF Increase in size
Falling edge 0x00 Reduction of
Referring to fig. 7, fig. 7 is a schematic diagram illustrating dynamic adjustment of delay parameters according to an embodiment of the disclosure.
By way of example, as shown in FIG. 7, 5 values may be collected, the delay Value of channel A and channel B is increased if all values obtained from 5 collection are 0x00 and the rising edges are aligned, the delay Value of channel A and channel B is decreased if all values obtained from 5 collection are 0x00 and the falling edges are aligned, the delay Value of channel A and channel B is decreased if all values obtained from 5 collection are 0xFF and the rising edges are aligned, the delay Value of channel A and channel B is decreased if all values obtained from 5 collection are 0xFF and the falling edges are aligned, the delay Value of channel A and channel B is increased, and the delay Value is not changed if one or more values greater than 0x00 and less than 0xFF appear in the Value obtained from 5 collection.
By determining a first delay parameter of a clock signal of a serial digital interface of the first channel at the delay unit, determining, in a test mode of the ADC, that when data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel is at a second delay parameter of the delay unit, setting the delay parameter of the first channel at the delay unit to be the first delay parameter, setting the delay parameter of the second channel at the delay unit to be the second delay parameter, and in a normal operation mode, according to the alignment mode of the clock signal of the serial digital interface after delay of the first channel and the clock signal of the serial digital interface before delay and the conversion signal output by the serial-parallel converter ISERDESE, the delay parameters of the input signal delayer IDELAYE of the first channel and the delay parameters of the input signal delayer IDELAYE of the second channel are dynamically adjusted, so that the problem of time sequence stability of 1-channel clock DCO sampling multi-channel high-speed serial LVDS data can be effectively solved, a time sequence window can be effectively increased, external environment change can be adapted, the time sequence window can be dynamically adjusted, the accuracy of collected data can be ensured under the premise that service is not interrupted in the system operation process, clock resources can be saved, the application fields of single clock and multiple chips can be further expanded, IO resources are effectively saved, and the high-low temperature working robustness of the system is improved.
It will be appreciated that the above-mentioned method embodiments of the present disclosure may be combined with each other to form a combined embodiment without departing from the principle logic, and are limited to the description of the present disclosure. It will be appreciated by those skilled in the art that in the above-described methods of the embodiments, the particular order of execution of the steps should be determined by their function and possible inherent logic.
In addition, the disclosure further provides a multi-channel serial digital interface time sequence alignment adjustment device, an electronic device, a storage medium and a program, which can be used for implementing any of the multi-channel serial digital interface time sequence alignment adjustment methods provided in the disclosure, and corresponding technical schemes and descriptions and corresponding descriptions referring to method parts are omitted.
Referring to fig. 8, fig. 8 shows a block diagram of a multi-channel serial digital interface timing alignment adjustment apparatus according to an embodiment of the disclosure.
The channels include a first channel and at least one second channel, the serial digital interface data of the multiple channels share the clock signal of the same channel, and the serial digital interface clock and the data are respectively delayed by using an FPGA delay unit, as shown in fig. 8, the apparatus includes:
a first determining module 10, configured to determine a first delay parameter of a clock signal of the serial digital interface of the first channel in the delay unit;
a second determining module 20, configured to determine a second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel;
The setting module 30 is configured to set a delay parameter of the first channel in the delay unit to be a first delay parameter, and set a delay parameter of the second channel in the delay unit to be a second delay parameter.
According to the multi-channel serial digital interface time sequence alignment adjustment method, through determining the first delay parameter of the clock signal of the serial digital interface of the first channel in the time delay unit, when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel is determined to be the second delay parameter of the time delay unit, the delay parameter of the first channel in the time delay unit is set to be the first delay parameter, the delay parameter of the second channel in the time delay unit is set to be the second delay parameter, the problem that a DCO window is too small and time sequence errors are easy to occur can be solved, the fact that the multi-channel data share the clock signal of the same serial digital interface can be achieved, the data of a plurality of channels of transmitting end assemblies can be accurately and synchronously collected by a receiving end assembly, IO (input/output) resources of the receiving end assembly are saved, and the expansion possibility, flexibility and reliability are improved.
In one possible implementation manner, the determining the first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit includes:
setting an initial delay parameter of the first channel;
Continuously collecting a conversion signal obtained by a conversion component in the delay unit, and increasing the delay parameter with a preset step length under the condition that the conversion signal is a first preset value or a second preset value, or recording the current delay parameter under the condition that the conversion signal is not the first preset value or the second preset value and is different from the previous conversion signal, and increasing the delay parameter with the preset step length;
And when the delay parameter reaches the maximum delay parameter, obtaining the first delay parameter by using the recorded delay parameters.
In one possible implementation manner, when the delay parameter reaches the maximum delay parameter, the obtaining the first delay parameter by using the recorded multiple delay parameters includes:
And taking the average value or the median of the plurality of delay parameters as the first delay parameter.
In one possible implementation manner, the determining the second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel includes:
setting an initial delay parameter of the second channel;
Continuously collecting a plurality of data output by the second channel in each period, if the plurality of data are not sampled correctly, increasing the delay parameter with a preset step length, or if the plurality of data are sampled correctly, recording the current delay parameter, and increasing the delay parameter with the preset step length;
And when the delay parameter reaches the maximum delay parameter, obtaining the second delay parameter by using the recorded delay parameters.
In a possible implementation manner, when the delay parameter reaches a maximum delay parameter, the obtaining the second delay parameter by using the recorded plurality of delay parameters includes:
and taking the average value or the median of the plurality of delay parameters as the second delay parameter.
In one possible embodiment, the method further comprises:
And dynamically adjusting delay parameters of the first channel and the second channel according to an alignment mode of the clock signal of the serial digital interface after delay of the first channel and the clock signal of the serial digital interface before delay and a conversion signal output by a conversion component in the delay unit.
In one possible implementation manner, the dynamically adjusting the delay parameters of the first channel and the second channel according to the alignment manner of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the delay unit includes:
collecting conversion signals for N times, wherein N is more than 1 and is an integer;
If the N conversion signals are all of a first preset value and the alignment mode is rising edge alignment, increasing delay parameters of the first channel and the second channel;
If the N conversion signals are all the first preset value and the alignment mode is falling edge alignment, reducing delay parameters of the first channel and the second channel;
if the N conversion signals are all of the second preset value and the alignment mode is rising edge alignment, reducing delay parameters of the first channel and the second channel;
If the N conversion signals are all the second preset value and the alignment mode is falling edge alignment, increasing delay parameters of the first channel and the second channel;
If at least one of the N converted signals has a value greater than a first preset value and less than a second preset value, the delay parameters of the first channel and the second channel are not changed.
In one possible implementation, the receiving end component delays the serial digital interface clock and the data respectively using a delay unit, where the delay unit includes:
A differential input buffer for converting a differential signal into a single-ended signal, the differential signal including a clock signal and a data signal;
The input signal delayer is connected with the differential input buffer and is used for delaying the single-ended signal according to a set delay parameter, wherein the delay parameter comprises the first delay parameter and the second delay parameter;
The I/O clock buffer and the regional clock buffer are connected with the input signal delayer and are respectively used for outputting an I/O clock signal and a regional clock signal according to the delayed clock signals;
the serial-to-parallel converter is used for receiving the single-ended signal and the I/O clock signal, carrying out serial-to-parallel conversion on the single-ended signal and outputting a converted signal;
A bit clock alignment state machine for determining whether the single-ended signal is aligned with the I/O clock signal according to the conversion signal,
Wherein the determining the second delay parameter of the data signal of the second channel when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel comprises:
And in a test mode of the transmitting end assembly, determining a second delay parameter of the data signal of the second channel when the data of the second channel can be correctly acquired by the clock signal of the serial digital interface of the first channel.
In one possible embodiment, the first preset value is 0x00 and the second preset value is 0xFF.
In some embodiments, functions or modules included in an apparatus provided by the embodiments of the present disclosure may be used to perform a method described in the foregoing method embodiments, and specific implementations thereof may refer to descriptions of the foregoing method embodiments, which are not repeated herein for brevity.
The disclosed embodiments also provide a storage medium having stored thereon program instructions that when executed by a processor implement the above-described method. The storage medium may be a non-volatile storage medium.
The embodiment of the disclosure also provides electronic equipment, which comprises a processor and a memory for storing instructions executable by the processor, wherein the processor is configured to call the instructions stored by the memory so as to execute the method.
Embodiments of the present disclosure also provide a computer program product comprising computer readable code, or a non-volatile storage medium carrying computer readable code, which when executed in a processor of an electronic device, performs the above-described method.
The electronic device may be provided as a terminal, server or other form of device.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims (17)

1.一种多通道串行数字接口时序对齐调整方法，其特征在于，所述通道包括第一通道及至少一个第二通道，多通道串行数字接口数据共用同一通道的时钟信号，使用延时单元对串行数字接口时钟和数据分别进行延时，所述方法包括：1. A multi-channel serial digital interface timing alignment adjustment method, characterized in that the channels include a first channel and at least one second channel, the multi-channel serial digital interface data share a clock signal of the same channel, and a delay unit is used to delay the serial digital interface clock and data respectively, the method comprising: 确定所述第一通道的串行数字接口的时钟信号在所述延时单元的第一延时参数；Determine a first delay parameter of a clock signal of the serial digital interface of the first channel in the delay unit; 确定当所述第二通道的数据能够被所述第一通道的串行数字接口的时钟信号正确采集时，所述第二通道的数据信号在所述延时单元的第二延时参数；Determine a second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel; 设置所述第一通道在所述延时单元的延时参数为第一延时参数，设置所述第二通道在所述延时单元的延时参数为第二延时参数。The delay parameter of the first channel in the delay unit is set to a first delay parameter, and the delay parameter of the second channel in the delay unit is set to a second delay parameter. 2.根据权利要求1所述的方法，其特征在于，所述确定所述第一通道的串行数字接口的时钟信号在所述延时单元的第一延时参数，包括：2. The method according to claim 1, characterized in that the step of determining a first delay parameter of the clock signal of the serial digital interface of the first channel in the delay unit comprises: 设置所述第一通道的初始延时参数；Setting the initial delay parameters of the first channel; 持续采集所述延时单元中的转换组件得到的转换信号，在所述转换信号为第一预设值或第二预设值的情况下，以预设步长增加所述延时参数；或在所述转换信号不为所述第一预设值或所述第二预设值、且与前一转换信号不同的情况下，记录当前延时参数，并以所述预设步长增加所述延时参数；Continuously collecting the conversion signal obtained by the conversion component in the delay unit, and when the conversion signal is a first preset value or a second preset value, increasing the delay parameter by a preset step length; or when the conversion signal is not the first preset value or the second preset value and is different from the previous conversion signal, recording the current delay parameter and increasing the delay parameter by the preset step length; 当所述延时参数达到最大延时参数时，利用记录的多个延时参数得到所述第一延时参数。When the delay parameter reaches a maximum delay parameter, the first delay parameter is obtained by using a plurality of recorded delay parameters. 3.根据权利要求2所述的方法，其特征在于，所述当所述延时参数达到最大延时参数时，利用记录的多个延时参数得到所述第一延时参数，包括：3. The method according to claim 2, characterized in that when the delay parameter reaches a maximum delay parameter, obtaining the first delay parameter using a plurality of recorded delay parameters comprises: 将所述多个延时参数的平均值或中位数作为所述第一延时参数。An average value or a median value of the plurality of delay parameters is used as the first delay parameter. 4.根据权利要求1所述的方法，其特征在于，所述确定当所述第二通道的数据能够被所述第一通道的串行数字接口的时钟信号正确采集时，所述第二通道的数据信号在所述延时单元的第二延时参数，包括：4. The method according to claim 1, characterized in that the determining that when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel is in the second delay parameter of the delay unit comprises: 设置所述第二通道的初始延时参数；Setting the initial delay parameters of the second channel; 在各个周期均连续采集所述第二通道输出的多个数据，若所述多个数据未被正确采样，则以预设步长增加所述延时参数；或若所述多个数据被正确采样，则记录当前延时参数，并以所述预设步长增加所述延时参数；Continuously collecting a plurality of data outputted by the second channel in each cycle, and if the plurality of data are not correctly sampled, increasing the delay parameter by a preset step length; or if the plurality of data are correctly sampled, recording the current delay parameter, and increasing the delay parameter by the preset step length; 当所述延时参数达到最大延时参数时，利用记录的多个延时参数得到所述第二延时参数。When the delay parameter reaches a maximum delay parameter, the second delay parameter is obtained by using a plurality of recorded delay parameters. 5.根据权利要求4所述的方法，其特征在于，所述当所述延时参数达到最大延时参数时，利用记录的多个延时参数得到所述第二延时参数，包括：5. The method according to claim 4, characterized in that when the delay parameter reaches the maximum delay parameter, obtaining the second delay parameter by using the recorded multiple delay parameters comprises: 将所述多个延时参数的平均值或中位数作为所述第二延时参数。An average value or a median value of the plurality of delay parameters is used as the second delay parameter. 6.根据权利要求1～5任一项所述的方法，其特征在于，所述方法还包括：6. The method according to any one of claims 1 to 5, characterized in that the method further comprises: 根据所述第一通道的延时后的串行数字接口的时钟信号与延时前的串行数字接口的时钟信号的对齐方式及所述延时单元中的转换组件输出的转换信号，对所述第一通道及所述第二通道的延时参数进行动态调整。The delay parameters of the first channel and the second channel are dynamically adjusted according to the alignment of the clock signal of the serial digital interface after delay and the clock signal of the serial digital interface before delay and the conversion signal output by the conversion component in the delay unit. 7.根据权利要求6所述的方法，其特征在于，所述根据所述第一通道的延时后的串行数字接口的时钟信号与延时前的串行数字接口的时钟信号的对齐方式及所述延时单元中的转换组件输出的转换信号，对所述第一通道及所述第二通道的延时参数进行动态调整，包括：7. The method according to claim 6, characterized in that the delay parameters of the first channel and the second channel are dynamically adjusted according to the alignment mode of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the delay unit, comprising: N次采集转换信号，N＞1且为整数；Collect and convert signals N times, where N>1 and is an integer; 如果N个转换信号都为第一预设值且所述对齐方式为上升沿对齐，则增加所述第一通道和所述第二通道的延时参数；If the N conversion signals are all the first preset values and the alignment mode is rising edge alignment, then increasing the delay parameters of the first channel and the second channel; 如果N个转换信号都为所述第一预设值且所述对齐方式为下降沿对齐，则减小所述第一通道和所述第二通道的延时参数；If the N conversion signals are all the first preset values and the alignment mode is falling edge alignment, reducing the delay parameters of the first channel and the second channel; 如果N个转换信号都为第二预设值且所述对齐方式为上升沿对齐，则减小所述第一通道和所述第二通道的延时参数；If the N conversion signals are all the second preset values and the alignment mode is rising edge alignment, reducing the delay parameters of the first channel and the second channel; 如果N个转换信号都为所述第二预设值且所述对齐方式为下降沿对齐，则增加所述第一通道和所述第二通道的延时参数；If the N conversion signals are all the second preset values and the alignment mode is falling edge alignment, then increase the delay parameters of the first channel and the second channel; 如果N个转换信号中出现至少一次大于第一预设值且小于第二预设值的值，则不改变所述第一通道和所述第二通道的延时参数。If a value greater than the first preset value and less than the second preset value appears at least once in the N conversion signals, the delay parameters of the first channel and the second channel are not changed. 8.根据权利要求1所述的方法，其特征在于，接收端组件使用延时单元对串行数字接口时钟和数据分别进行延时，所述延时单元包括：8. The method according to claim 1, characterized in that the receiving end component uses a delay unit to delay the serial digital interface clock and data respectively, and the delay unit comprises: 输入信号延时器，用于接收时钟信号或者数据信号，根据设置的延时参数对所述时钟信号或者所述数据信号进行延时，输出延时时钟信号和延时数据信号，其中，所述延时参数包括所述第一延时参数、所述第二延时参数；An input signal delayer, used for receiving a clock signal or a data signal, delaying the clock signal or the data signal according to a set delay parameter, and outputting a delayed clock signal and a delayed data signal, wherein the delay parameter includes the first delay parameter and the second delay parameter; 串并转换器，用于接收所述时钟信号或者所述数据信号，对所述时钟信号或者所述数据信号进行串并转换，输出转换信号；A serial-to-parallel converter, used for receiving the clock signal or the data signal, performing serial-to-parallel conversion on the clock signal or the data signal, and outputting a conversion signal; 分频模块，用于将所述时钟信号进行分频，输出分频时钟，为所述串并转换器提供时钟；A frequency division module, used for dividing the frequency of the clock signal, outputting a divided clock, and providing a clock for the serial-to-parallel converter; 位时钟对齐状态机，用于根据对所述时钟信号串并转换后得到的所述转换信号判断所述时钟信号与所述延时时钟信号是否对齐；A bit clock alignment state machine, used for judging whether the clock signal is aligned with the delayed clock signal according to the conversion signal obtained after serial-to-parallel conversion of the clock signal; 延时判断状态机，用于根据对所述延时数据信号进行串并转换后得到的所述转换信号判断当前延时值是否能够使得数据被正确采集；A delay judgment state machine, used to judge whether the current delay value can enable data to be correctly collected according to the conversion signal obtained after serial-to-parallel conversion of the delayed data signal; 数据对齐模块，用于调整所述延时数据信号串并转换后的所述转换信号之间的错位，使得所述转换信号的边界被正确识别；A data alignment module, used for adjusting the misalignment between the conversion signals after the serial-to-parallel conversion of the delayed data signals, so that the boundaries of the conversion signals are correctly identified; 其中，所述确定当所述第二通道的数据能够被所述第一通道的串行数字接口的时钟信号正确采集时，所述第二通道的数据信号在所述延时单元的第二延时参数，包括：The step of determining that when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the data signal of the second channel is at the second delay parameter of the delay unit includes: 在发射端组件的测试模式下，确定当所述第二通道的数据能够被所述第一通道串行数字接口的时钟信号正确采集时，所述第二通道的数据信号的第二延时参数。In a test mode of the transmitting end component, a second delay parameter of the data signal of the second channel is determined when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel. 9.根据权利要求2或3或7所述的方法，其特征在于，所述第一预设值为0x00，所述第二预设值为0xFF。9. The method according to claim 2 or 3 or 7, characterized in that the first preset value is 0x00 and the second preset value is 0xFF. 10.一种多通道串行数字接口时序对齐调整装置，其特征在于，所述通道包括第一通道及至少一个第二通道，多通道串行数字接口数据共用同一通道的时钟信号，使用延时单元对串行数字接口时钟和数据分别进行延时，所述装置包括：10. A multi-channel serial digital interface timing alignment adjustment device, characterized in that the channels include a first channel and at least one second channel, the multi-channel serial digital interface data share the clock signal of the same channel, and a delay unit is used to delay the serial digital interface clock and data respectively, and the device comprises: 第一确定模块，用于确定所述第一通道的串行数字接口的时钟信号在所述延时单元的第一延时参数；A first determining module, used to determine a first delay parameter of a clock signal of a serial digital interface of the first channel in the delay unit; 第二确定模块，用于确定当所述第二通道的数据能够被所述第一通道的串行数字接口的时钟信号正确采集时，所述第二通道的数据信号在所述延时单元的第二延时参数；A second determining module, used to determine a second delay parameter of the data signal of the second channel in the delay unit when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel; 设置模块，用于设置所述第一通道在所述延时单元的延时参数为第一延时参数，设置所述第二通道在所述延时单元的延时参数为第二延时参数。The setting module is used to set the delay parameter of the first channel in the delay unit to be a first delay parameter, and to set the delay parameter of the second channel in the delay unit to be a second delay parameter. 11.一种多通道串行数字接口时序对齐调整设备，其特征在于，所述通道包括第一通道及至少一个第二通道，多通道串行数字接口数据共用同一通道的时钟信号，使用延时单元对串行数字接口时钟和数据分别进行延时，所述设备包括第一延时单元、至少一个第二延时单元，所述第一延时单元及所述第二延时单元均包括输入信号延时器、串并转换器、位时钟对齐状态机、数据对齐模块及数据采集模块，所述第一延时单元还包括分频模块，所述第二延时单元还包括延时判断状态机，所述第一延时单元用于确定所述第一通道的串行数字接口的时钟信号在所述第一延时单元的第一延时参数，各个第二延时单元用于确定当各个第二通道的数据能够被所述第一通道的串行数字接口的时钟信号正确采集时，所述第二通道的数据信号在所述第二延时单元的第二延时参数，其中，11. A multi-channel serial digital interface timing alignment adjustment device, characterized in that the channel includes a first channel and at least one second channel, the multi-channel serial digital interface data share the clock signal of the same channel, and a delay unit is used to delay the serial digital interface clock and data respectively, the device includes a first delay unit and at least one second delay unit, the first delay unit and the second delay unit both include an input signal delayer, a serial-to-parallel converter, a bit clock alignment state machine, a data alignment module and a data acquisition module, the first delay unit also includes a frequency division module, the second delay unit also includes a delay judgment state machine, the first delay unit is used to determine the first delay parameter of the clock signal of the serial digital interface of the first channel in the first delay unit, and each second delay unit is used to determine when the data of each second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the second delay parameter of the data signal of the second channel in the second delay unit, wherein, 所述输入信号延时器，用于接收时钟信号或者数据信号，根据设置的延时参数对所述时钟信号或者所述数据信号进行延时，输出延时时钟信号和延时数据信号，其中，所述延时参数包括所述第一延时参数、所述第二延时参数；The input signal delayer is used to receive a clock signal or a data signal, delay the clock signal or the data signal according to a set delay parameter, and output a delayed clock signal and a delayed data signal, wherein the delay parameter includes the first delay parameter and the second delay parameter; 所述串并转换器，用于接收所述时钟信号或者所述数据信号，对所述时钟信号或者所述数据信号进行串并转换，输出转换信号；The serial-to-parallel converter is used to receive the clock signal or the data signal, perform serial-to-parallel conversion on the clock signal or the data signal, and output a conversion signal; 所述分频模块，用于将所述时钟信号进行分频，输出分频时钟，为所述串并转换器提供时钟；The frequency division module is used to divide the frequency of the clock signal, output the divided clock, and provide a clock for the serial-to-parallel converter; 所述位时钟对齐状态机，用于根据对所述时钟信号串并转换后得到的所述转换信号判断所述时钟信号与所述延时时钟信号是否对齐；The bit clock alignment state machine is used to determine whether the clock signal is aligned with the delayed clock signal according to the conversion signal obtained after serial-to-parallel conversion of the clock signal; 所述延时判断状态机，用于根据对所述延时数据信号进行串并转换后得到的所述转换信号判断当前延时值是否能够使得数据被正确采集；The delay judgment state machine is used to judge whether the current delay value can enable data to be correctly collected according to the conversion signal obtained after serial-to-parallel conversion of the delayed data signal; 数据对齐模块，用于调整所述延时数据信号串并转换后的所述转换信号之间的错位，使得所述转换信号的边界被正确识别；A data alignment module, used for adjusting the misalignment between the conversion signals after the serial-to-parallel conversion of the delayed data signals, so that the boundaries of the conversion signals are correctly identified; 所述数据采集模块用于采集串并转换器输出的数据。The data acquisition module is used to acquire data output by the serial-to-parallel converter. 12.根据权利要求11所述的设备，其特征在于，所述第一延时单元中串并转换器包括第一串并转换器、第二串并转换器、第三串并转换器，其中，12. The device according to claim 11, characterized in that the serial-to-parallel converter in the first delay unit comprises a first serial-to-parallel converter, a second serial-to-parallel converter, and a third serial-to-parallel converter, wherein: 所述输入信号延时器的数据输入端用于输入所述时钟信号，The data input terminal of the input signal delayer is used to input the clock signal. 所述输入信号延时器的延时参数输入端连接于所述位时钟对齐状态机的输出端，以接收所述位时钟对齐状态机输出的延时参数，The delay parameter input end of the input signal delayer is connected to the output end of the bit clock alignment state machine to receive the delay parameter output by the bit clock alignment state machine. 所述输入信号延时器的输出端连接于所述第一延时单元的第一串并转换器的第一时钟信号端、所述第一延时单元的第二串并转换器的第一时钟信号端、所述第一延时单元的第三串并转换器的第一时钟信号端及所述分频模块的输入端，The output end of the input signal delayer is connected to the first clock signal end of the first serial-to-parallel converter of the first delay unit, the first clock signal end of the second serial-to-parallel converter of the first delay unit, the first clock signal end of the third serial-to-parallel converter of the first delay unit and the input end of the frequency division module. 所述分频模块的输出端连接于所述第一延时单元的第一串并转换器的第二时钟信号端、所述第一延时单元的第二串并转换器的第二时钟信号端、所述第一延时单元的第三串并转换器的第二时钟信号端，The output end of the frequency division module is connected to the second clock signal end of the first serial-to-parallel converter of the first delay unit, the second clock signal end of the second serial-to-parallel converter of the first delay unit, and the second clock signal end of the third serial-to-parallel converter of the first delay unit. 所述第一延时单元的第一串并转换器的数据输入端用于接收所述时钟信号，The data input terminal of the first serial-to-parallel converter of the first delay unit is used to receive the clock signal. 所述第一延时单元的第一串并转换器的输出端连接于所述位时钟对齐状态机的数据输入端，The output end of the first serial-to-parallel converter of the first delay unit is connected to the data input end of the bit clock alignment state machine. 所述第一延时单元的第二串并转换器的数据输入端用于接收帧同步信号，The data input terminal of the second serial-to-parallel converter of the first delay unit is used to receive a frame synchronization signal. 所述第一延时单元的第二串并转换器的输出端连接于所述数据对齐模块的输入端，The output end of the second serial-to-parallel converter of the first delay unit is connected to the input end of the data alignment module. 所述第一延时单元的第三串并转换器的数据输入端用于接收数据信号，The data input terminal of the third serial-to-parallel converter of the first delay unit is used to receive a data signal. 所述第一延时单元的第三串并转换器的输出端连接于所述数据采集模块的输入端。The output end of the third serial-to-parallel converter of the first delay unit is connected to the input end of the data acquisition module. 13.根据权利要求12所述的设备，其特征在于，所述第二延时单元中输入信号延时器包括第一输入信号延时器、第二输入信号延时器，所述第二延时单元中串并转换器包括第一串并转换器、第二串并转换器，13. The device according to claim 12, characterized in that the input signal delay device in the second delay unit includes a first input signal delay device and a second input signal delay device, and the serial-to-parallel converter in the second delay unit includes a first serial-to-parallel converter and a second serial-to-parallel converter, 所述第一输入信号延时器的数据输入端用于接收帧同步信号，The data input terminal of the first input signal delayer is used to receive a frame synchronization signal. 所述第一输入信号延时器的延时参数输入端连接于所述延时判断状态机的输出端，用于接收所述延时判断状态机输出的延时参数，The delay parameter input end of the first input signal delayer is connected to the output end of the delay judgment state machine, and is used to receive the delay parameter output by the delay judgment state machine. 所述第一输入信号延时器的数据输出端连接于所述第二延时单元的第一串并转换器的数据输入端，The data output terminal of the first input signal delayer is connected to the data input terminal of the first serial-to-parallel converter of the second delay unit. 所述第二输入信号延时器的数据输入端用于接收数据信号，The data input terminal of the second input signal delayer is used to receive a data signal. 所述第二输入信号延时器的延时参数输入端连接于所述延时判断状态机的输出端，用于接收所述延时判断状态机输出的延时参数，The delay parameter input end of the second input signal delayer is connected to the output end of the delay judgment state machine, and is used to receive the delay parameter output by the delay judgment state machine. 所述第二输入信号延时器的数据输出端连接于所述第二延时单元的第二串并转换器的数据输入端，The data output terminal of the second input signal delayer is connected to the data input terminal of the second serial-to-parallel converter of the second delay unit. 所述第二延时单元的第一串并转换器的第一时钟信号端、所述第二延时单元的第二串并转换器的第一时钟信号端连接于所述第一延时单元的所述输入信号延时器的输出端，The first clock signal end of the first serial-to-parallel converter of the second delay unit and the first clock signal end of the second serial-to-parallel converter of the second delay unit are connected to the output end of the input signal delay of the first delay unit. 所述第二延时单元的第一串并转换器的第二时钟信号端、所述第二延时单元的第二串并转换器的第二时钟信号端连接于所述分频模块的输出端，The second clock signal end of the first serial-to-parallel converter of the second delay unit and the second clock signal end of the second serial-to-parallel converter of the second delay unit are connected to the output end of the frequency division module. 所述第二延时单元的第一串并转换器的输出端连接于所述数据对齐模块的输入端，The output end of the first serial-to-parallel converter of the second delay unit is connected to the input end of the data alignment module. 所述第二延时单元的第二串并转换器的输出端连接于所述数据采集模块的输入端及所述延时判断状态机的输入端。The output end of the second serial-to-parallel converter of the second delay unit is connected to the input end of the data acquisition module and the input end of the delay judgment state machine. 14.根据权利要求11～13任一项所述的设备，其特征在于，所述确定所述第一通道的串行数字接口的时钟信号在所述第一延时单元的第一延时参数，包括：14. The device according to any one of claims 11 to 13, characterized in that the step of determining a first delay parameter of a clock signal of a serial digital interface of the first channel in the first delay unit comprises: 设置所述第一延时单元的输入信号延时器的初始延时参数；Setting the initial delay parameter of the input signal delay of the first delay unit; 持续采集所述第一延时单元中的预设串并转换器得到的转换信号，在所述转换信号为第一预设值或第二预设值的情况下，以预设步长增加所述延时参数；或在所述转换信号不为所述第一预设值或所述第二预设值、且与前一转换信号不同的情况下，记录当前延时参数，并以所述预设步长增加所述延时参数；Continuously collecting a conversion signal obtained by a preset serial-to-parallel converter in the first delay unit, and when the conversion signal is a first preset value or a second preset value, increasing the delay parameter by a preset step length; or when the conversion signal is not the first preset value or the second preset value and is different from a previous conversion signal, recording a current delay parameter and increasing the delay parameter by the preset step length; 当所述延时参数达到最大延时参数时，利用记录的多个延时参数得到所述第一延时参数。When the delay parameter reaches a maximum delay parameter, the first delay parameter is obtained by using a plurality of recorded delay parameters. 15.根据权利要求11～13任一项所述的设备，其特征在于，所述确定当所述第二通道的数据能够被所述第一通道的串行数字接口的时钟信号正确采集时，所述第二通道的数据信号在所述第二延时单元的第二延时参数，包括：15. The device according to any one of claims 11 to 13, characterized in that the determining, when the data of the second channel can be correctly collected by the clock signal of the serial digital interface of the first channel, the second delay parameter of the data signal of the second channel in the second delay unit comprises: 设置所述第二延时单元的输入信号延时器的初始延时参数；Setting the initial delay parameter of the input signal delay of the second delay unit; 在各个周期均连续采集所述第二通道的预设串并转换器输出的多个数据，若所述多个数据未被正确采样，则以预设步长增加所述延时参数；或若所述多个数据被正确采样，则记录当前延时参数，并以所述预设步长增加所述延时参数；Continuously collecting a plurality of data outputted by the preset serial-to-parallel converter of the second channel in each cycle, and if the plurality of data are not correctly sampled, increasing the delay parameter by a preset step length; or if the plurality of data are correctly sampled, recording the current delay parameter, and increasing the delay parameter by the preset step length; 当所述延时参数达到最大延时参数时，利用记录的多个延时参数得到所述第二延时参数。When the delay parameter reaches a maximum delay parameter, the second delay parameter is obtained by using a plurality of recorded delay parameters. 16.根据权利要求11所述的设备，其特征在于，所述设备还用于：16. The device according to claim 11, characterized in that the device is also used for: 根据所述第一通道的延时后的串行数字接口的时钟信号与延时前的串行数字接口的时钟信号的对齐方式及预设延时单元中的转换组件输出的转换信号，对所述第一通道及所述第二通道的延时参数进行动态调整。The delay parameters of the first channel and the second channel are dynamically adjusted according to the alignment method of the clock signal of the serial digital interface after delay and the clock signal of the serial digital interface before delay and the conversion signal output by the conversion component in the preset delay unit. 17.根据权利要求16所述的设备，其特征在于，所述根据所述第一通道的延时后的串行数字接口的时钟信号与延时前的串行数字接口的时钟信号的对齐方式及预设延时单元中的转换组件输出的转换信号，对所述第一通道及所述第二通道的延时参数进行动态调整，包括：17. The device according to claim 16, characterized in that the delay parameters of the first channel and the second channel are dynamically adjusted according to the alignment mode of the clock signal of the serial digital interface after the delay of the first channel and the clock signal of the serial digital interface before the delay and the conversion signal output by the conversion component in the preset delay unit, comprising: N次采集转换信号，N＞1且为整数；Collect and convert signals N times, where N>1 and is an integer; 如果N个转换信号都为第一预设值且所述对齐方式为上升沿对齐，则增加所述第一通道和所述第二通道的延时参数；If the N conversion signals are all the first preset values and the alignment mode is rising edge alignment, then increasing the delay parameters of the first channel and the second channel; 如果N个转换信号都为所述第一预设值且所述对齐方式为下降沿对齐，则减小所述第一通道和所述第二通道的延时参数；If the N conversion signals are all the first preset values and the alignment mode is falling edge alignment, reducing the delay parameters of the first channel and the second channel; 如果N个转换信号都为第二预设值且所述对齐方式为上升沿对齐，则减小所述第一通道和所述第二通道的延时参数；If the N conversion signals are all the second preset values and the alignment mode is rising edge alignment, reducing the delay parameters of the first channel and the second channel; 如果N个转换信号都为所述第二预设值且所述对齐方式为下降沿对齐，则增加所述第一通道和所述第二通道的延时参数；If the N conversion signals are all the second preset values and the alignment mode is falling edge alignment, then increase the delay parameters of the first channel and the second channel; 如果N个转换信号中出现至少一次大于第一预设值且小于第二预设值的值，则不改变所述第一通道和所述第二通道的延时参数。If a value greater than the first preset value and less than the second preset value appears at least once in the N conversion signals, the delay parameters of the first channel and the second channel are not changed.
CN202310763251.4A 2023-06-26 2023-06-26 Multi-channel serial digital interface timing alignment adjustment method, device and equipment Pending CN119201816A (en)

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